Advanced Vector Extensions (AVX, also known asGesher New Instructions and thenSandy Bridge New Instructions) areSIMD extensions to thex86instruction set architecture formicroprocessors fromIntel andAdvanced Micro Devices (AMD). They were proposed by Intel in March 2008 and first supported by Intel with theSandy Bridge[1] microarchitecture shipping in Q1 2011 and later by AMD with theBulldozer[2] microarchitecture shipping in Q4 2011. AVX provides new features, new instructions, and a new coding scheme.
AVX2 (also known asHaswell New Instructions) expands most integer commands to 256 bits and introduces new instructions. They were first supported by Intel with theHaswell microarchitecture, which shipped in 2013.
AVX-512 expands AVX to 512-bit support using a newEVEX prefix encoding proposed by Intel in July 2013 and first supported by Intel with theKnights Landing co-processor, which shipped in 2016.[3][4] In conventional processors, AVX-512 was introduced withSkylake server and HEDT processors in 2017.
AVX uses sixteen YMM registers to perform a single instruction on multiple pieces of data (seeSIMD). Each YMM register can hold and do simultaneous operations (math) on:
The width of the SIMD registers is increased from 128 bits to 256 bits, and renamed from XMM0–XMM7 to YMM0–YMM7 (inx86-64 mode, from XMM0–XMM15 to YMM0–YMM15). The legacySSE instructions can still be utilized via theVEX prefix to operate on the lower 128 bits of the YMM registers.
| 511256 | 255128 | 1270 |
| ZMM0 | YMM0 | XMM0 |
| ZMM1 | YMM1 | XMM1 |
| ZMM2 | YMM2 | XMM2 |
| ZMM3 | YMM3 | XMM3 |
| ZMM4 | YMM4 | XMM4 |
| ZMM5 | YMM5 | XMM5 |
| ZMM6 | YMM6 | XMM6 |
| ZMM7 | YMM7 | XMM7 |
| ZMM8 | YMM8 | XMM8 |
| ZMM9 | YMM9 | XMM9 |
| ZMM10 | YMM10 | XMM10 |
| ZMM11 | YMM11 | XMM11 |
| ZMM12 | YMM12 | XMM12 |
| ZMM13 | YMM13 | XMM13 |
| ZMM14 | YMM14 | XMM14 |
| ZMM15 | YMM15 | XMM15 |
| ZMM16 | YMM16 | XMM16 |
| ZMM17 | YMM17 | XMM17 |
| ZMM18 | YMM18 | XMM18 |
| ZMM19 | YMM19 | XMM19 |
| ZMM20 | YMM20 | XMM20 |
| ZMM21 | YMM21 | XMM21 |
| ZMM22 | YMM22 | XMM22 |
| ZMM23 | YMM23 | XMM23 |
| ZMM24 | YMM24 | XMM24 |
| ZMM25 | YMM25 | XMM25 |
| ZMM26 | YMM26 | XMM26 |
| ZMM27 | YMM27 | XMM27 |
| ZMM28 | YMM28 | XMM28 |
| ZMM29 | YMM29 | XMM29 |
| ZMM30 | YMM30 | XMM30 |
| ZMM31 | YMM31 | XMM31 |
AVX introduces a three-operand SIMD instruction format calledVEX coding scheme, where the destination register is distinct from the two source operands. For example, anSSE instruction using the conventional two-operand forma ←a +b can now use a non-destructive three-operand formc ←a +b, preserving both source operands. Originally, AVX's three-operand format was limited to the instructions with SIMD operands (YMM), and did not include instructions with general purpose registers (e.g. EAX). It was later used for coding new instructions on general purpose registers in later extensions, such asBMI. VEX coding is also used for instructions operating on the k0-k7 mask registers that were introduced withAVX-512.
Thealignment requirement of SIMD memory operands is relaxed.[5] Unlike their non-VEX coded counterparts, most VEX coded vector instructions no longer require their memory operands to be aligned to the vector size. Notably, theVMOVDQA instruction still requires its memory operand to be aligned.
The newVEX coding scheme introduces a new set of code prefixes that extends theopcode space, allows instructions to have more than two operands, and allows SIMD vector registers to be longer than 128 bits. The VEX prefix can also be used on the legacy SSE instructions giving them a three-operand form, and making them interact more efficiently with AVX instructions without the need forVZEROUPPER andVZEROALL.
The AVX instructions support both 128-bit and 256-bit SIMD. The 128-bit versions can be useful to improve old code without needing to widen the vectorization, and avoid the penalty of going from SSE to AVX, they are also faster on some early AMD implementations of AVX. This mode is sometimes known as AVX-128.[6]
These AVX instructions are in addition to the ones that are 256-bit extensions of the legacy 128-bit SSE instructions; most are usable on both 128-bit and 256-bit operands.
| Instruction | Description |
|---|---|
VBROADCASTSS,VBROADCASTSD,VBROADCASTF128 | Copy a 32-bit, 64-bit or 128-bit memory operand to all elements of a XMM or YMM vector register. |
VINSERTF128 | Replaces either the lower half or the upper half of a 256-bit YMM register with the value of a 128-bit source operand. The other half of the destination is unchanged. |
VEXTRACTF128 | Extracts either the lower half or the upper half of a 256-bit YMM register and copies the value to a 128-bit destination operand. |
VMASKMOVPS,VMASKMOVPD | Conditionally reads any number of elements from a SIMD vector memory operand into a destination register, leaving the remaining vector elements unread and setting the corresponding elements in the destination register to zero. Alternatively, conditionally writes any number of elements from a SIMD vector register operand to a vector memory operand, leaving the remaining elements of the memory operand unchanged. On the AMD Jaguar processor architecture, this instruction with a memory source operand takes more than 300 clock cycles when the mask is zero, in which case the instruction should do nothing. This appears to be a design flaw.[7] |
VPERMILPS,VPERMILPD | Permute In-Lane. Shuffle the 32-bit or 64-bit vector elements of one input operand. These are in-lane 256-bit instructions, meaning that they operate on all 256 bits with two separate 128-bit shuffles, so they can not shuffle across the 128-bit lanes.[8] |
VPERM2F128 | Shuffle the four 128-bit vector elements of two 256-bit source operands into a 256-bit destination operand, with an immediate constant as selector. |
VTESTPS,VTESTPD | Packed bit test of the packed single-precision or double-precision floating-point sign bits, setting or clearing the ZF flag based on AND and CF flag based on ANDN. |
VZEROALL | Set all YMM registers to zero and tag them as unused. Used when switching between 128-bit use and 256-bit use. |
VZEROUPPER | Set the upper half of all YMM registers to zero. Used when switching between 128-bit use and 256-bit use. |
Issues regarding compatibility between future Intel and AMD processors are discussed underXOP instruction set.
AVX adds new register-state through the 256-bit wide YMM register file, so explicitoperating system support is required to properly save and restore AVX's expanded registers betweencontext switches. The following operating system versions support AVX:
Advanced Vector Extensions 2 (AVX2), also known asHaswell New Instructions,[24] is an expansion of the AVX instruction set introduced in Intel'sHaswell microarchitecture. AVX2 makes the following additions:
Sometimes three-operandfused multiply-accumulate (FMA3) extension is considered part of AVX2, as it was introduced by Intel in the same processor microarchitecture. This is a separate extension using its ownCPUID flag and is described onits own page and not below.
| Instruction | Description |
|---|---|
VBROADCASTSS,VBROADCASTSD | Copy a 32-bit or 64-bit register operand to all elements of a XMM or YMM vector register. These are register versions of the same instructions in AVX1. There is no 128-bit version, but the same effect can be simply achieved using VINSERTF128. |
VPBROADCASTB,VPBROADCASTW,VPBROADCASTD,VPBROADCASTQ | Copy an 8, 16, 32 or 64-bit integer register or memory operand to all elements of a XMM or YMM vector register. |
VBROADCASTI128 | Copy a 128-bit memory operand to all elements of a YMM vector register. |
VINSERTI128 | Replaces either the lower half or the upper half of a 256-bit YMM register with the value of a 128-bit source operand. The other half of the destination is unchanged. |
VEXTRACTI128 | Extracts either the lower half or the upper half of a 256-bit YMM register and copies the value to a 128-bit destination operand. |
VGATHERDPD,VGATHERQPD,VGATHERDPS,VGATHERQPS | Gathers single- or double-precision floating-point values using either 32- or 64-bit indices and scale. |
VPGATHERDD,VPGATHERDQ,VPGATHERQD,VPGATHERQQ | Gathers 32 or 64-bit integer values using either 32- or 64-bit indices and scale. |
VPMASKMOVD,VPMASKMOVQ | Conditionally reads any number of elements from a SIMD vector memory operand into a destination register, leaving the remaining vector elements unread and setting the corresponding elements in the destination register to zero. Alternatively, conditionally writes any number of elements from a SIMD vector register operand to a vector memory operand, leaving the remaining elements of the memory operand unchanged. |
VPERMPS,VPERMD | Shuffle the eight 32-bit vector elements of one 256-bit source operand into a 256-bit destination operand, with a register or memory operand as selector. |
VPERMPD,VPERMQ | Shuffle the four 64-bit vector elements of one 256-bit source operand into a 256-bit destination operand, with a register or memory operand as selector. |
VPERM2I128 | Shuffle (two of) the four 128-bit vector elements oftwo 256-bit source operands into a 256-bit destination operand, with an immediate constant as selector. |
VPBLENDD | Doubleword immediate version of the PBLEND instructions fromSSE4. |
VPSLLVD,VPSLLVQ | Shift left logical. Allows variable shifts where each element is shifted according to the packed input. |
VPSRLVD,VPSRLVQ | Shift right logical. Allows variable shifts where each element is shifted according to the packed input. |
VPSRAVD | Shift right arithmetically. Allows variable shifts where each element is shifted according to the packed input. |
AVX-512 are 512-bit extensions to the 256-bit Advanced Vector Extensions SIMD instructions for x86 instruction set architecture proposed byIntel in July 2013.[3]
AVX-512 instructions are encoded with the newEVEX prefix. It allows 4 operands, 8 new 64-bitopmask registers, scalar memory mode with automatic broadcast, explicit rounding control, and compressed displacement memoryaddressing mode. The width of the register file is increased to 512 bits and total register count increased to 32 (registers ZMM0-ZMM31) in x86-64 mode.
AVX-512 consists of multiple instruction subsets, not all of which are meant to be supported by all processors implementing them. The instruction set consists of the following:
Only the core extension AVX-512F (AVX-512 Foundation) is required by all implementations, though all current implementations also support CD (conflict detection). All central processors with AVX-512 also support VL, DQ and BW. The ER, PF, 4VNNIW and 4FMAPS instruction set extensions are currently only implemented in Intel computing coprocessors.
The updated SSE/AVX instructions in AVX-512F use the same mnemonics as AVX versions; they can operate on 512-bit ZMM registers, and will also support 128/256 bit XMM/YMM registers (with AVX-512VL) and byte, word, doubleword and quadword integer operands (with AVX-512BW/DQ and VBMI).[26]: 23
Subset | F | CD | ER | PF | 4FMAPS | 4VNNIW | VPOPCNTDQ | VL | DQ | BW | IFMA | VBMI | VBMI2 | BITALG | VNNI | BF16 | VPCLMULQDQ | GFNI | VAES | VP2INTERSECT | FP16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| IntelKnights Landing (2016) | Yes | Yes | No | ||||||||||||||||||
| IntelKnights Mill (2017) | Yes | No | |||||||||||||||||||
| IntelSkylake-SP,Skylake-X (2017) | No | No | Yes | No | |||||||||||||||||
| IntelCannon Lake (2018) | Yes | No | |||||||||||||||||||
| IntelCascade Lake-SP (2019) | No | Yes | No | ||||||||||||||||||
| IntelCooper Lake (2020) | No | Yes | No | ||||||||||||||||||
| IntelIce Lake (2019) | Yes | No | Yes | No | |||||||||||||||||
| IntelTiger Lake (2020) | Yes | No | |||||||||||||||||||
| IntelRocket Lake (2021) | No | ||||||||||||||||||||
| IntelAlder Lake (2021) | PartialNote 1 | PartialNote 1 | |||||||||||||||||||
| AMDZen 4 (2022) | Yes | Yes | No | ||||||||||||||||||
| IntelSapphire Rapids (2023) | No | Yes | |||||||||||||||||||
| AMDZen 5 (2024) | Yes | No | |||||||||||||||||||
^Note 1 : Intel does not officially support AVX-512 family of instructions on theAlder Lake microprocessors. In early 2022, Intel began disabling in silicon (fusing off) AVX-512 in Alder Lake microprocessors to prevent customers from enabling AVX-512.[29]In older Alder Lake family CPUs with some legacy combinations of BIOS and microcode revisions, it was possible to execute AVX-512 family instructions when disabling all the efficiency cores which do not contain the silicon for AVX-512.[30][31][32]
AVX-VNNI is aVEX-coded variant of theAVX512-VNNI instruction set extension. Similarly, AVX-IFMA is aVEX-coded variant ofAVX512-IFMA. These extensions provide the same sets of operations as their AVX-512 counterparts, but are limited to 256-bit vectors and do not support any additional features ofEVEX encoding, such as broadcasting, opmask registers or accessing more than 16 vector registers. These extensions allow support of VNNI and IFMA operations even when fullAVX-512 support is not implemented in the processor.
AVX10, announced in July 2023,[38] is a new, "converged" AVX instruction set. It addresses several issues of AVX-512, in particular that it is split into too many parts[39] (20 feature flags). The initial technical paper also made 512-bit vectors optional to support, but as of revision 3.0 vector length enumeration is removed and 512-bit vectors are mandatory.[40]
AVX10 presents a simplified CPUID interface to test for instruction support, consisting of the AVX10 version number (indicating the set of instructions supported, with later versions always being a superset of an earlier one).[41] For example, AVX10.2 indicates that a CPU is capable of the second version of AVX10.[42] Initial revisions of the AVX10 technical specifications also included maximum supported vector length as part of the ISA extension name, e.g. AVX10.2/256 would mean a second version of AVX10 with vector length up to 256 bits, but later revisions made that unnecessary.
The first version of AVX10, notated AVX10.1, doesnot introduce any instructions or encoding features beyond what is already in AVX-512 (specifically, in IntelSapphire Rapids: AVX-512F, CD, VL, DQ, BW, IFMA, VBMI, VBMI2, BITALG, VNNI, GFNI, VPOPCNTDQ, VPCLMULQDQ, VAES, BF16, FP16). For CPUs supporting AVX10 and 512-bit vectors, all legacy AVX-512 feature flags will remain set to facilitate applications supporting AVX-512 to continue using AVX-512 instructions.[42]
AVX10.1 was first released in IntelGranite Rapids[42] (Q3 2024) and AVX10.2 will be available inDiamond Rapids.[43]
APX is a new extension. It is not focused on vector computation, but provides RISC-like extensions to the x86-64 architecture by doubling the number of general-purpose registers to 32 and introducing three-operand instruction formats. AVX is only tangentially affected as APX introduces extended operands.[44][45]
Since AVX instructions are wider, they consume more power and generate more heat. Executing heavy AVX instructions at high CPU clock frequencies may affect CPU stability due to excessivevoltage droop during load transients. Some Intel processors have provisions to reduce theTurbo Boost frequency limit when such instructions are being executed. This reduction happens even if the CPU hasn't reached its thermal and power consumption limits.
OnSkylake and its derivatives, the throttling is divided into three levels:[66][67]
The frequency transition can be soft or hard. Hard transition means the frequency is reduced as soon as such an instruction is spotted; soft transition means that the frequency is reduced only after reaching a threshold number of matching instructions. The limit is per-thread.[66]
InIce Lake, only two levels persist:[68]
Rocket Lake processors do not trigger frequency reduction upon executing any kind of vector instructions regardless of the vector size.[68] However, downclocking can still happen due to other reasons, such as reaching thermal and power limits.
Downclocking means that using AVX in a mixed workload with an Intel processor can incur a frequency penalty. Avoiding the use of wide and heavy instructions help minimize the impact in these cases. AVX-512VL allows for using 256-bit or 128-bit operands in AVX-512 instructions, making it a sensible default for mixed loads.[69]
On supported and unlocked variants of processors that down-clock, the clock ratio reduction offsets (typically called AVX and AVX-512 offsets) are adjustable and may be turned off entirely (set to 0x) via Intel's Overclocking / Tuning utility or in BIOS if supported there.[70]
Memory arguments for most instructions with VEX prefix operate normally without causing #GP(0) on any byte-granularity alignment (unlike Legacy SSE instructions).
See image in linked section, where AVX2 ratio has been set to 0.