Doze Mode

Doze mode allows the application program to slow down the CPU clock while leaving the peripheral clock unchanged. When switching to Doze mode, no adjustment is needed to the individual peripheral configuration registers. The operation of the peripherals is not affected by the change in the CPU clock speed.

Entering Doze Mode

Doze Mode is controlled by the upper five bits of the Clock Divider RegisterCLKDIV<15:11>.

• The Doze Enable (DOZEN) bit causes the device to enter Doze mode.
• WhenDOZEN is set, the speed of the CPU is cycled down by the amount specified byDOZE<2:0>.
• The user has the option of restoring the CPU clock to the speed set by the configuration bits when an interrupt occurs. This allows interrupts to be processed at full speed. The Recover on Interrupt (ROI) bit controls the state of the clock for interrupt processing.

Exiting Doze Mode

Doze mode is exited by clearing theDOZEN bit.

Idle Mode

Idle mode turns off clock to the CPU but leaves the clock to the peripherals unchanged. In Idle mode, the system oscillator is left running and the data in all memory locations is retained.

Entering Idle Mode

A device is put into Idle mode by executing thePWRSAV assembly instruction with the suffix#1.

The MPLAB^® XC16 C Compiler defines a macro for PWRSAV #IDLE_MODE.

Exiting Idle Mode

The Idle mode will end and the CPU will execute the instruction immediately following the PWRSAV instruction upon the following conditions:

• A Reset condition, other than a Power-On Reset.
• A Watchdog Timer overflow.
• An interrupt request occurs with a priority less than or equal to the current priority of the CPU.

If an interrupt occurs with a priority higher than the present CPU priority, the CPU wakes up and begins execution with the interrupt service routine.

Sleep Mode

Sleep mode turns off the system clock. If enabled, the WDT will run off the LPRC. The CPU and all peripherals requiring the system clock will cease operation. The contents of the memory and registers are maintained in Sleep mode.

Entering Sleep Mode

A device is put into Sleep mode by executing thePWRSAV assembly instruction with the suffix#0.

The MPLAB^® XC16 C Compiler defines a macro for PWRSAV #SLEEP_MODE.

Exiting Sleep Mode

Sleep mode will end and the CPU will execute the instruction immediately following the PWRSAV instruction upon the following conditions:

• A Reset condition, other than a Power-On Reset.
• A WDT overflow.
• Any interrupt request occurs.

Delay in Exiting Sleep Mode

The delay associated with waking up from Sleep will vary depending upon the oscillator being used. For most oscillator settings, the delay in waking up from Sleep is the same as when the device is first powered on. Please consult the datasheet of the device you are using to determine the specific delay for the part you are using.

Low-Voltage Sleep Mode

Low-Voltage Sleep mode stops the system clock in the same way as the Sleep mode. Low-Voltage Sleep mode uses a low-voltage regulator to power the core. This mode uses less power than the Sleep mode but takes longer to wake up from sleep due to the voltage regulator.

Entering Low Voltage Sleep

The low-voltage regulator is controlled by theLPCFG/LVRCFG configuration bit (also designated asLVRCFG in some devices) and the Low-Voltage Enable bit (RETEN/LVREN), and Reset and System Control register (RCON). TheLPCFG/LVRCF configuration bit makes the low-voltage regulator available to be controlled byRCON.

With theLPCFG/LVRCFG configuration bit set, the following sequence of instructions will put the device into Low-Voltage Sleep mode:

1. Setting theLVREN bit inRCON.
2. ExecutingPWRSAV instruction with the suffix#0.

With MPLAB^® XC16 C Compiler:

Exiting Low-Voltage Sleep

Low-Voltage Sleep mode will end and the CPU will execute the instruction immediately following thePWRSAV instruction upon the following conditions:

• A Reset condition, other than a Power-On Reset.
• A WDT overflow.
• Any interrupt request.

 Learn More

Low Power Operating Modes
Deep Sleep
Clock Switching
Battery Backup (Vbat)

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