If you close theMHC window, you can re-open it again by clicking onTools > Embedded > MPLAB Harmony Configurator

If a BSP exists for your development board, you will want to use it. Choosing a BSP lets the MHC know about the hardware you will use for the project. With this knowledge, the MHC can automatically control the following settings for you:

• PIC32 core configuration (watchdog timer, debugger channel)
• PIC32 oscillator configuration (including external clock/crystal)
• PIC32 I/O Port pin connections to LEDs and switches

In addition to configuring hardware options for you, the BSP comes with a small group of library functions that allow you to more easily interface with LEDs, switches, and other board-specific hardware. In this lab, you will observe the selections the BSP makes for you. This will show you how to make these selections manually in case a BSP does not exist for the board you want to use.

In case you are wondering where these cryptic selection names come from, they correspond to the PIC32 core configuration registers and bit names.

The PIC32 is connected to a 24 MHz external clock input. You are not using the internal PIC32 oscillator.

Verify the output to the PLL is now set to 198 MHz.

If this window is minimized, it can be found at the bottom-left of the MPLAB IDE. Click on it to maximize it.

a

Check theUse Codec AK 4953? box.

b

A default value for volume is specified. You can change the value depending on your requirement.

c

Do not checkSpecify MCLK value. A default value of 256 for MCLK is selected under the I²S driver configuration (MCLK sampling rate multiplier).

d

You need to use only one client of the CODEC driver, therefore retain theNumber of AK4953 Driver Clients value as 1.

e

The AK4953 Driver supports only one instance of AK4953 CODEC module. AK4953 driver is a single instance driver. Therefore default instance ofCodec AK4953 Driver Instance 0 is selected.

f

Select theI²S driver (used for data interface) instance asDRV_I2S_INDEX_0. The AK4953 driver uses an I²S interface for the audio data transfer to/from the PIC32 microcontroller. The PIC32MZ2048EFH144 device supports multiple instances of I²S modules. Select an instance (instance 0) for audio data communication.

g

Select theDynamic I²C driver (used for control interface) instance asDRV_I2C_INDEX_0 or 0. The AK4953 driver uses the I²C interface for the audio control transfers to/from the PIC32 microcontroller. The control transfers exchange commands to/from the AK4953 CODEC to configure and/or read the initialized/existing configuration. The PIC32MZ2048EFH144 device supports multiple instances of I²C modules. Select an instance (instance 0) for audio control communication.

CODEC devices need a fine clock source to generate accurate audio sampling rates. The clock source (MCLK from the CODEC device’s perspective) can be generated internally by the CODEC device.

a

TheUse I²C Driver? is checked by default. This is done since the AK4953 CODEC driver uses the I²C driver.

b

SelectDynamic for theDriver Implementation. A dynamic I²C driver implementation is selected because you will need a second I²C instance in Lab5. The I²C in Lab5 is used to interface to the touch panel.

c

Check theInterrupt mode option. The Interrupt mode option is selected so that the I²C data completion events can be detected asynchronously without the need for polling for the transfer to complete. This is necessary because, by the end of Lab5, the application will add a number of Harmony drivers, system services, and middleware. All these Harmony modules have to cooperatively run without blocking the processor so that the functionality of other modules does not get affected.

d

Retain default value of 1 set forNumber of I²C Driver Clients andNumber of I²C Driver Instances. At this point, I²C is used only to interface with the AK4953 CODEC. These values will be changed later in one of the following labs when more instances of I²C modules are used.

e

CheckInclude Force Write I²C Function. This will include an Application Programming Interface (API) that sends data to Slave even if the Slave NACKs data. This is needed by the AK4953 CODEC since it NACKs I²C data during the initialization sequence.

f

UnderI²C Driver Instance 0, retainUse Bit Bang I²C Implementation? unchecked. Since you are using the hardware I²C instances, you will use the driver for the real hardware instead of a bit banged driver implementation.

g

SelectI2C_ID_2 asI²C Module ID.

h

Retain default valueDRV_I2C_MODE_MASTER asOperation Mode. The PIC32 I²C module 2 will act as Master and the AK4953 CODEC module control interface (I²C) will act as a Slave.

i

Retain default values forMaster Interrupt Priority andMaster Interrupt Sub-priority asINT_PRIORITY_LEVEL1 andINT_SUBPRIORITY_LEVEL0 respectively. You will want CODEC I²C events to be signaled at higher priority.

j

Retain default value forError Interrupt Priority andError Interrupt Sub-priority asINT_PRIORITY_LEVEL1 andINT_SUBPRIORITY_LEVEL0 respectively.

k

Baud Rate Generator Clock is configured to 99 MHz; this is derived from the peripheral bus 2 clock frequency generated from 198 MHz system clock.

l

Retain default value of 50 KHz forI²C CLOCK FREQUENCY. The AK4953 CODEC supports fast I²C control interface (up to 400 KHz).

m

RetainSlew Rate Control unchecked. This function enables the I²C module to use high-frequency signaling, allowing it to use the 400 kHz and 1 MHz signaling rates.

n

Retain default value ofSYS_MODULE_POWER_RUN_FULL forPower State. You will want to run the I²C module in Normal Power mode.

o

Verify/set the I/O Pins used by I²C module using the Graphical Pin Manager.
Select MHC'sPin Diagram sub-tab. Also, select thePin table tab in the MHC output pane (bottom of IDE window).
The I²C2 has dedicated pins for SCL2 and SDA2 signals. These pins are hard-coded and configured by the I²C driver.

a

TheUse I²S Driver? is checked by default. This is done since the AK4953 CODEC driver uses the I²S driver.

b

Expand theUse I²S Driver? option.

c

TheDynamic Driver Implementation is selected by default and is greyed out. The I²S driver does not support static implementation yet.

d

Check theDMA Mode of operation. Under Direct Memory Access (DMA) mode check,Transmit DMA Support. TheEnable DMA Channel Interrupts? option is checked by default.
Transmit DMA Support is enabled to use DMA channels to transfer audio data from memory to I²S buffers. The DMA channel is interrupt enabled to allow DMA transfer completion notification.

e

RetainStop in Idle Mode as it is.

f

Retain defaultSampling Rate as 48000. This is the initial value of sampling rate.

g

Retain default value of 256 forMCLK Sampling Rate Multiplier. The AK4953 CODEC supports 256 fs with 48000 Hz sampling rate for generating the REFCLOCK.

h

Retain default value of 4 forMaster Clock/Bit Clock ratio.
For sampling Rate 48000 Hz, and MCLK sampling rate multiplier value of 256, The MCLK or REFCLOCK = 256 * 48000 = 12288000 Hz. The common Bit Clock (BCLK) that can be generated for the given combination of MCLK and Sampling rate would be REFCLOCK/1, REFCLOCK/2, REFCLOCK/4 or REFCLOCK/8.
For example, AK4953 CODEC supports BCLK value as either 32 fs or 64 fs. For 48000 Hz sampling rate, the BCLK would be 64 * 48000 = 3072000 Hz. Therefore, the MCLK/BCLK ratio is 12288000/3072000 = 4.

i

Retain default value of 1 set forNumber of I²S Driver Clients andNumber of I²S Driver Instances. You are using the I²S interface only for audio playback, therefore one instance of I²S driver and its client is sufficient.

j

UnderI²S Driver Instance 0, retainSPI_ID_1 asI²S Module ID. I²S module instance 1 is interfaced to the AK4953 CODEC’s data lines.

k

Retain default value ofUsage Mode asDRV_I2S_MODE_MASTER. It indicates whether the I²S instance would act as a Master or Slave. In Master mode, the PIC32 generates the BCLK to the Slave. In Slave mode, the PIC32 receives BCLK from the I²S Master. In the interface to AK4953 CODEC, the PIC32 I²S will act as a Master and hence, generates the BCLK.

l

Retain default value ofBaud Clock asSPI_BAUD_RATE_MCLK_CLOCK. This Indicates that the system clock of 198 MHz is used to generate the baud rate.

m

Retain default value ofClock Mode asDRV_I2S_CLOCK_MODE_IDLE_HIGH_EDGE_FALL. This is the default polarity for the I²S protocol.

n

ChangeAudio Communication Width toSPI_AUDIO_COMMUNICATION_16DATA_16FIFO_32CHANNEL. In the scope of these labs, you are supporting CD quality audio playback, therefore setting 16-bit audio data per channel, 32-bit channel width.

o

Retain default value ofAudio Mode asSPI_AUDIO_TRANSMIT_STEREO. The labs support stereo audio playback.

p

Retain default value ofInput Sample Phase Selection asSPI_INPUT_SAMPLING_PHASE_IN_MIDDLE. This is the default phase for the I²S protocol.

q

Retain default value ofAudio Protocol Mode asDRV_I2S_AUDIO_I2S. You chose the I²S protocol interface mode supported by the AK4953 CODEC.

r

RetainQueue Size Transmit to 3. You will queue up to three audio buffer objects at a time.

s

SetQueue Size Receive to 1. The receive path is not used. Set a minimal value of 1 buffer object.

t

RetainTransmit DMA Channel Instance to 0. You are using DMA channel instance 0 for audio data transfer.

u

Retain default value ofSYS_MODULE_POWER_RUN_FULL forPower State. You will want to run the I²S module in normal power mode.

a

Expand theMPLAB Harmony Configurator > Options > System Services > Clock selection tree.

b

ExpandUse Clock System Service?

c

Click theExecute button besideLaunch Clock Configurator.

d

Locate theReference Clock block. By default theReference Clock #1 tab is selected. Reference Clock #1 enables configuring the reference clock to Serial Peripheral Interface (SPI)/I²S, Peripheral Pin Select (PPS).

e

Check theON box as shown in the following image. This enables the reference clock circuitry.

f

SelectSPLL asROSEL1. The system PLL is used as the source clock for generating the reference clock.

g

Click theAuto-Calculate button to generate the Reference Clock #1. This will open up theReference Clock Divider and Trim Auto Calculator window.

h

Verify that theReference Clock Divisor andTrim Auto Calculator show the desired reference clock and sampling values to be generated. The values are generated from the MCLK multiplier and sampling rate specified in CODEC/I²S driver configuration.

i

Select the radio buttonTarget I²S Input Frequency then click theApply button. The Target I²S Input Frequency is the reference clock input to the AK4953 CODEC.

j

Check theOE box to enable the Reference Clock #1 output.

a

Expand theMPLAB Harmony Configurator > Options > System Services > DMA selection tree.

b

Expand theUse DMA System Service? tree.

c

RetainSelect Service Mode asDynamic. You will need a dynamic driver for the following labs when more DMA channels are used.

d

Retain theNumber of DMA Channel Instances to 1. One DMA channel instance is used by I²S.

e

ExpandDMA Channel Instance 0. This is the instance set by I²S driver for transferring audio data.

f

UnderDMA Channel, selectDMA_CHANNEL_2. You will use DMA Channel 2 for I²S data transfer.

g

RetainInterrupt Priority andInterrupt Sub-Priority asINT_PRIORITY_LEVEL1 andINT_SUBPRIORITY_LEVEL0 respectively. You will want I²S data transfer events (DMA) to have a higher priority.

a

Map the REFCLOCK1 signal to pin RD15 as shown in the following image. For schematic, refer to the Multimedia Expansion Board II (MEB II) User’s Guide

b

The I²S1 has a dedicated pin for SCK1 signal. This pin is hardcoded and configured by the I²S driver.

c

Map I²S1 signals SDI1, SDO1 and SS1(out) signals to pins RD14, RB10 and RF12 as shown in the following image. For schematic, refer to the Multimedia Expansion Board II (MEB II) User’s Guide.

At this point, you should be able to debug and step through the application. Effectively, you have a running MPLAB Harmony system. However, it is not yet ready to do anything. Next, you will develop your application state machine logic and make sure the system does what you want it to do. You’re ready to start implementing the application now.