Audio Sine Tone Tutorial: Step 3

The added ASF modules have default configurations. The following sections customize some of the module configurations.

Step 3.1: Configure GPIO for TWI and USART

1

In theSolution Explorer, Under thesrc/config folder, open the header fileconf_board.h

2

Add the macrosCONF_BOARD_TWIHS0 andCONF_BOARD_UART_CONSOLE

image16.png

The macroCONF_BOARD_TWIHS0 enables the board initialization code to map GPIO pins to be used by TWI peripheral. The TWI interface is used by the WM8904 Audio Codec component as the command interface to exchange configuration data with the CODEC WM8904.

The macroCONF_BOARD_UART_CONSOLE enables the board initialization code to map GPIO pins to be used by USART peripheral. The USART interface is used by the standard I/O service to implement a debugging console function.

Step 3.2: Configure the System Clock

1

In theSolution Explorer, Undersrc/config folder, Open the header fileconf_clock.h

2

Modify the macroCONFIG_PLL0_MUL to "20"

image17.png

MacroCONFIG_PLL0_MUL is a multiplier to the PLL source to generate the required processor and system clock. In a default configuration, the processor and system clock are computed as follows:

  • Target frequency (Processor clock)
  • XTAL frequency: 12 MHz
  • System clock source: PLLA
  • System clock prescaler: 1 (divided by 1)
  • System clock divider: 2 (divided by 2)
  • PLLA source: XTAL
  • PLLA output: XTAL * 25 / 1
  • Processor clock: 12 * 25 / 1 / 1 = 300 MHz
  • System clock: 300 / 2 = 150 MHz

For this application, you will generate a system clock of 120 MHz. This is because a system clock of 120 MHz would provide an appropriate input clock to SSC module so that the bit clock (TK) and sampling rate (TF) generated by the SSC module has a minimal error.

To generate a system clock of 120 MHz, the multiplier to the PLL source needs to be 20 instead of 25. Therefore, the macroCONFIG_PLL0_MUL is modified as "20".

Processor and system clock computation with the modified multiplier value of 20:

  • XTAL frequency: 12 MHz
  • System clock source: PLLA
  • System clock prescaler: 1 (divided by 1)
  • System clock divider: 2 (divided by 2)
  • PLLA source: XTAL
  • PLLA output: XTAL * 20 / 1
  • Processor clock: 12 * 20 / 1 / 1 = 240 MHz
  • System clock: 240 / 2 = 120 MHz

Step 3.3: Configure USART for Debug Console

1

In theSolution Explorer, Under thesrc/config folder, open the header fileconf_uart_serial.h

2

Uncomment the commented reference settings for the USART

image18.png

3

You are done with adding the custom configurations. Save all the files and verify the application builds successfully by clickingimage19.png



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