AVR® ADC Noise Reduction Mode

AVR® devices have an Analog to Digital Converter (ADC) Noise Reduction mode, that stops the CPU and all I/O modules except asynchronous timer, PTC, and ADC, to minimize switching noise during ADC conversions. It's used when a high-resolution ADC measurement is required. ADC measurements are then implemented when the core is put to sleep.

Entering/Exiting ADC Noise Reduction

The SLEEP instruction makes the MCU enter ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, the two-wire Serial Interface address watch, Timer1, and the Watchdog to continue operating (if enabled). This sleep mode basically halts clkI/O, clkCPU, and clkFLASH, while allowing the other clocks to run. This improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC is enabled, a conversion starts automatically when this mode is entered.

adcnoise.png

Apart from the ADC Conversion Complete interrupt, only these events can wake up the MCU from ADC Noise Reduction mode:

  • External Reset
  • Watchdog System Reset
  • Watchdog Interrupt
  • Brown-out Reset
  • Two-wire Serial Interface address match
  • Timer/Counter interrupt
  • SPM/EEPROM ready interrupt
  • External level interrupt on INT
  • Pin change interrupt
​

Note: Timer/Counter only keeps running in asynchronous mode.

Additional Information