Timer0 Interrupt

The TMR0IF interrupt flag bit of the INTCON register is set every time the TMR0 register overflows from FFh to 00h, regardless of whether or not the Timer0 interrupt is enabled. This allows the software to poll the bit asynchronously. The TMR0IF bit is not automatically reset, it needs to be cleared in the software.

To enable the automatic interrupt, the Timer0 interrupt enable bit (TMR0IE) of the INTCON register must be set to '1'.

With the interrupt enabled, when the TMR0 register overflows, the CPU will direct execution to the interrupt vector which needs to hold the address of the software interrupt routine. When the overflow occurs, the Interrupt Service Routine (ISR) can preload the TMR0 register and then clear the TMR0IF bit.