dsPIC33CH Architecture Overview
dsPIC33CH Features
- Dual Independent Cores
- Master Core intended for communications and supervisory control
- High-speed Slave Core intended for time-critical control applications such as SMPS or motor control
- Each core has its own peripheral set
- Intercore communications through low-latencymailboxes
- Configurable cross-core fault and interrupt signals
- Reconfigurable pins through Microchip's Peripheral Pin Select
Programming Considerations
An application is written for each core. Both applications are combined by the IDE into one HEX file and programmed into the device's flash program memory. At start-up, before the user application runs, the compiler inserted start-up code copies the slave application from program flash to the high-speed PRAM for execution by the Slave Core.
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Procedure
Steps Needed to Program the dsPIC33CH
