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SRAM arrays with built-in parity computation for real-time error detection in cache tag arrays

Tipus de documentText en actes de congrés
Data publicació2021
EditorInstitute of Electrical and Electronics Engineers (IEEE)
Condicions d'accésAccés obert
Tots els drets reservats. Aquesta obra està protegida pels drets de propietat intel·lectual i industrial corresponents. Sense perjudici de les exempcions legals existents, queda prohibida la seva reproducció, distribució, comunicació pública o transformació sense l'autorització de la persona titular dels drets
Abstract
This work proposes an SRAM array with built-in real-time error detection (RTD) capabilities. Each cell in the new RTD-SRAM array computes its part of the real-time parity of an SRAM array column on-the-fly. RTD based arrays detect a fault right away after it occurs, rather than when it is read. RTD, therefore, breaks the serialization between data access and error detection and, thus, it can speed-up the access-time of arrays that use on-the-fly error detection and correction. The paper presents an analysis and optimization of an RTD-SRAM and its application to a tag array. Compared to a state-of-the-art tag array protection, the evaluated scheme has comparable error detection and correction strength and, depending on the array dimensions, the access time is reduced by 5% to 18%, energy by 20% to 40% and area up to 30%.
CitacióCanal, R.; Sazeides, Y.; Bramnik, A. SRAM arrays with built-in parity computation for real-time error detection in cache tag arrays. A: Design, Automation and Test in Europe Conference and Exhibition. "Proceedings of the 2021 Design, Automation & Test in Europe (DATE 2021): 01-05 February 2021, virtual conference". Institute of Electrical and Electronics Engineers (IEEE), 2021, p. 711-716. ISBN 978-3-9819263-5-4. DOI 10.23919/DATE51398.2021.9473986. 
ISBN978-3-9819263-5-4

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