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Journal of Optical Communications and Networking
Vol. 9,
Issue 4,
pp. C76-C87
(2017)
•https://doi.org/10.1364/JOCN.9.000C76

Simulation and FPGA-Based Implementation of Iterative Parallel Schedulers for Optical Interconnection Networks

Isabella Cerutti, Jan Alain Corvera, Samuel Matthew Dumlao, Rosula Reyes, Piero Castoldi, and Nicola Andriolli

Author Information

Author Affiliations

Isabella Cerutti,¹Jan Alain Corvera,²Samuel Matthew Dumlao,²Rosula Reyes,²Piero Castoldi,¹and Nicola Andriolli¹

¹I. Cerutti (e-mail: i.cerutti@sssup.it), P. Castoldi, and N. Andriolli are with Scuola Superiore Sant’Anna, Pisa, Italy.

²A. Corvera, S. M. Dumlao, and R. Reyes are with Ateneo de Manila University, Manila, Philippines.

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Isabella Cerutti, Jan Alain Corvera, Samuel Matthew Dumlao, Rosula Reyes, Piero Castoldi, and Nicola Andriolli, "Simulation and FPGA-Based Implementation of Iterative Parallel Schedulers for Optical Interconnection Networks," J. Opt. Commun. Netw.9, C76-C87 (2017)
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About this Article
History
- Original Manuscript: October 4, 2016
- Revised Manuscript: February 6, 2017
- Manuscript Accepted: March 6, 2017
- Published: March 28, 2017
Virtual Issues
Journal of Optical Communications and Networking Photonic Networks and Devices (2017)

Abstract

High-performance interconnection networks are required for inter-board, intra-board, and on-chip data communication. With the growth of data communication, the requirements for high bandwidth density, high scalability, low latency, and low power consumption are becoming more stringent, making optical solutions appealing. Such requirements should be achieved not only by the hardware architecture but also by the electronic scheduler that is in charge of deciding the packet transmissions and controlling the optical devices. In particular, low-latency schedulers are of paramount importance—especially for optical interconnection networks whose switching capabilities may be constrained by the optical domain. This paper focuses on the hardware implementation and optimization of a scheduler suitable for optical interconnection networks. Parallel, iterative scheduling algorithms are considered for high computational efficiency. More specifically, an iterative parallel implementation of the longest-queue-first algorithm ( $i p L Q F$ ) is proposed and compared to the well-known $i S L I P$ algorithm. Hardware optimization is carried out to improve their implementation efficiency. Although $i p L Q F$ achieves better network performance in terms of packet latency, the hardware implementation indicates that $i S L I P$ stands for execution time and resource utilization in commercial field programmable gate array boards.

Full Article | PDF Article

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Journal of Optical Communications and Networking

Andrew Lord, Editor-in-Chief

TABLE I

Logical Resource Utilization for the Various Implementations (Total Resources = 424,960

	$N = 4$	$N = 8$	$N = 16$
$i p L Q F_{2}$	1% (4,622)	3% (14,378)	14% (57,970)
$i p L Q F_{1}$	1% (4,678)	3% (14,743)	14% (58,689)
$i S L I P_{3}$	$< 1 %$ (2,655)	2% (9,146)	10% (41,292)
$i S L I P_{2}$	$< 1 %$ (2,691)	2% (9,425)	10% (41,958)
$i S L I P_{1}$	$< 1 %$ (2,702)	3% (11,984)	17% (72,176)

	$N = 4$	$N = 8$	$N = 16$
I/O pins	12% (106)	22% (198)	60% (529)
Memory	2% (81,920)	8% (327,680)	33% (1,310,720)

Tables (3)

Algorithm 1

( $W$ , $R$ , $p_{H}$ , $p_{V}$ ): $M$

—————————Initialization:——————————

S_{H} = 0^{N \times 1}

;

S_{V} = 0^{1 \times N}

;

H = 0^{N \times N}

;

V = 0^{N \times N}

;

H V = 0^{N \times N}

;

for

r = 1, \dots, R

do ▹ for each iteration

for

k = 1, \dots, N

do ▹ for each port

—————–Request phase at input:——————

m = 0

;

n = 0

; ▹ input matching

S_{H} (k) = 0

then ▹ input

k

not matched

for

j = | p_{H} |, \dots {, | p_{H} + N - 1 |}_{[1, N]}

do ▹

\forall

col.

(S_{V} (j) = 0) & (m < W (k, j))

then

m = W (k, j)

;

n = j

; ▹ update max.

end if

end for

H (k, n) = 1;

▹ update

H

end if

——— Request phase at output: ————

m = 0; n = 0;

▹ output matching

S_{V} (k) = 0

then ▹ output

k

not matched

for

i = | p_{V} |, \dots, {| p_{V} + N - 1 |}_{[1, N]}

do ▹ ∀ row

(S_{H} (i) = 0 & (m < W (k, j))

then

m = W (k, j)

;

n = i

; ▹ update max.

end if

end for

V (n, k) = 1

; ▹ update

V

end if

end for

————————- Accept phase: ————————-

m = 0

;

n = 0

;

for

i = | p_{H} |, \dots, {| p_{H} + N - 1 |}_{[1, N]}

for

j = 1, \dots, N

S_{H} (i) = 0

and

S_{V} (j) = 0

then

H V (i, j) = H (i, j) \otimes V (i, j)

; ▹ AND

H V (i, j) = 1

then ▹ matching

S_{H} (i) = 1; S_{V} (j) = 1; M (i) = j;

m < W (i, M (i))

then

m = W (i, M (i)); n = i;

▹ update max

end if

end for

r \neq R

then ▹ update pointers

p_{H} = {| p_{H} + 1 |}_{[1, N]}; p_{V} = {| p_{V} + 1 |}_{[1, N]};

▹ rotate

else

m > 1

then

p_{H} = M (n)

;

p_{V} = n

; ▹ ptrs. at max. position

else

p_{H} = {| p_{H} + 1 |}_{[1, N]}; p_{V} = {| p_{V} + 1 |}_{[1, N]};

▹rotate

end if

end for

return

M

▹ return matchings

TABLE I

Logical Resource Utilization for the Various Implementations (Total Resources = 424,960

	$N = 4$	$N = 8$	$N = 16$
$i p L Q F_{2}$	1% (4,622)	3% (14,378)	14% (57,970)
$i p L Q F_{1}$	1% (4,678)	3% (14,743)	14% (58,689)
$i S L I P_{3}$	$< 1 %$ (2,655)	2% (9,146)	10% (41,292)
$i S L I P_{2}$	$< 1 %$ (2,691)	2% (9,425)	10% (41,958)
$i S L I P_{1}$	$< 1 %$ (2,702)	3% (11,984)	17% (72,176)

TABLE II

Pin and Memory Utilization When Scaling the Number of Ports

	$N = 4$	$N = 8$	$N = 16$
I/O pins	12% (106)	22% (198)	60% (529)
Memory	2% (81,920)	8% (327,680)	33% (1,310,720)

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Movatterモバイル変換

Simulation and FPGA-Based Implementation of Iterative Parallel Schedulers for Optical Interconnection Networks

Author Affiliations

Abstract

Cited By

Figures (17)

Tables (3)

Journal of Optical Communications and Networking

Algorithm 1

( $W$ , $R$ , $p_{H}$ , $p_{V}$ ): $M$

TABLE I

Logical Resource Utilization for the Various Implementations (Total Resources = 424,960

TABLE II

Pin and Memory Utilization When Scaling the Number of Ports

Tables (3)

Algorithm 1

TABLE I

TABLE II

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