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Shinobu NAGAYAMA, Tsutomu SASAO, Jon T. BUTLER, "Design Method for Numerical Function Generators Using Recursive Segmentation and EVBDDs" in IEICE TRANSACTIONS on Fundamentals, vol. E90-A, no. 12, pp. 2752-2761, December 2007, doi:10.1093/ietfec/e90-a.12.2752.
Abstract:Numerical function generators (NFGs) realize arithmetic functions, such ase^x,sin(πx), and, in hardware. They are used in applications where high-speed is essential, such as in digital signal or graphics applications. We introduce the edge-valued binary decision diagram (EVBDD) as a means of reducing the delay and memory requirements in NFGs. We also introduce a recursive segmentation algorithm, which divides the domain of the function to be realized into segments, where the given function is realized as a polynomial. This design reduces the size of the multiplier needed and thus reduces delay. It is also shown that an adder can be replaced by a set of 2-input AND gates, further reducing delay. We compare our results to NFGs designed with multi-terminal BDDs (MTBDDs). We show that EVBDDs yield a design that has, on the average, only 39% of the memory and 58% of the delay of NFGs designed using MTBDDs.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e90-a.12.2752/_p

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@ARTICLE{e90-a_12_2752,
author={Shinobu NAGAYAMA, Tsutomu SASAO, Jon T. BUTLER, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Design Method for Numerical Function Generators Using Recursive Segmentation and EVBDDs},
year={2007},
volume={E90-A},
number={12},
pages={2752-2761},
abstract={Numerical function generators (NFGs) realize arithmetic functions, such ase^x,sin(πx), and, in hardware. They are used in applications where high-speed is essential, such as in digital signal or graphics applications. We introduce the edge-valued binary decision diagram (EVBDD) as a means of reducing the delay and memory requirements in NFGs. We also introduce a recursive segmentation algorithm, which divides the domain of the function to be realized into segments, where the given function is realized as a polynomial. This design reduces the size of the multiplier needed and thus reduces delay. It is also shown that an adder can be replaced by a set of 2-input AND gates, further reducing delay. We compare our results to NFGs designed with multi-terminal BDDs (MTBDDs). We show that EVBDDs yield a design that has, on the average, only 39% of the memory and 58% of the delay of NFGs designed using MTBDDs.},
keywords={},
doi={10.1093/ietfec/e90-a.12.2752},
ISSN={1745-1337},
month={December},}

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TY - JOUR
TI - Design Method for Numerical Function Generators Using Recursive Segmentation and EVBDDs
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2752
EP - 2761
AU - Shinobu NAGAYAMA
AU - Tsutomu SASAO
AU - Jon T. BUTLER
PY - 2007
DO -10.1093/ietfec/e90-a.12.2752
JO - IEICE TRANSACTIONS on Fundamentals
SN -1745-1337
VL - E90-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2007
AB -Numerical function generators (NFGs) realize arithmetic functions, such ase^x,sin(πx), and, in hardware. They are used in applications where high-speed is essential, such as in digital signal or graphics applications. We introduce the edge-valued binary decision diagram (EVBDD) as a means of reducing the delay and memory requirements in NFGs. We also introduce a recursive segmentation algorithm, which divides the domain of the function to be realized into segments, where the given function is realized as a polynomial. This design reduces the size of the multiplier needed and thus reduces delay. It is also shown that an adder can be replaced by a set of 2-input AND gates, further reducing delay. We compare our results to NFGs designed with multi-terminal BDDs (MTBDDs). We show that EVBDDs yield a design that has, on the average, only 39% of the memory and 58% of the delay of NFGs designed using MTBDDs.
ER -