7.43.3.STM32MP2

STM32MP2 is a microprocessor designed by STMicroelectronicsbased on Arm Cortex-A35.

More information can be found onSTM32MP2 Series page.

For TF-A common configuration of STM32 MPUs, please checkSTM32 MPUs page.

7.43.3.1.STM32MP2 Versions

Here are the variants for STM32MP2:- STM32MP21- STM32MP23- STM32MP25

7.43.3.1.1.STM32MP21 Versions

The STM32MP21 series is available in 3 different lines which are pin-to-pin compatible:

  • STM32MP215: Single Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD - CSI - LTDC

  • STM32MP213: Single Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD

  • STM32MP211: Single Cortex-A35 + Cortex-M33 - 1x Ethernet

Each line comes with a security option (cryptography & secure boot) and a Cortex-A frequency option:

  • A Basic + Cortex-A35 @ 1.2GHz

  • C Secure Boot + HW Crypto + Cortex-A35 @ 1.2GHz

  • D Basic + Cortex-A35 @ 1.5GHz

  • F Secure Boot + HW Crypto + Cortex-A35 @ 1.5GHz

7.43.3.1.2.STM32MP23 Versions

The STM32MP23 series is available in 3 different lines which are pin-to-pin compatible:

  • STM32MP235: Dual Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD - H264 - 3D GPU - AI / NN - LVDS / DSI

  • STM32MP233: Dual Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD

  • STM32MP231: Single Cortex-A35 + Cortex-M33 - 1x Ethernet

Each line comes with a security option (cryptography & secure boot) and a Cortex-A frequency option:

  • A Basic + Cortex-A35 @ 1.2GHz

  • C Secure Boot + HW Crypto + Cortex-A35 @ 1.2GHz

  • D Basic + Cortex-A35 @ 1.5GHz

  • F Secure Boot + HW Crypto + Cortex-A35 @ 1.5GHz

7.43.3.1.3.STM32MP25 Versions

The STM32MP25 series is available in 4 different lines which are pin-to-pin compatible:

  • STM32MP257: Dual Cortex-A35 cores, Cortex-M33 core - 3x Ethernet (2+1 switch) - 3x CAN FD – H264 - 3D GPU – AI / NN - LVDS

  • STM32MP255: Dual Cortex-A35 cores, Cortex-M33 core - 2x Ethernet – 3x CAN FD - H264 - 3D GPU – AI / NN - LVDS

  • STM32MP253: Dual Cortex-A35 cores, Cortex-M33 core - 2x Ethernet – 3x CAN FD - LVDS

  • STM32MP251: Single Cortex-A35 core, Cortex-M33 core - 1x Ethernet

Each line comes with a security option (cryptography & secure boot) and a Cortex-A frequency option:

  • A Basic + Cortex-A35 @ 1.2GHz

  • C Secure Boot + HW Crypto + Cortex-A35 @ 1.2GHz

  • D Basic + Cortex-A35 @ 1.5GHz

  • F Secure Boot + HW Crypto + Cortex-A35 @ 1.5GHz

TheSTM32MP2 part number codification page gives more information about part numbers.

7.43.3.2.Memory mapping

0x00000000+-----------------+|||...|||0x0E000000+-----------------+ \|BL31||+-----------------+||...||0x0E012000+-----------------+||BL2DTB||EmbeddedSRAM0x0E016000+-----------------+||BL2||0x0E040000+-----------------+/|||...|||0x40000000+-----------------+||||Devices||0x80000000+-----------------+ \||||||Non-secureRAM(DDR)|||0xFFFFFFFF+-----------------+/

7.43.3.3.Build Instructions

7.43.3.3.1.STM32MP2x specific flags

Dedicated STM32MP2 build flags:

  • STM32MP_DDR_FIP_IO_STORAGE: to store DDR firmware in FIP.
    Default: 1
  • STM32MP21: to select STM32MP21 variant configuration.
    Default: 0
  • STM32MP23: to select STM32MP23 variant configuration.
    Default: 0
  • STM32MP25: to select STM32MP25 variant configuration.
    Default: 1

To compile the correct DDR driver, one flag must be set among:

  • STM32MP_DDR3_TYPE: to compile DDR3 driver and DT.
    Default: 0
  • STM32MP_DDR4_TYPE: to compile DDR4 driver and DT.
    Default: 0
  • STM32MP_LPDDR4_TYPE: to compile LpDDR4 driver and DT.
    Default: 0

7.43.3.3.2.Boot with FIP

You need to build BL2, BL31, BL32 (OP-TEE) and BL33 (U-Boot) and retrieveDDR PHY firmware before building FIP binary.

7.43.3.3.2.1.U-Boot

cd<u-boot_directory>makestm32mp25_defconfigmakeDEVICE_TREE=stm32mp257f-ev1all

7.43.3.3.2.2.OP-TEE

cd<optee_directory>makeCROSS_COMPILE64=aarch64-none-elf-CROSS_COMPILE32=arm-none-eabi-ARCH=armPLATFORM=stm32mp2\CFG_EMBED_DTB_SOURCE_FILE=stm32mp257f-ev1.dts

7.43.3.3.2.3.DDR PHY firmware

DDR PHY firmware files may not be delivered inside TF-A repository, especiallyif you build directly from trustedfirmware.org repository. It then needs to beretrieved fromSTMicroelectronics DDR PHY github.

You can either clone the repository to the default directory:

gitclonehttps://github.com/STMicroelectronics/stm32-ddr-phy-binary.gitdrivers/st/ddr/phy/firmware/bin

Or clone it somewhere else, and addSTM32MP_DDR_FW_PATH= in your make commandline when building FIP.

7.43.3.3.2.4.TF-A BL2

To build TF-A BL2 with its STM32 header for SD-card boot:

makeCROSS_COMPILE=aarch64-none-elf-PLAT=stm32mp2\STM32MP_DDR4_TYPE=1SPD=opteed\DTB_FILE_NAME=stm32mp257f-ev1.dtbSTM32MP_SDMMC=1

For other boot devices, you have to replace STM32MP_SDMMC in the previous commandwith the desired device flag.

7.43.3.3.2.5.FIP

makeCROSS_COMPILE=aarch64-none-elf-PLAT=stm32mp2\STM32MP_DDR4_TYPE=1SPD=opteed\DTB_FILE_NAME=stm32mp257f-ev1.dtb\BL33=<u-boot_directory>/u-boot-nodtb.bin\BL33_CFG=<u-boot_directory>/u-boot.dtb\BL32=<optee_directory>/tee-header_v2.bin\BL32_EXTRA1=<optee_directory>/tee-pager_v2.binfip

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