7.43.2.STM32MP1

STM32MP1 is a microprocessor designed by STMicroelectronicsbased on Arm Cortex-A7.It is an Armv7-A platform, using dedicated code from TF-A.More information can be found onSTM32MP1 Series page.

For TF-A common configuration of STM32 MPUs, please checkSTM32 MPUs page.

7.43.2.1.STM32MP1 Versions

There are 2 variants for STM32MP1: STM32MP13 and STM32MP15

7.43.2.1.1.STM32MP13 Versions

The STM32MP13 series is available in 3 different lines which are pin-to-pin compatible:

  • STM32MP131: Single Cortex-A7 core

  • STM32MP133: STM32MP131 + 2*CAN, ETH2(GMAC), ADC1

  • STM32MP135: STM32MP133 + DCMIPP, LTDC

Each line comes with a security option (cryptography & secure boot) and a Cortex-A frequency option:

  • A Cortex-A7 @ 650 MHz

  • C Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz

  • D Cortex-A7 @ 900 MHz

  • F Secure Boot + HW Crypto + Cortex-A7 @ 900 MHz

7.43.2.1.2.STM32MP15 Versions

The STM32MP15 series is available in 3 different lines which are pin-to-pin compatible:

  • STM32MP157: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz, 3D GPU, DSI display interface and CAN FD

  • STM32MP153: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz and CAN FD

  • STM32MP151: Single Cortex-A7 core, Cortex-M4 core @ 209 MHz

Each line comes with a security option (cryptography & secure boot) and a Cortex-A frequency option:

  • A Basic + Cortex-A7 @ 650 MHz

  • C Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz

  • D Basic + Cortex-A7 @ 800 MHz

  • F Secure Boot + HW Crypto + Cortex-A7 @ 800 MHz

TheSTM32MP1 part number codification page gives more information about part numbers.

7.43.2.2.Memory mapping

0x00000000+-----------------+||ROM0x00020000+-----------------+|||...|||0x2FFC0000+-----------------+ \|BL32DTB||0x2FFC5000+-----------------+||BL32||0x2FFDF000+-----------------+||...||0x2FFE3000+-----------------+||BL2DTB||EmbeddedSRAM0x2FFEA000+-----------------+||BL2||0x2FFFF000+-----------------+||SCMImailbox||0x30000000+-----------------+/|||...|||0x40000000+-----------------+||||Devices||0xC0000000+-----------------+ \|||0xC0100000+-----------------+||BL33||Non-secureRAM(DDR)|...|||||0xFFFFFFFF+-----------------+/

7.43.2.3.Build Instructions

7.43.2.3.1.STM32MP1x specific flags

Dedicated STM32MP1 flags:

  • STM32_TF_VERSION: to manage BL2 monotonic counter.
    Default: 0
  • STM32MP13: to select STM32MP13 variant configuration.
    Default: 0
  • STM32MP15: to select STM32MP15 variant configuration.
    Default: 1

7.43.2.3.2.Boot with FIP

You need to build BL2, BL32 (SP_min or OP-TEE) and BL33 (U-Boot) before building FIP binary.

7.43.2.3.2.1.U-Boot

cd<u-boot_directory>makestm32mp15_trusted_defconfigmakeDEVICE_TREE=stm32mp157c-ev1all

7.43.2.3.2.2.OP-TEE (recommended)

OP-TEE is the default BL32 supported for STMicroelectronics platforms.

cd<optee_directory>makeCROSS_COMPILE=arm-linux-gnueabihf-ARCH=armPLATFORM=stm32mp1\CFG_EMBED_DTB_SOURCE_FILE=stm32mp157c-ev1.dts

7.43.2.3.2.3.TF-A BL32 (SP_min) (not recommended)

If you choose not to use OP-TEE, you can use TF-A SP_min.This is not the recommended BL32 to use, and will have very limited support.To build TF-A BL32, and its device tree file:

makeCROSS_COMPILE=arm-none-eabi-PLAT=stm32mp1ARCH=aarch32ARM_ARCH_MAJOR=7\AARCH32_SP=sp_minDTB_FILE_NAME=stm32mp157c-ev1.dtbbl32dtbs

7.43.2.3.2.4.TF-A BL2

To build TF-A BL2 with its STM32 header for SD-card boot:

makeCROSS_COMPILE=arm-none-eabi-PLAT=stm32mp1ARCH=aarch32ARM_ARCH_MAJOR=7\DTB_FILE_NAME=stm32mp157c-ev1.dtbSTM32MP_SDMMC=1

For other boot devices, you have to replace STM32MP_SDMMC in the previous commandwith the desired device flag.

This BL2 is independent of the BL32 used (SP_min or OP-TEE)

7.43.2.3.2.5.FIP

With BL32 SP_min:

makeCROSS_COMPILE=arm-none-eabi-PLAT=stm32mp1ARCH=aarch32ARM_ARCH_MAJOR=7\AARCH32_SP=sp_min\DTB_FILE_NAME=stm32mp157c-ev1.dtb\BL33=<u-boot_directory>/u-boot-nodtb.bin\BL33_CFG=<u-boot_directory>/u-boot.dtb\fip

With OP-TEE:

makeCROSS_COMPILE=arm-none-eabi-PLAT=stm32mp1ARCH=aarch32ARM_ARCH_MAJOR=7\AARCH32_SP=optee\DTB_FILE_NAME=stm32mp157c-ev1.dtb\BL33=<u-boot_directory>/u-boot-nodtb.bin\BL33_CFG=<u-boot_directory>/u-boot.dtb\BL32=<optee_directory>/tee-header_v2.bin\BL32_EXTRA1=<optee_directory>/tee-pager_v2.binBL32_EXTRA2=<optee_directory>/tee-pageable_v2.binfip

7.43.2.3.2.6.Trusted Boot Board

tools/cert_create/cert_create-n--rot-keybuild/stm32mp1/release/rot_key.pem\--tfw-nvctr0\--ntfw-nvctr0\--key-algecdsa--hash-algsha256\--trusted-key-certbuild/stm32mp1/release/trusted_key.crt\--tos-fw<optee_directory>/tee-header_v2.bin\--tos-fw-extra1<optee_directory>/tee-pager_v2.bin\--tos-fw-extra2<optee_directory>/tee-pageable_v2.bin\--tos-fw-certbuild/stm32mp1/release/tos_fw_content.crt\--tos-fw-key-certbuild/stm32mp1/release/tos_fw_key.crt\--nt-fw<u-boot_directory>/u-boot-nodtb.bin\--nt-fw-certbuild/stm32mp1/release/nt_fw_content.crt\--nt-fw-key-certbuild/stm32mp1/release/nt_fw_key.crt\--hw-config<u-boot_directory>/u-boot.dtb\--fw-configbuild/stm32mp1/release/fdts/fw-config.dtb\--stm32mp-cfg-certbuild/stm32mp1/release/stm32mp_cfg_cert.crttools/fiptool/fiptoolcreate--tos-fw<optee_directory>/tee-header_v2.bin\--tos-fw-extra1<optee_directory>/tee-pager_v2.bin\--tos-fw-extra2<optee_directory>/tee-pageable_v2.bin\--nt-fw<u-boot_directory>/u-boot-nodtb.bin\--hw-config<u-boot_directory>/u-boot.dtb\--fw-configbuild/stm32mp1/release/fdts/fw-config.dtb\--trusted-key-certbuild/stm32mp1/release/trusted_key.crt\--tos-fw-certbuild/stm32mp1/release/tos_fw_content.crt\--tos-fw-key-certbuild/stm32mp1/release/tos_fw_key.crt\--nt-fw-certbuild/stm32mp1/release/nt_fw_content.crt\--nt-fw-key-certbuild/stm32mp1/release/nt_fw_key.crt\--stm32mp-cfg-certbuild/stm32mp1/release/stm32mp_cfg_cert.crt\build/stm32mp1/release/stm32mp1.fip

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