7.12.Intel Stratix 10 SoCFPGA

Stratix 10 SoCFPGA is a FPGA with integrated quad-core 64-bit Arm Cortex A53 processor.

Upon boot, Boot ROM loads bl2 into OCRAM. Bl2 subsequently initializesthe hardware, then loads bl31 and bl33 (UEFI) into DDR and boots to bl33.

BootROM-->TrustedFirmware-A-->UEFI

7.12.1.How to build

7.12.1.1.Code Locations

  • Trusted Firmware-A:link

  • UEFI (to be updated with new upstreamed UEFI):link

7.12.1.2.Build Procedure

  • Fetch all the above 2 repositories into local host.Make all the repositories in the same ${BUILD_PATH}.

  • Prepare the AARCH64 toolchain.

  • Build UEFI using Stratix 10 platform as configurationThis will be updated to use an updated UEFI using the latest EDK2 source

makeCROSS_COMPILE=aarch64-linux-gnu-device=s10

  • Build atf providing the previously generated UEFI as the BL33 image

makeCROSS_COMPILE=aarch64-linux-gnu-bl2fipPLAT=stratix10BL33=PEI.ROM

7.12.1.3.Install Procedure

  • dd fip.bin to a A2 partition on the MMC drive to be booted in Stratix 10board.

  • Generate a SOF containing bl2

aarch64-linux-gnu-objcopy-Ibinary-Oihex--change-addresses0xffe00000bl2.binbl2.hexquartus_cpf--bootloaderbl2.hex<quartus_generated_sof><output_sof_with_bl2>

  • Configure SOF to board

nios2-configure-sof<output_sof_with_bl2>

7.12.2.Boot trace

INFO:    DDR: DRAM calibration success.INFO:    ECC is disabled.INFO:    Init HPS NOC's DDR Scheduler.NOTICE:  BL2: v2.0(debug):v2.0-809-g7f8474a-dirtyNOTICE:  BL2: Built : 17:38:19, Feb 18 2019INFO:    BL2: Doing platform setupINFO:    BL2: Loading image id 3INFO:    Loading image id=3 at address 0xffe1c000INFO:    Image id=3 loaded: 0xffe1c000 - 0xffe24034INFO:    BL2: Loading image id 5INFO:    Loading image id=5 at address 0x50000INFO:    Image id=5 loaded: 0x50000 - 0x550000NOTICE:  BL2: Booting BL31INFO:    Entry point address = 0xffe1c000INFO:    SPSR = 0x3cdNOTICE:  BL31: v2.0(debug):v2.0-810-g788c436-dirtyNOTICE:  BL31: Built : 15:17:16, Feb 20 2019INFO:    ARM GICv2 driver initializedINFO:    BL31: Initializing runtime servicesWARNING: BL31: cortex_a53: CPU workaround for 855873 was missing!INFO:    BL31: Preparing for EL3 exit to normal worldINFO:    Entry point address = 0x50000INFO:    SPSR = 0x3c9UEFI firmware (version 1.0 built at 11:26:18 on Nov  7 2018)