7.27.NXP S32G274A

S32G2 is an NXP vehicle network processor combining ASIL D safety, hardwaresecurity, high-performance real-time and application processing and networkacceleration. S32G2 supports the needs of new vehicle architectures:service-oriented gateways, domain controllers, zonal processors, safetyprocessors and more. It is equipped with 4 Cortex-A53 cores operating at1.0GHz.

The TF-A includes support for one single S32G2-based board called S32G274ARDB2.The S32G-VNP-RDB2 is a compact, highly optimized and integrated boardengineering for vehicle service-oriented gateway (SoG), domain controlapplications, high-performance processing, safety and security applications.More details about this board can be found ats32g274ardb2.

7.27.1.Boot Flow

BootROM->BL2(SRAM)->BL31(SRAM)->BL33(DDR-TODO)

Warning

This boot flow is a preliminary version that will serve as a foundation forupcoming S32G2 contributions. The execution will hang after the BL31 stagedue to U-Boot being deployed in SRAM instead of DDR. This issue will beresolved with the addition of the DDR driver.

7.27.2.Code Locations

7.27.3.How to build

The port currently available on the S32G274ARDB2 platform is in its initialstage. This means that important drivers like DDR and storage are not yetavailable. Consequently, the boot process depends on BootROM to load all TF-Astages in SRAM. To create a bootable image, the script below should be used.This script makes use of themkimage tool, which is part of the U-Boot dropfor S32G274A SoCs.

#!/bin/bash -xeTF_A="${TF_A:-`pwd`}"UBOOT="${UBOOT:-${TF_A}/../u-boot}"DEBUG="${DEBUG:-1}"FIP_BASE="0x34100000"if["${DEBUG}"-eq"1"];thenBUILD="debug"elseBUILD="release"fiBOOT_IMAGE="build/s32g274ardb2/${BUILD}/BOOT_IMAGE.bin"BL2_BIN="build/s32g274ardb2/${BUILD}/bl2.bin"FIP_BIN="build/s32g274ardb2/${BUILD}/fip.bin"# Generate bl2, bl31 and fip imagemake-C"${TF_A}"-j9'PLAT=s32g274ardb2'\BL33="${UBOOT}/u-boot-nodtb.bin"DEBUG="${DEBUG}"cleanmake-C"${TF_A}"-j9'PLAT=s32g274ardb2'\BL33="${UBOOT}/u-boot-nodtb.bin"DEBUG="${DEBUG}"bl2make-C"${TF_A}"-j9'PLAT=s32g274ardb2'\BL33="${UBOOT}/u-boot-nodtb.bin"DEBUG="${DEBUG}"fip# Extract BL2 entryBL2_START="0x$(poetryrunmemory-ps32g274ardb2-bdebug-f|\grepBL2|awk-F'|''{print $3}'|xargs)"# BL2 bin file size in bytesBL2_SIZE="$(stat-c"%s""${BL2_BIN}")"# Pack bl2.bin and fip.bin by ensuring that the FIP image will start at FIP_BASEcp-vf"${BL2_BIN}""${BOOT_IMAGE}"ddif="${FIP_BIN}"of="${BOOT_IMAGE}"seek="$((FIP_BASE-BL2_START))"bs=1# Build a bootable image by appending the IVT"${UBOOT}/tools/mkimage"\-a"${BL2_START}"\-e"${BL2_START}"\-Ts32ccimage\-n"${UBOOT}/u-boot-s32.cfgout"\-d"${BOOT_IMAGE}"\fip.s32

7.27.4.SoC Errata Workarounds

The S32G274A port of the TF-A includes compilation flags that can be used tocontrol the workaround for the SoC. These flags are used similarly to how theCPU Errata Workarounds are used. The list of workaroundsincludes the following switches:

  • ERRATA_S32_051700: This applies erratum ERR051700 workaround toSoCs part of the S32 Common Chassis family, and therefore it needs tobe enabled for the S32G and S32R devices.