7.39.Renesas RZ/G
The “RZ/G” Family of high-end 64-bit Arm®-based microprocessors (MPUs)enables the solutions required for the smart society of the future.Through a variety of Arm Cortex®-A53 and A57-based devices, engineers caneasily implement high-resolution human machine interfaces (HMI), embeddedvision, embedded artificial intelligence (e-AI) and real-time control andindustrial ethernet connectivity.
The scalable RZ/G hardware platform and flexible software platformcover the full product range, from the premium class to the entrylevel. Plug-ins are available for multiple open-source software tools.
7.39.1.Renesas RZ/G2 reference platforms:
Board | Details | |
|---|---|---|
hihope-rzg2h | “96 boards” compatible board from Hoperun equipped with Renesas RZ/G2H SoC | |
hihope-rzg2m | “96 boards” compatible board from Hoperun equipped with Renesas RZ/G2M SoC | |
hihope-rzg2n | “96 boards” compatible board from Hoperun equipped with Renesas RZ/G2N SoC | |
ek874 | “96 boards” compatible board from Silicon Linux equipped with Renesas RZ/G2E SoC | |
The current TF-A port has been tested on the HiHope RZ/G2MSoC_id r8a774a1 revision ES1.3.
ARM CA57 (ARMv8) 1.5 GHz dual core, with NEON/VFPv4, L1$ I/D 48K/32K, L2$ 1MBARM CA53 (ARMv8) 1.2 GHz quad core, with NEON/VFPv4, L1$ I/D 32K/32K, L2$ 512KMemory controller for LPDDR4-3200 4GB in 2 channels(32-bit bus mode)Two- and three-dimensional graphics engines,Video processing units,Display Output,Video Input,SD card host interface,USB3.0 and USB2.0 interfaces,CAN interfaces,Ethernet AVB,Wi-Fi + BT,PCI Express Interfaces,Memories INTERNAL 384KB SYSTEM RAM DDR 4 GB LPDDR4 QSPI FLASH 64MB EMMC 32 GB EMMC (HS400 240 MBYTES/S) MICROSD-CARD SLOT (SDR104 100 MBYTES/S)
7.39.2.Overview
On RZ/G2 SoCs the BOOTROM starts the cpu at EL3; for this port BL2will therefore be entered at this exception level (the Renesas’ ATFreference tree [1] resets into EL1 before entering BL2 - see itsbl2.ld.S)
BL2 initializes DDR before determining the boot reason (cold or warm).
Once BL2 boots, it determines the boot reason, writes it to sharedmemory (BOOT_KIND_BASE) together with the BL31 parameters(PARAMS_BASE) and jumps to BL31.
To all effects, BL31 is as if it is being entered in reset mode sinceit still needs to initialize the rest of the cores; this is the reasonbehind using direct shared memory access to BOOT_KIND_BASE _and_PARAMS_BASE instead of using registers to get to those locations (seeel3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 usecase).
[1]https://github.com/renesas-rz/meta-rzg2/tree/BSP-1.0.5/recipes-bsp/arm-trusted-firmware/files
7.39.3.How to build
The TF-A build options depend on the target board so you will have torefer to those specific instructions. What follows is customized tothe HiHope RZ/G2M development kit used in this port.
7.39.3.1.Build Tested:
makebl2bl31rzgLOG_LEVEL=40PLAT=rzgLSI=G2MRCAR_DRAM_SPLIT=2\RCAR_LOSSY_ENABLE=1SPD="none"MBEDTLS_DIR=$mbedtls
7.39.3.2.System Tested:
mbed_tls:git@github.com:ARMmbed/mbedtls.git [devel]
u-boot:The port has beent tested using mainline uboot with HiHope RZ/G2M boardspecific patches.
linux:The port has beent tested using mainline kernel.
7.39.3.3.TF-A Build Procedure
Fetch all the above 3 repositories.
Prepare the AARCH64 toolchain.
Build u-boot using hihope_rzg2_defconfig.
Result: u-boot-elf.srec
makeCROSS_COMPILE=aarch64-linux-gnu-hihope_rzg2_defconfigmakeCROSS_COMPILE=aarch64-linux-gnu-
Build TF-A
Result: bootparam_sa0.srec, cert_header_sa6.srec, bl2.srec, bl31.srec
makebl2bl31rzgLOG_LEVEL=40PLAT=rzgLSI=G2MRCAR_DRAM_SPLIT=2\RCAR_LOSSY_ENABLE=1SPD="none"MBEDTLS_DIR=$mbedtls
7.39.3.4.Install Procedure
Boot the board in Mini-monitor mode and enable access to theQSPI flash.
Use the flash_writer utility[2] to flash all the SREC files.
7.39.4.Boot trace
INFO:ARMGICv2driverinitializedNOTICE:BL2:RZ/G2InitialProgramLoader(CA57)Rev.2.0.6NOTICE:BL2:PRRisRZ/G2MVer.1.3NOTICE:BL2:BoardisHiHopeRZ/G2MRev.4.0NOTICE:BL2:BootdeviceisQSPIFlash(40MHz)NOTICE:BL2:LCMstateisunknownNOTICE:BL2:DDR3200(rev.0.40)NOTICE:BL2:[COLD_BOOT]NOTICE:BL2:DRAMSplitis2chNOTICE:BL2:QoSisdefaultsetting(rev.0.19)NOTICE:BL2:DRAMrefreshinterval1.95usecNOTICE:BL2:PeriodicWriteDQTrainingNOTICE:BL2:CH0:400000000-47fffffff,2GiBNOTICE:BL2:CH2:600000000-67fffffff,2GiBNOTICE:BL2:LossyDecompareasNOTICE:Entry0:DCMPAREACRAx:0x80000540DCMPAREACRBx:0x570NOTICE:Entry1:DCMPAREACRAx:0x40000000DCMPAREACRBx:0x0NOTICE:Entry2:DCMPAREACRAx:0x20000000DCMPAREACRBx:0x0NOTICE:BL2:FDTat0xe631db30NOTICE:BL2:v2.3(release):v2.4-rc0-2-g1433701e5NOTICE:BL2:Built:13:45:26,Nov72020NOTICE:BL2:NormalbootINFO:BL2:DoingplatformsetupINFO:BL2:Loadingimageid3NOTICE:BL2:dst=0xe631d200src=0x8180000len=512(0x200)NOTICE:BL2:dst=0x43f00000src=0x8180400len=6144(0x1800)WARNING:r-carignoringtheBL31sizefromcertificate,usingRCAR_TRUSTED_SRAM_SIZEinsteadINFO:Loadingimageid=3ataddress0x44000000NOTICE:rcar_file_len:len:0x0003e000NOTICE:BL2:dst=0x44000000src=0x81c0000len=253952(0x3e000)INFO:Imageid=3loaded:0x44000000-0x4403e000INFO:BL2:Loadingimageid5INFO:Loadingimageid=5ataddress0x50000000NOTICE:rcar_file_len:len:0x00100000NOTICE:BL2:dst=0x50000000src=0x8300000len=1048576(0x100000)INFO:Imageid=5loaded:0x50000000-0x50100000NOTICE:BL2:BootingBL31INFO:Entrypointaddress=0x44000000INFO:SPSR=0x3cdU-Boot2021.01-rc1-00244-gac37e14fbd(Nov042020-20:03:34+0000)CPU:RenesasElectronicsR8A774A1rev1.3Model:HopeRunHiHopeRZ/G2MwithsubboardDRAM:3.9GiBMMC:mmc@ee100000:0,mmc@ee160000:1LoadingEnvironmentfromMMC...OKIn:serial@e6e88000Out:serial@e6e88000Err:serial@e6e88000Net:eth0:ethernet@e6800000Hitanykeytostopautoboot:0=>