7.11.Intel Agilex SoCFPGA

Agilex SoCFPGA is a FPGA with integrated quad-core 64-bit Arm Cortex A53 processor.

Upon boot, Boot ROM loads bl2 into OCRAM. Bl2 subsequently initializesthe hardware, then loads bl31 and bl33 (UEFI) into DDR and boots to bl33.

BootROM-->TrustedFirmware-A-->UEFI

7.11.1.How to build

7.11.1.1.Code Locations

  • Trusted Firmware-A:link

  • UEFI (to be updated with new upstreamed UEFI):link

7.11.1.2.Build Procedure

  • Fetch all the above 2 repositories into local host.Make all the repositories in the same ${BUILD_PATH}.

  • Prepare the AARCH64 toolchain.

  • Build UEFI using Agilex platform as configurationThis will be updated to use an updated UEFI using the latest EDK2 source

makeCROSS_COMPILE=aarch64-linux-gnu-device=agx

  • Build atf providing the previously generated UEFI as the BL33 image

makeCROSS_COMPILE=aarch64-linux-gnu-bl2fipPLAT=agilexBL33=PEI.ROM

7.11.1.3.Install Procedure

  • dd fip.bin to a A2 partition on the MMC drive to be booted in Agilexboard.

  • Generate a SOF containing bl2

aarch64-linux-gnu-objcopy-Ibinary-Oihex--change-addresses0xffe00000bl2.binbl2.hexquartus_cpf--bootloaderbl2.hex<quartus_generated_sof><output_sof_with_bl2>

  • Configure SOF to board

nios2-configure-sof<output_sof_with_bl2>

7.11.2.Boot trace

INFO:DDR:DRAMcalibrationsuccess.INFO:ECCisdisabled.NOTICE:BL2:v2.1(debug)NOTICE:BL2:BuiltINFO:BL2:DoingplatformsetupNOTICE:BL2:BootingBL31INFO:Entrypointaddress=0xffe1c000INFO:SPSR=0x3cdNOTICE:BL31:v2.1(debug)NOTICE:BL31:BuiltINFO:ARMGICv2driverinitializedINFO:BL31:InitializingruntimeservicesWARNING:BL31:cortex_a53INFO:BL31:PreparingforEL3exittonormalworldINFO:Entrypointaddress=0x50000INFO:SPSR=0x3c9