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Re: [PATCH 06/27] arm64/sve: System register and exception syndrome definitions

• From: Dave Martin <Dave dot Martin at arm dot com>
• To: Alex Bennée <alex dot bennee at linaro dot org>
• Cc: linux-arch at vger dot kernel dot org, libc-alpha at sourceware dot org,Ard Biesheuvel <ard dot biesheuvel at linaro dot org>,Szabolcs Nagy <szabolcs dot nagy at arm dot com>,Catalin Marinas <catalin dot marinas at arm dot com>,Will Deacon <will dot deacon at arm dot com>,Richard Sandiford <richard dot sandiford at arm dot com>,kvmarm at lists dot cs dot columbia dot edu, linux-arm-kernel at lists dot infradead dot org
• Date: Mon, 21 Aug 2017 16:19:58 +0100
• Subject: Re: [PATCH 06/27] arm64/sve: System register and exception syndrome definitions
• Authentication-results: sourceware.org; auth=none
• References: <1502280338-23002-1-git-send-email-Dave.Martin@arm.com> <1502280338-23002-7-git-send-email-Dave.Martin@arm.com> <87a82t5kos.fsf@linaro.org> <8760dh5cbl.fsf@linaro.org> <20170821142627.GQ6321@e103592.cambridge.arm.com> <871so55613.fsf@linaro.org>

On Mon, Aug 21, 2017 at 03:50:32PM +0100, Alex Bennée wrote:> Dave Martin <Dave.Martin@arm.com> writes:> > On Mon, Aug 21, 2017 at 01:34:38PM +0100, Alex Bennée wrote:[...]> >> > Dave Martin <Dave.Martin@arm.com> writes:[...]> >> >> +#define ZCR_ELx_LEN_SHIFT0> >> >> +#define ZCR_ELx_LEN_SIZE9> >> >> +#define ZCR_ELx_LEN_MASK0x1ff> >> >> +> >>> >> LEN should be 0/4/0xf> >>> >> LEN, bits [3:0]> >>> >> Constrains the scalable vector register length for EL1 and EL0 to> >> (LEN+1)x128 bits.> >> > The SVE supplement is not very explicit about the meaning of bits [8:4],> > but they are reserved to extend the LEN field in the future, in case> > that's ever needed for future architecture revisions.  I've aimed for> > Linux to cope with this.> >> > Basically bits [8:4] are read-as-zero, write-ignore today, but in> > the future some or all of them may be LEN field bits.> >> > In particular, this means that writing all bits [8:0] with 1 will> > configure the largest supported vector length, even on future> > architecture versions that may have a larger LEN field.> > Ahh ok. It's not clear from the html and it is certainly implied in the> supplement (2.1.1) that the architectural max is:> >   The size of every vector register is an IMPLEMENTATION DEFINED>   multiple of 128 bits, up to an architectural maximum of 2048 bits.> > >> > It didn't seem useful to distinguish the two classes of bits here.> > Maybe a comment clarifying would be useful then?OK, I think I can say something like:/* * The ZCR_ELx_LEN_* definitions intentionally include bits [8:4] * which are reserved by the SVE architecture for future expansion of * the LEN field, with compatible semantics. */Any good?Cheers---Dave

• Follow-Ups:
  • Re: [PATCH 06/27] arm64/sve: System register and exception syndrome definitions
    • From: Alex Bennée

• References:
  • [PATCH 00/27] ARM Scalable Vector Extension (SVE)
    • From: Dave Martin
  • [PATCH 06/27] arm64/sve: System register and exception syndrome definitions
    • From: Dave Martin
  • Re: [PATCH 06/27] arm64/sve: System register and exception syndrome definitions
    • From: Alex Bennée
  • Re: [PATCH 06/27] arm64/sve: System register and exception syndrome definitions
    • From: Alex Bennée
  • Re: [PATCH 06/27] arm64/sve: System register and exception syndrome definitions
    • From: Dave Martin
  • Re: [PATCH 06/27] arm64/sve: System register and exception syndrome definitions
    • From: Alex Bennée