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Re: [PATCH] powerpc: Restrict xssqrtqp operands to Vector Registers (Altivec/VMX)

• From: "Tulio Magno Quites Machado Filho" <tuliom at linux dot vnet dot ibm dot com>
• To: "Gabriel F. T. Gomes" <gftg at linux dot vnet dot ibm dot com>, libc-alpha at sourceware dot org
• Cc:
• Date: Wed, 09 Aug 2017 11:49:24 -0300
• Subject: Re: [PATCH] powerpc: Restrict xssqrtqp operands to Vector Registers (Altivec/VMX)
• Authentication-results: sourceware.org; auth=none
• References: <20170808161232.17066-1-gftg@linux.vnet.ibm.com>

"Gabriel F. T. Gomes" <gftg@linux.vnet.ibm.com> writes:> POWER ISA 3.0 introduces the xssqrtqp instructions, which expects> operands to be in Vector Registers (Altivec/VMX), even though this> instruction belongs to the Vector-Scalar Instruction Set.>> In GCC's Extended Assembly for POWER, the 'wq' register constraint is> provided for use with IEEE 754 128-bit floating-point values.  However,> this constrain does not limit the register allocation to Vectors/constrain/constraint/> Registers (Altivec/VMX) and could assign a Vector-Scalar Register (VSX)> to the operands of the instruction.>> This patch changes the register constraint used in sqrtf128 from 'wq' to> 'v', in order to request a Vector Register (Altivec/VMX) for use with> the xssqrtqp instruction.>> Tested for powerpc64le and --with-cpu=power9.>> * sysdeps/powerpc/fpu/math_private.h (__ieee754_sqrtf128): Since> xssqrtqp requires operands to be in Vector Registers> (Altivec/VMX), replace the register constraint 'wq' with 'v'.> * sysdeps/powerpc/powerpc64le/power9/fpu/e_sqrtf128.c> (__ieee754_sqrtf128): Likewise.Looks good to me, but as it affects glibc 2.26, I think we need a bug reportand a bugzilla number in the commit message.Thanks!-- Tulio Magno

• Follow-Ups:
  • Re: [PATCH] powerpc: Restrict xssqrtqp operands to Vector Registers (Altivec/VMX)
    • From: Gabriel F. T. Gomes

• References:
  • [PATCH] powerpc: Restrict xssqrtqp operands to Vector Registers (Altivec/VMX)
    • From: Gabriel F. T. Gomes