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Very long instruction word

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Very Long Instruction Word orVLIW which refers to aCPU architecture designed to take advantage ofinstruction level parallelism (ILP) but at minimum level ofhardware complexities. ( Alternatively,Variable Length Instruction Word orVLIW a refers to aCPU instruction (instruction set ) designed to load ( or copy ) a literal value count of inlineMachine code to the on-chip RAM for higher speedCPU decoding. )

A processor that executes everyinstruction one after the other (i.e. a non-pipelined scalar architecture) may use processor resourcesinefficiently, leading to poorperformance. The performance can be improved by usingmicro-architectural design techniques that useILP including:

Instruction pipelining where the execution of multipleinstructions can be partiallyoverlapped; where each instructions is divided into series of sub-steps (termed:micro-operations).
Superscalar execution in which multipleexecution units are used to execute multipleinstructions in parallel.
Out-of-order execution whereinstructions execute in any order but without violatingdata dependencies.
Register renaming which is atechnique used to avoid unnecessaryserialization of programinstructions caused by the reuse of registers by those instructions, in order to enable out-of-order execution.
Speculative execution which allow the execution of completeinstructions or parts of instructions before being sure whether this execution is required.
Branch prediction which is used to avoid delays (termed: stalls) cause of control dependencies to be resolved. Branch prediction is used withspeculative execution.

All aboveILP techniques are implemented at a higher cost with increased hardware complexity. Before executing any operations in-parallel, the processor must verify that the instructions do not haveinterdependencies. There are many types of interdependencies, but a simple example would be a program in which the first instruction's result is used as an input for the second instruction. They clearly cannot execute at the same time, and the second instruction cannot be executed before the first. Modernout-of-order processors use major resources in order to take advantage of these techniques, since the scheduling of instructions must be determineddynamically as a program executes based on dependencies.

TheVLIW approach, on the other hand, executes operation in parallel based on a fixed schedule determined when programs arecompiled. Since determining the order of execution ofoperations (including which operations can execute simultaneously) is handled by the compiler, the processor does not need the complex hardware required byILP techniques described above. As a result,VLIW CPUs offer significantcomputational power with less hardware complexity but with greatercompiler design complexity.

TheVLIW approach is a concept which is only useful as the code generated by acompiler makes it, but with a number of special-purpose instructions available to simplify certain complicated operations:

Insuperscalar designs, the number ofexecution units is invisible to theinstruction set. Each instruction encodes only one operation. For mostsuperscalar designs, the instruction width is 32 bits or less.
In contrast, oneVLIW instruction encodes multiple operations; specifically, one instruction encodes at least one operation for eachexecution unit of the device. For example, if aVLIW device has five execution units, then aVLIW instruction for that device would have five operation fields, each field specifying what operation should be done on that corresponding execution unit. In order to find a space for these operation fields,VLIW instructions are usually at least 64-bits in width and on some architectures 128-bits or wider; this is how the name comes.