Temporary bonding (TB) and debonding (DB) of wafers have been widely developed and applied over the last decade in various wafer-level packaging technologies, such as package-on-package (PoP), fan-out integration, and 2.5D and 3D integration using through-silicon vias (TSVs). The materials used to achieve TB and DB are extremely critical and the industry's current best practice is the use of tw...» read more
AuthorsA. Martins*, M. Pinheiro*, A. F. Ferreira*, R. Almeida*, F. Matos*,J. Oliveira*, Eoin O´Toole*, H. M. Santos†, M. C. Monteiro‡, H. Gamboa‡, R. P. Silva*‡Fraunhofer Portugal AICOS, Porto, Portugal†INESC TEC*AMKOR Technology Portugal, S.A.ABSTRACTThe development of Low-Density Fan-Out (LDFO), formerly Wafer Level Fan-Out (WLFO), platforms to encompass the require...» read more
For more than 50 years, the semiconductor industry has enjoyed the benefits of Moore's Law — or so it seemed. In reality, there were three laws rolled up into one: Each process generation would have a higher clock speed at the same power. This was not discovered by Moore, but by Dennard, who also invented the DRAM. Process generations continue to get faster and lower power, but the power...» read more
Packaging houses are readying the next wave of advanced IC packages, hoping to gain a bigger foothold in the race to develop next-generation chip designs.At a recent event, ASE, Leti/STMicroelectronics, TSMC and others described some of their new and advanced IC packaging technologies, which involve various product categories, such as 2.5D, 3D and fan-out. Some new packaging technologies ar...» read more
A new wave of 2.5D/3D, fan-out and other advanced IC packages is expected to flood the market over the next year.The new packages are targeted to address many of the same and challenging applications in the market, such as multi-die integration, memory bandwidth issues and even chip scaling. But the new, advanced IC packages face some technical challenges. And cost remains an issue as advan...» read more
The number of technology options continue to grow for advanced packaging, including new and different ways to incorporate so-called silicon bridges in products.For some time, Intel has offered a silicon bridge technology called Embedded Multi-die Interconnect Bridge (EMIB), which makes use of a tiny piece of silicon with routing layers that connects one chip to another in an IC package. In ...» read more
An Steegen, executive vice president of semiconductor technology and systems at Imec, sat down with Semiconductor Engineering to discuss IC scaling and chip packaging. Imec is working on next-generation transistors, but it is also developing several new technologies for IC packaging, such as a proprietary silicon bridge, a cooling technology and packaging modules. What follows are excerpts of t...» read more
Several packaging houses are developing the next wave of high-density fan-out packages for premium smartphones, but perhaps a bigger battle is brewing in the lower density fan-out arena.Amkor, ASE, STATS ChipPAC and others sell traditional low-density fan-out packages, although some new and competitive technologies are beginning to appear in the market. Low-density fan-out, or sometimes cal...» read more
Several years ago, many predicted the demise of an older interconnect packaging technology called wire bonding, prompting the need for more advanced packaging types.Those predictions were wrong. The semiconductor industry today uses several advanced packaging types, but wire bonding has been reinvented over the years and remains the workhorse in packaging. For example, Advanced Semiconducto...» read more
The electrochemical deposition (ECD) equipment market for IC packaging is heating up as 2.5D, 3D and fan-out technologies begin to ramp.[getentity e_name="Applied Materials"] recently rolled out an ECD system for IC packaging. In addition, Lam Research, TEL and others compete in the growing but competitive ECD equipment market for packaging.ECD—sometimes referred to as pl...» read more
AI export rule to be scrapped; SEMI, EU request; Cadence, Nvidia supercomputer; AI co-processor; Imagination's new GPU; semi sales up; imec, TNO photonics lab; NSF key to national security; flexible packaging control system; SiConic test engineering; USB 4 support; SiC JFETS; magnetic behavior in hematite.
Does the world need another CPU architecture when that no longer reflects the typical workload? Perhaps not, but it may need a bridge to get to where it needs to be.
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