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Home >Manufacturing, Packaging & Materials > When Cleaning Chips Isn’t Clean Enough

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When Cleaning Chips Isn’t Clean Enough

ByGregory Haley - 19 Feb, 2026 - Comments: 0

Key Takeaways Contamination is becoming much more difficult to identify at the most advanced nodes, forcing fabs to rethink how control is achieved. Issues may show up as electrical or statistical anomalies, not particles, and not at time zero. Reliable classification is needed to identify critical contamination and reduce time and effort spent on nuisance failures.For much...» read more

Blog Review: Feb. 18

ByJesse Allen - 18 Feb, 2026 - Comments: 0

Synopsys' Raja Tabet anticipates deployment of an agentic AI workforce within the next 12 to 24 months that can take on different engineering personas, such as a digital implementation agent, a verification agent, or an analog agent, to run experiments in parallel, generate and triage tests, and propose fixes.Cadence's Reela Samuel dives into power usage effectiveness in data centers and wh...» read more

Can A Computer Science Student Be Taught To Design Hardware?

ByLiz Allan - 17 Feb, 2026 - Comments: 2

Key Takeaways New approaches are being devised and tested to address the talent shortage. Leveraging AI in design tools will help engineers become more efficient, and potentially could reduce the time it takes to train engineering students. EDA companies are looking at whether it's possible to train computer science and software engineers to become hardware engineers.A vari...» read more

The Race Begins For Much Bigger Abstractions In Data Centers

ByEd Sperling - 17 Feb, 2026 - Comments: 0

Key Takeaways Data center build-out is enabling much larger and more complex abstractions. Competition is building for digital/virtual twins across multiple industry segments, including automotive, aerospace, and chip manufacturing. AI, and particularly AI agents, will play a significant role in sorting through data to find potential trouble spots.The frenzy of new data cen...» read more

How Siemens Symphony Pro Enabled AnalogPort To Verify Complex Chip Interfaces

BySiemens EDA - 13 Feb, 2026 - Comments: 0

The semiconductor industry's shift toward chiplet-based architectures has created significant mixed-signal verification challenges for high-speed die-to-die interconnects. Traditional verification approaches force difficult trade-offs: Digital mixed-signal (DMS) flows sacrifice analog fidelity, while Analog mixed-signal (AMS) flows struggle with scalability and manual overhead. This paper detai...» read more

Formal Verification Fundamentals Remain Non-Negotiable In The New Verification Revolution

ByNicolae Tusinschi - 12 Feb, 2026 - Comments: 0

The semiconductor industry stands at a critical juncture. First-time silicon success rates have reached all-time lows, while design complexity continues to grow exponentially. System-on-chip designs now integrate billions of transistors, multiple processor cores, complex memory hierarchies, and sophisticated interconnect fabrics. In this environment, the stakes for verification accuracy have ne...» read more

Chiplets And 3D-ICs Add New Electrical And Mechanical Challenges

ByAnn Mutschler - 12 Feb, 2026 - Comments: 1

Key Takeaways• Chiplets and 3D-IC architectures add new thermal-mechanical stresses that can affect the reliability of entire systems.• As chiplets are assembled into packages, defectivity targets become more stringent for each component in a system.• Traditional silos are breaking down, forcing design teams to address issues such as materials choices that previously were handled by...» read more

UCIe’s Major Technical Components Are Now In Place

ByBryon Moyer - 12 Feb, 2026 - Comments: 0

Key Takeaways UCIe 3.0 doubles bandwidth and enhances manageability, addressing new use cases and following an annual update cycle since 2023. The growing demand for chiplet-based architectures in AI data centers is driven by the limitations of monolithic chips, making inter-chiplet communication and connectivity crucial. While UCIe was initially seen as feature-heavy, many of its ma...» read more

Are You Using Structural Patterns In An SLT Environment?

ByPeter Orlando - 10 Feb, 2026 - Comments: 0

Extending the in‑field life of your silicon is essential for long‑term success and for staying ahead of your competitors in today’s rapidly evolving digital world of data centers, automotive and cellular chipsets, and AI applications. For those reasons, it’s increasingly important to test your silicon in a System Level Test (SLT) environment. Testing in an SLT environment offers many be...» read more

Chip Industry Week in Review

ByThe SE Staff - 06 Feb, 2026 - Comments: 1

Intel hired ex-Qualcomm GPU guru Eric Demers for the company's high-performance GPU push, setting the stage for a three-way battle with Nvidia and AMD. The key targets for Intel and AMD will be better power efficiency and a programming model that rivals CUDA, but don't expect Nvidia to stand still.Acquisitions Texas Instruments plans to acquire Silicon Labs for ~$7.5B cash to enhance i...» read more

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