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2.5D

Multiple chips arranged in a planar or stacked configuration with an interposer for communication.

2D Materials

3D NAND

Thanks to 193nm immersion and multiple patterning, flash vendors have extended planar NAND down to the 1xnm node regime. Planar NAND involves the production of horizontal strips of polysilicon. The strips are used to make the wordlines. These, in turn, connect the control gates of the memory cells.

But at the 1xnm node, vendors are struggling to scale the critical element in a NAND device-the floating gate. In fact, the floating gate is seeing an undesirable reduction in the control gate to capacitive coupling ratio.

Realizing that planar NAND is on its last legs, Samsung in 2013 got a jump on its rivals and introduced the industry's first 3D NAND device. Samsung's V-NAND device is a 128 Gbit chip, which stacks 24 vertical layers and consists of 2.5 million channels. More recently, Samsung introduced a 32-layer device and SSDs based on its chips.

In addition, Micron, SK Hynix and Toshiba are also developing 3D NAND.

In 3D NAND, the polysilicon strips are stretched, folded over and stood up vertically. Instead of using a traditional floating gate, 3D NAND uses charge trap technology. Based on silicon nitride films, charge-trap stores the charge on opposite sides of a memory.

One way to illustrate the manufacturing challenges for 3D NAND is to examine Samsung's V-NAND device. Using 30nm to 40nm design rules and a gate-last flow, Samsung's 3D NAND technology is called the Terabit Cell Array Transistor (TCAT). TCAT is a gate-all-around device, where the gate surrounds the channel.

The TCAT flow starts with a CMOS substrate. Then, alternating layers of silicon nitride and silicon dioxide are deposited on the substrate, according to Objective Analysis. This process, which is like making a layer cake, represents the first big challenge in the flow-alternating stack deposition.

Using chemical vapor deposition (CVD), alternating stack deposition involves a process of depositing and stacking thin films layer by layer. The challenge is to deposit the films with good uniformities and low defects. And the challenges escalate as 3D NAND vendors scale their devices beyond 32 layers.

Alternating stack deposition determines the number of layers for a given device. Following that step, a hard mask is applied on the structure and holes are patterned on the top.

Then comes the next hard part. High-aspect ratio trenches are etched from the top of the device to the substrate. The aspect ratios are ten times larger than those in planar. Following the high-aspect ratio etch process, the hole is lined with polysilicon for the channel. The hole is filled with silicon dioxide, which is called a “macaroni channel,” according to Objective Analysis.

Then, columns are formed within the structure using a slit etch process. At that point, the original alternating layers of silicon nitride and silicon dioxide are removed. The final structure looks like a narrow tower with fins, according to Objective Analysis.

Following that step, the peripheral logic must be connected to the control gates. To accomplish that feat, the structure undergoes another difficult step-staircase etch. Using an etcher, the idea is to etch a staircase pattern into the side of the device.

3D Transistors

Transistors where source and drain are added as fins of the gate.

3D-ICs

2.5D and 3D forms of integration

5G

Next-generation wireless technology with higher data transfer rates, low latency, and able to support more devices.

6G

A brief history of design

We start with schematics and end with ESL

A brief history of logic simulation

Important events in the history of logic simulation

A brief history of logic synthesis

Early development associated with logic synthesis

ADAS: Advanced Driver Assistance Systems

Sensing and processing to make driving safer.

Advanced Packaging

Advanced packaging is a general grouping of a variety of distinct techniques, including 2.5D, 3D-IC, fan-out wafer-level packaging and system-in-package.

While putting multiple chips in a package has been around for decades, the driver for advanced packaging is directly correlated with Moore's Law. Wires are shrinking along with transistors, and the amount of distance that a signal needs to travel from one end of a chip over skinny wires is increasing at each node. By connecting these chips together using fatter pipes, which can be in the form of through-silicon vias, interposers, bridges or simple wires, the speed of those signals can be increased and the amount of energy required to drive those signals can be reduced. Moreover, depending on the package, there are fewer physical effects to contend with and components developed at different process nodes can be mixed.

These approaches are now in use across a wide range of products, but initial concerns about cost and time to market continue to slow adoption. That is changing. EDA companies have introduced new tools and flows to automate advanced packaging, and both foundries and OSATs are refining the processes to make it more predictable and less expensive. That is getting a boost by the rising cost of scaling transistors beyond 28nm, as well.

Advanced Packaging Fundamentals eBook (2025-2026)

Agile

An approach to software development focusing on continual delivery and flexibility to changing requirements

Agile Hardware Development

How Agile applies to the development of hardware systems

Air Gap

A way of improving the insulation between various components in a semiconductor by creating empty space.

Amdahl’s Law

The theoretical speedup when adding processors is always limited by the part of the task that cannot benefit from the improvement.

Analog

Semiconductors that measure real-world conditions

Analog circuits

Analog integrated circuits are integrated circuits that make a representation of continuous signals in electrical form.

Analog Design and Verification

The design and verification of analog components.

Application Programming Interface (API)

A software tool used in software programming that abstracts all the programming steps into a user interface for the developer.

Application Specific Integrated Circuit (ASIC)

A custom, purpose-built integrated circuit made for a specific task or product.

Application-Specific Standard Product (ASSP)

An IC created and optimized for a market and sold to multiple companies.

Assertion

Code that looks for violations of a property

Atomic Force Microscopy (AFM), Atomic Force Microscope (AFM)

A method of measuring the surface structures down to the angstrom level.

Atomic Layer Deposition (ALD)

A method of depositing materials and films in exact places on a surface.

Atomic Layer Etch (ALE)

ALE is a next-generation etch technology to selectively and precisely remove targeted materials at the atomic scale.

Automatic Test Equipment (ATE)

Automatic Test Pattern Generation (ATPG)

The generation of tests that can be used for functional or manufacturing verification

Automotive Ethernet, Time Sensitive Networking (TSN)

Time sensitive networking puts real time into automotive Ethernet.

Automotive Standards

Autonomous Vehicles

Avalanche Noise

Noise in reverse biased junctions

AVM

Verification methodology created by Mentor

Backend-of-the-line (BEOL)

IC manufacturing processes where interconnects are made.

Bandgap, Band Gap

Batteries

Devices that chemically store energy.

Behavioral Synthesis

Transformation of a design described in a high-level of abstraction to RTL

Blech Effect

A reverse force to electromigration.

Bluetooth, Bluetooth Low Energy (BLE)

Also known as Bluetooth 4.0, an extension of the short-range wireless protocol for low energy applications.

Brazil

BSIM

Transistor model

Built-in self-test (BiST)

On-chip logic to test a design.

Bunch of Wires (BoW)

Chiplet interconnect specification.

Bus Functional Model

Interface model between testbench and device under test

C, C++

C, C++ are sometimes used in design of integrated circuits because they offer higher abstraction.

Cache Coherent Interconnect for Accelerators (CCIX)

Interconnect standard which provides cache coherency for accelerators and memory expansion peripheral devices connecting to processors.

CD-SEM: Critical-Dimension Scanning Electron Microscope

CD-SEM, or critical-dimension scanning electron microscope, is a tool for measuring feature dimensions on a photomask.

CDC design principles

Making CDC interfaces predictable

Cell-Aware Test

Fault model for faults within cells

Cell-Aware Test for FinFET

Cell-aware test methodology for addressing defect mechanisms specific to FinFETs.

Central Processing Unit (CPU)

The CPU is an dedicated integrated circuit or IP core that processes logic and math.

Characterization/Metrology Lab

A lab that wrks with R&D organizations and fabs involved in the early analytical work for next-generation devices, packages and materials.

Checker

Testbench component that verifies results

Chemical Vapor Deposition (CVD)

A process used to develop thin films and polymer coatings.

China

Chip Design

Design is the process of producing an implementation from a conceptual form

Chip Design and Verification

The design, verification, implementation and test of electronics systems into integrated circuits.

Chip Thermal Interface Protocol

Exchange of thermal design information for 3D ICs

Chiplet Fundamentals For Engineers: 2026 eBook

Chiplets

A chiplet is a discrete unpackaged die that can be assembled into a package with other chiplets; each chiplet is optimized to its function, using the node best suited to the function. The chiplet concept is often referred to as the disaggregation of the system on chip (SoC), using heterogeneous integration techniques to put multiple die or chiplets into a system in package (SiP) or other advanced packaging concept. The technology is still nascent and presents many issues for design, test, manufacturing, and integration teams to work out.

There are several approaches to chiplets. The basic idea is that you have a menu of modular chips, or chiplets, in a library. Then, you assemble chiplets in a package and connect them using a die-to-die interconnect scheme. In theory, the chiplet approach is a fast and less expensive way to assemble various types of third-party chips, such as I/Os, memory and processor cores, in a package.

With an SoC, a chip might incorporate a CPU, plus an additional 100 IP blocks on the same chip. That design is then scaled by moving to the next node, which is an expensive process. With a chiplet model, those 100 IP blocks are hardened into smaller dies or chiplets. In theory, you would have a large catalog of chiplets from various IC vendors. Then, you can mix-and-match them to build a system. Chiplets could be made at different process nodes and re-used in different designs.

A group led by DARPA, as well as Marvell, zGlue and others are pursuing chiplet technology, which is a different way of integrating multiple dies in a package or system.

Commercial vendors
Marvell and Kandou Bus were the first to jump on the chiplet concept. They announced a deal in 2016 under which Marvell would use Kandou’s chip-to-chip interconnect technology to tie multiple chips together. Kandou is developing an ecosystem of small and midsize companies, and has agreed to give up some of its IP to others to jump-start this approach. Marvell is building a switch based on Kandou’s interconnect technology.

DARPA’s approach
In 2016, DARPA released a solicitation for bids from outside companies for its CHIPS program. The goal was (and still is) to devise a modular design and manufacturing flow for chiplets. DARPA also plans to develop a large catalog of third-party chiplets for commercial and military apps. All told, the CHIPS flow is expected to lead to a 70% reduction in design cost and turn-around times.

The CHIPS program started in 2017. The program has various types of contractors/sub-contractors—manufacturers (Intel, Northrop, Micross and UCLA); chiplet developers (Ferric, Jariet, Micron, Synopsys, and University of Michigan); and EDA suppliers (Cadence and Georgia Institute of Technology).

Clock Domain Crossing (CDC)

Asynchronous communications across boundaries

Clock Gating

Dynamic power reduction by gating the clock

Clock Tree Optimization

Design of clock trees for power reduction

CMOS

Complementary metal-oxide semiconductor (CMOS) is a fabrication technology for semiconductor systems that can be used for the construction of digital circuitry, memories and some analog circuits. The technology is based on the pairing of two metal oxide semiconductor field effect transistors (MOSFET), one of which is a p-type and the other an n-type transistor. The term metal oxide semiconductor is a reference to the traditional structure of the device where there would be a metal gate on top of an oxide layer on top of a semiconductor. Today, the metal layer is replaced by a polysilicon layer most of the time.

CMOS dissipates power in two primary ways. When they are switching, there is a momentary short circuit across the transistor pair. Also, switching has to dissipate any stored charge (load capacitance) on the electrical connector between it and any other switches connected to it within the circuit. This is referred to as dynamic power. For older geometries, this was the majority of the power consumed by such devices. In more modern devices, the second power draw, when the device is remaining in the same state, has become more important. This is leakage power and may be a significant percentage of total power consumption.

Co-Packaged Optics

Code Coverage

Metrics related to about of code executed in functional verification

Combinatorial Equivalence Checking

Verify functionality between registers remains unchanged after a transformation

Compiled-code Simulation

Faster form for logic simulation

Complementary FET (CFET)

Complementary FET, a new type of vertical transistor.

Compound Semiconductors

Combinations of semiconductor materials.

Compute Express Link (CXL)

Interconnect between CPU and accelerators.

Contact

The structure that connects a transistor with the first layer of copper interconnects.

Convolutional Neural Network (CNN)

A technique for computer vision based on machine learning.

Coverage

Completion metrics for functional verification

Crosstalk

Interference between signals

Crypto processors

Crypto processors are specialized processors that execute cryptographic algorithms within hardware.

Current Intellectual Property Companies

Companies supplying IP or IP services

Dark Silicon

A method of conserving power in ICs by powering down segments of a chip when they are not in use.

Data Analytics

Data analytics uses AI and ML to find patterns in data to improve processes in EDA and semi manufacturing.

Debug

The removal of bugs from a design

Deep Learning (DL)

Deep learning is a subset of artificial intelligence where data representation is based on multiple layers of a matrix.

Definitions

Dennard’s Law

An observation that as features shrink, so does power consumption.

Deposition

Design for Manufacturing (DFM)

Actions taken during the physical design stage of IC development to ensure that the design can be accurately manufactured.

Design for Test (DFT)

Techniques that reduce the difficulty and cost associated with testing an integrated circuit.

Design Patent

Protection for the ornamental design of an item

Design Rule Checking (DRC)

A physical design process to determine if chip satisfies rules defined by the semiconductor manufacturer

Design Rule Pattern Matching

Locating design rules using pattern matching techniques.

Device Noise

Sources of noise in devices

DFT and Clock Gating

Insertion of test logic for clock-gating

Diamond Semiconductors

A wide-bandgap synthetic material.

Digital IP

Categorization of digital IP

Digital Oscilloscope

Allowed an image to be saved digitally

Digital Signal Processor (DSP)

A digital signal processor is a processor optimized to process signals.

Digital Twins

A digital representation of a product or system.

Directed Self-Assembly (DSA)

A complementary lithography technology.

DNA biometrics

DNA analysis is based upon unique DNA sequencing.

Domain/Distributed Architecture

Double Data Rate (DDR)

Double Patterning

A patterning technique using multiple passes of a laser.

Double Patterning Methodologies

Colored and colorless flows for double patterning

DRAM: Dynamic Random Access Memory

Dynamic random access memory (DRAM) stores data in a capacitor. These capacitors leak charge so the information fades unless the charge is refreshed periodically. Because of this refresh requirement, it is a dynamic memory as opposed to SRAM and other static memory.

The advantage of DRAM is its structural simplicity: only one transistor and a capacitor are required per bit, compared with six transistors in SRAM. This allows DRAM to reach very high density.

Ferroelectric RAM (FeRAM or FRAM) is a random access memory similar in construction to DRAM but uses a ferroelectric layer instead of a dielectric layer to achieve non-volatility.

In today's systems, the memory/storage hierarchy is straightforward. SRAM is integrated into the processor for cache. DRAM is used for main memory. Disk drives and solid-state storage drives are used for storage.

DRAM is based on a one-transistor, one-capacitor (1T1C) cell structure. The cells are arranged in a rectangular, grid-like array. In simple terms, a voltage is applied to the transistor in the DRAM cell. The voltage is then given a data value. It is then placed on a bit-line. This, in turn, charges the storage capacitor. Each bit of data is then stored in the capacitor.

Over time, the charge in the capacitor will leak or discharge when the transistor is turned off. So, the stored data in the capacitor must be refreshed every 64 milliseconds.

The industry has managed to scale the DRAM for decades. But soon, the DRAM will run out of steam, as it is becoming more difficult to scale the 1T1C cell. Beyond 20nm, the DRAM is expected to scale two or three iterations in the 1xnm regime, which is referred to as 1xnm, 1ynm and 1znm.

Several types of DRAM were being developed in the early 2000's that used characteristics of silicon on insulator (SOI). Instead of using a capacitor to store the value, the floating body effect inherent in the manufacturing process is used. Several commercial variants such as the Twin Transistor RAM (TTRAM) were being developed by Renesas and the Z-RAM Zero capacitor RAM by the now defunct company Innovative Silicon (Micron owns its patents). Improvements in SRAM manufacturing negated any benefits of these

The DRAM was invented by Dr. Robert Dennard at the IBM Thomas J. Watson Research Center in 1966.

Dynamic Voltage and Frequency Scaling (DVFS)

Dynamically adjusting voltage and frequency for power reduction

e

Hardware Verification Language

E-beam Inspection

A slower method for finding smaller defects.

E-Beam Lithography

Lithography using a single beam e-beam tool

Edge AI

Edge Placement Error (EPE)

The difference between the intended and the printed features of an IC layout.

Electromigration

Electromigration (EM) due to power densities

Electronic Design Automation (EDA)

Electronic Design Automation (EDA) is the industry that commercializes the tools, methodologies and flows associated with the fabrication of electronic systems.

Electronic System Level (ESL)

Levels of abstraction higher than RTL used for design and verification

Electrostatic Discharge (ESD)

Transfer of electrostatic charge.

Embedded FPGA (eFPGA)

An eFPGA is an IP core integrated into an ASIC or SoC that offers the flexibility of programmable logic without the cost of FPGAs.

Emulation

Special purpose hardware used for logic verification

Energy Harvesting

Capturing energy from the environment

Environmental Noise

Noise caused by the environment

Epitaxy

A method for growing or depositing mono crystalline films on a substrate.

eRM

Reuse methodology based on the e language

Error Correction Code (ECC)

Methods for detecting and correcting errors.

Ethernet

Ethernet is a reliable, open standard for connecting devices by wire.

EUV: Extreme Ultraviolet Lithography

EUV lithography is a soft X-ray technology.

Failure Analysis

Finding out what went wrong in semiconductor design and manufacturing.

Fan-Outs

A way of including more features that normally would be on a printed circuit board inside a package.

Fault Simulation

Evaluation of a design under the presence of manufacturing defects

Ferroelectric FETs (FeFET)

Ferroelectric FET is a new type of memory.

Field Programmable Gate Array (FPGA)

Reprogrammable logic device

FinFET

A three-dimensional transistor.

Flash Memory

Flash memory is a modern form of erasable memory. Whereas EEPROM was erased in bulk, flash allows more selective erasure.

The concept was developed by Dr. Fujio Masuoka of Toshiba. It was presented at the 1984 IEEE International Electron Devices Meeting, IEDM held in San Francisco, California. Intel introduced the NOR chip in 1988; Toshiba introduced the NAND type chip in 1991.

Most commercially available flash products are guaranteed to withstand between 100,000 and 1,000,000 program/erase cycles.

With NOR flash, the memory cells are connected in parallel enabling the device to have better random access. NAND flash is optimized for density and access is performed in a serial manner. This reduces the amount of access circuitry required. For this reason NOR has traditionally been used for code access and NAND for data access.

Flexible Hybrid Electronics (FHE)

Integrated circuits on a flexible substrate

FlexRay ISO 17458

An automotive communications protocol

Flicker Noise

Noise related to resistance fluctuation

Flip-Chip

A type of interconnect using solder balls or microbumps.

Forksheet FET

A transistor type with integrated nFET and pFET.

Formal Verification

Formal verification involves a mathematical proof to show that a design adheres to a property

Foundry, pure-play foundry

A company that specializes in manufacturing semiconductor devices.

Functional Coverage

Coverage metric used to indicate progress in verifying functionality

Functional Design and Verification

Functional Design and Verification is currently associated with all design and verification functions performed before RTL synthesis.

Functional Verification

Functional verification is used to determine if a design, or unit of a design, conforms to its specification.

Gage R&R, Gage Repeatability And Reproducibility

A statistical method for determining if a test system is production ready by measuring variation during test for repeatability and reproducibility.

Gallium Nitride (GaN)

GaN is a III-V material with a wide bandgap.

Gate-All-Around FET (GAA FET)

A transistor design with a gate is placed on all four sides of the channel.

Gate-Level Power Optimizations

Power reduction techniques available at the gate level.

Generation-Recombination Noise

noise related to generation-recombination

Generative Adversarial Network (GAN)

A neural network framework that can generate new data.

Germany

Germany is known for its automotive industry and industrial machinery.

Graphene

Graphene is two dimensional allotrope of carbon in which carbon atoms are arranged in a hexagonal pattern in a single, one atom thick layer. It is widely credited as spurring research into many other 2D materials.

The material had been theorized and observed on surfaces for decades, but in 2004 graphene was isolated and characterized by Andre Geim and Kostya Novoselov at the University of Manchester, research that earned them the 2010 Nobel Prize in Physics. The researchers used sticky tape to remove flakes from bulk graphite then repeatedly separated the flakes.

Graphene has no band gap and conducts electricity extremely well, with electron mobility at room temperature reported to be over 15000 cm2⋅V−1⋅s−1. Thermal conductivity is high, and the material is also nearly transparent and around 100 times stronger than steel in proportion to its thickness.

While graphene and other 2D materials can be isolated in small quantities in research environments using mechanical exfoliation (the sticky tape method), making it on a commercial level is more difficult. One alternative, electrochemical intercalation, infiltrates an inert molecule into a chemical vapor deposition film, chemically isolating the top layer while continuing to use the substrate for mechanical support. Another depends on atomic layer deposition of individual layers, followed by a passivation layer. Layer-by-layer deposition methods can be used to construct van der Waals heterostructures, in which a stack is held together by van der Waals forces while each layer retains its 2-D character.

Graphics Double Data Rate (GDDR)

Graphics Processing Unit (GPU)

An electronic circuit designed to handle graphics and video.

Guard Banding

Adding extra circuits or software into a design to ensure that if one part doesn't work the entire system doesn't fail.

Hard IP

Fully designed hardware IP block

Hardware Assisted Verification

Use of special purpose hardware to accelerate verification

Hardware Modeler

Historical solution that used real chips in the simulation process

hardware/software co-design

Optimizing the design by using a single language to describe hardware and software.

Heat Dissipation

Power creates heat and heat affects power

Heterogeneous Integration

The process of integrating different chips, chiplets, and chip components into packages.

High-Bandwidth Memory (HBM)

A dense, stacked version of memory with high-speed interfaces that can be used in advanced packaging.

High-Density Advanced Packaging (HDAP)

An umbrella term (circa 2015) for advanced packaging in semiconductors.

High-Level Synthesis (HLS)

Synthesis technology that transforms an untimed behavioral description into RTL

HSA Platform System Architecture Specification

Defines a set of functionality and features for HSA hardware

HSA Runtime Programmer’s Reference Manual

Runtime capabilities for the HSA architecture

Hybrid Bonding

IC Types

What are the types of integrated circuits?

IEEE 1076-VHSIC HW Description Language

Hardware Description Language

IEEE 1076.1-Analog & Mixed-Signal

Analog extensions to VHDL

IEEE 1076.1.1-VHDL-AMS Standard Packages

A collection of VHDL 1076.1 packages

IEEE 1076.4-VHDL Synthesis Package – Floating Point

Modeling of macro-cells in VHDL

IEEE 1149 Boundary Scan Test

Boundry Scan Test

IEEE 1364-Verilog

IEEE ratified version of Verilog

IEEE 1364.1-Verilog RTL Synthesis

Standard for Verilog Register Transfer Level Synthesis

IEEE 1532- in-system programmability (ISP)

Extension to 1149.1 for complex device programming

IEEE 1647-Functional Verification Language e

Functional verification language

IEEE 1666-Standard SystemC

SystemC

IEEE 1685-IP-XACT

Standard for integration of IP in System-on-Chip

IEEE 1687-IEEE Standard for Access and Control of Instrumentation Embedded

IEEE Standard for Access and Control of Instrumentation Embedded within a Semiconductor Device

IEEE 1800-SystemVerilog

IEEE ratified version of SystemVerilog

IEEE 1800.2–UVM

Universal Verification Methodology

IEEE 1801-Design/Verification of Low-Power, Energy-Aware UPF

IEEE Standard for Design and Verification of Low-Power Integrated Circuits also known by its Accellera name of Unified Power Format (UPF)

IEEE 1838: Test Access Architecture for 3D Stacked IC

Standard for Test Access Architecture for Three-Dimensional Stacked Integrated Circuits

IEEE 1850-Property Specification Language (PSL)

Verification language based on formal specification of behavior

IEEE 802.1-Higher Layer LAN Protocols

IEEE 802.1 is the standard and working group for higher layer LAN protocols.

IEEE 802.11-Wireless LAN

IEEE 802.11 working group manages the standards for wireless local area networks (LANs).

IEEE 802.15-Wireless Specialty Networks (WSN)

IEEE 802.15 is the working group for Wireless Specialty Networks (WSN), which are used in IoT, wearables and autonomous vehicles.

IEEE 802.18-Radio Regulatory TAG

"RR-TAG" is a technical advisory group supporting IEEE standards groups working on 802.11, 802.12, 802.16, 802.20, 802.21, and 802.22.

IEEE 802.19-Wireless Coexistence

Standards for coexistence between wireless standards of unlicensed devices.

IEEE 802.3-Ethernet

IEEE 802.3-Ethernet working group manages the IEEE 802.3-Ethernet standards.

IEEE P2415: Unified HW Abstraction & Layer for Energy Proportional Electronic Systems

Standard for Unified Hardware Abstraction and Layer for Energy Proportional Electronic Systems

IEEE P2416-Power Modeling

Power Modeling Standard for Enabling System Level Analysis

IEEE-ISTO 5001 (Nexus 5001) — embedded processor debug

IIoT: Industrial Internet of Things

Specific requirements and special consideration for the Internet of Things within an Industrial setting.

Impact of lithography on wafer costs

Wafer costs across nodes

Implementation Power Optimizations

Power optimization techniques for physical implementation

In-Memory Computing

Performing functions directly in the fabric of memory.

Induced Gate Noise

Thermal noise within a channel

Insulated-Gate Bipolar Transistors (IGBT)

IGBTs are combinations of MOSFETs and bipolar transistors.

Integrated Device Manufacturer (IDM)

A semiconductor company that designs, manufactures, and sells integrated circuits (ICs).

Inter Partes Review

Method to ascertain the validity of one or more claims of a patent

Interconnects

Interconnects (BEOL)

Buses, NoCs and other forms of connection between various elements in an integrated circuit.

Internet of Things (IoT)

Also known as the Internet of Everything, or IoE, the Internet of Things is a global application where devices can connect to a host of other devices, each either providing data from sensors, or containing actuators that can control some function. Data can be consolidated and processed on mass in the Cloud.

Interposers

Fast, low-power inter-die conduits for 2.5D electrical signals.

Inverse Lithography Technology (ILT)

Finding ideal shapes to use on a photomask.

Ion Implants

Injection of critical dopants during the semiconductor manufacturing process.

IP-XACT

Standard for integration of IP in System-on-Chip

IR Drop

The voltage drop when current flows through a resistor.

ISO 21434 / SAE 21434 Standard – Automotive cybersecurity

ISO 26262 – Functional safety

Standard related to the safety of electrical and electronic systems within a car

ISO/PAS 21448 – SOTIF

Standard to ensure proper operation of automotive situational awareness systems.

ISO/SAE FDIS 21434-Road Vehicles — Cybersecurity Engineering

A standard (under development) for automotive cybersecurity.

Israel

Issues

Koomey’s Law

The energy efficiency of computers doubles roughly every 18 months.

Large Language Models (LLMs)

Laws

Theories have been influential and are often referred to as "laws" and are discussed in trade publications, research literature, and conference presentations as "truisms" that eventually have limits.

Layout versus Schematic Checking (LVS)

Device and connectivity comparisons between the layout and the schematic

Level Shifters

Cells used to match voltages across voltage islands

Line Edge Roughness (LER)

Deviation of a feature edge from ideal shape.

Lint

Removal of non-portable or suspicious code

Litho Etch Litho Etch (LELE)

LELE is a form of double patterning

Litho Freeze Litho Etch

A type of double patterning.

Lithography

Light used to transfer a pattern from a photomask onto a substrate.

Lithography k1 coefficient

Coefficient related to the difficulty of the lithography process

Logic Resizing

Correctly sizing logic elements

Logic Restructuring

Restructuring of logic for power reduction

Logic Simulation

A simulator is a software process used to execute a model of hardware

Low Power Double Data Rate (LPDDR)

Low Power Methodologies

Methodologies used to reduce power consumption.

Low Power Verification

Verification of power circuitry

Low-Power Design

Machine Learning (ML)

An approach in which machines are trained to favor basic behaviors and outcomes rather than explicitly programmed to do certain tasks. That results in optimization of both hardware and software to achieve a predictable range of results.

Magnetoresistive RAM (MRAM)

Uses magnetic properties to store data

Makimoto’s Wave

Observation related to the amount of custom and standard content in electronics.

Manufacturing Execution System (MES)

Tracking a wafer through the fab.

Manufacturing Noise

Noise sources in manufacturing

MEMS

Microelectromechanical Systems are a fusion of electrical and mechanical engineering and are typically used for sensors and for advanced microphones and even speakers.

Metal Organic Chemical Vapor Deposition (MOCVD)

A key tool for LED production.

Metastability

Unstable state within a latch

Metcalfe’s Law

Observation that relates network value being proportional to the square of users

Methodologies and Flows

Describes the process to create a product

Metrology

Metrology is the science of measuring and characterizing tiny structures and materials.

Microcontroller (MCU)

A type of processor that traditionally was a scaled-down, all-in-one embedded processor, memory and I/O for use in very specific operations.

Microprocessor, Microprocessor Unit (MPU)

The integrated circuit that first put a central processing unit on one chip of silicon.

Mixed-Signal

The integration of analog and digital.

Models

Models and Abstractions

Models are abstractions of devices

Molded Interconnect Substrate (MIS)

A midrange packaging option that offers lower density than fan-outs.

Monolithic 3D Chips

A way of stacking transistors inside a single chip instead of a package.

Moore’s Law

Observation related to the growth of semiconductors by Gordon Moore.

Multi-Beam e-Beam Lithography

An advanced form of e-beam lithography

Multi-chip Modules (MCM)

An early approach to bundling multiple functions into a single package.

Multi-Corner Multi-Mode (MCMM) Analysis

Increasing numbers of corners complicates analysis. Concurrent analysis holds promise.

Multi-Die Assemblies

Multi-site testing

Using a tester to test multiple dies at the same time.

Multi-Vt

Use of multi-threshold voltage devices

Multiple Patterning

A way to image IC designs at 20nm and below.

Nanoimprint Lithography

A hot embossing process type of lithography.

Nanosheet FET

A type of field-effect transistor that uses wider and thicker wires than a lateral nanowire.

Near Threshold Computing

Optimizing power by computing below the minimum operating voltage.

Near-Memory Computing

Moving compute closer to memory to reduce access costs.

Negative Bias Temperature Instability (NBTI)

NBTI is a shift in threshold voltage with applied stress.

Network on Chip (NoC)

An in-chip network, often in a SoC, that connects IP blocks and components and routes data packets among them.

Neural Networks

A method of collecting data from the physical world that mimics the human brain.

Neuromorphic Computing

A compute architecture modeled on the human brain.

Nodes

Nodes in semiconductor manufacturing indicate the features that node production line can create on an integrated circuit, such as interconnect pitch, transistor density, transistor type, and other new technology.

Noise

Random fluctuations in voltage or current on a signal.

Non-Volatile Memory (NVM)

Memory in which information is retained even when a power source is not present.

Non-volatile memory is becoming more complicated at advanced nodes, where price, speed, power and utilization are feeding into some very application-specific tradeoffs about where to place that memory. NVM's capacity is hard to scale at smaller geometries, and it needs higher voltages to program the cells. More die area may be needed to support capacities required by the additional processing cores at finer process geometries, and additional manufacturing cost may be required to support higher voltages.1

NVM can be embedded into a chip, or it can be moved off chip with various types of interconnect technology. But that decision is more complicated than it might first appear. It depends on the process node, the voltage, the type of NVM and what’s being stored in it, as well as the overall chip or system budget. It is a balancing act between the power/performance improvements of smaller geometries and how much memory can be embedded cost-effectively.

Fundamentally, there are two types of NVM:

Multi-time programmable (MTP) NVM can be programmed many times.
One-time programmable (OTP) NVM can be programmed once.

Some MTP NVM will work with a standard CMOS process, whereby no extra steps or masks are involved. Because they can be manufactured using a standard CMOS process, these MTP NVMs can continue to be scaled, but they require a floating gate, like a flash cell. A charge is trapped on a floating gate.

Then there’s the regular gate and the transistor. When you erase it, you remove the charge from the floating gate. Also, this floating gate requires a thicker oxide, and not all processes offer that. This is why MTP scaling basically stopped at 40nm and 28nm. Beyond that, it’s difficult to do it because the oxide thickness is not there to do to make it happen.

However, if NVM could be embedded in the same logic process without having to make tweaks to the process, then the costs are more manageable, and this is exactly what Synopsys was after with its acquisition of Sidense and Kilopass, both of which developed versions of OTP NVM.

The OTP technology doesn’t require the thicker oxide that is required for the MTP, and there is no floating gate.

1 MUTSCHLER, Ann. "Non-Volatile Memory Tradeoffs Intensify," Semiconductor Engineering, JANUARY 22ND, 2020, https://semiengineering.com/non-volatile-memory-tradeoffs-intensify/

Open Verification Methodology (OVM)

Verification methodology created from URM and AVM

Operand Isolation

Disabling datapath computation when not enabled

Optical Inspection

Method used to find defects on a wafer.

Optical Lithography

Optical Proximity Correction (OPC)

A way to improve wafer printability by modifying mask patterns.

Original Equipment Manufacturer (OEM)

The company that buys raw goods, including electronics and chips, to make a product.

Outsourced Semiconductor Assembly and Test (OSAT)

Companies who perform IC packaging and testing - often referred to as OSAT

Overlay

The ability of a lithography scanner to align and print various layers accurately on top of each other.

package-on-package (PoP)

Part Average Testing (PAT)

Outlier detection for a single measurement, a requirement for automotive electronics.

Patterning

PCI Express (PCIe), Peripheral Component Interconnect Express

High-speed serial expansion bus for connecting sending data between devices.

Pellicle

A thin membrane that prevents a photomask from being contaminated.

Phase-Change Memory

Memory that stores information in the amorphous and crystalline phases.

Photomask

A template of what will be printed on a wafer.

Photonic Integrated Circuit (PIC)

Photonics

Photoresist

Light-sensitive material used to form a pattern on the substrate.

Physical AI

Physical Design

Design and implementation of a chip that takes physical placement, routing and artifacts of those into consideration.

Physical Layer (PHY)

Physically connects devices and is the conduit that encodes, decodes bits of data.

Physical Vapor Deposition (PVD)

PVD is a deposition method that involves high-temperature vacuum evaporation and sputtering.

Physical Verification

Making sure a design layout works as intended.

Physically Unclonable Functions (PUFs)

A set of unique features that can be built into a chip but not cloned.

Pin Swapping

Lowering capacitive loads on logic

Planar

PODEM

An algorithm used ATPG

Portable Stimulus (PSS)

Hardware Verification Language, PSS is defined by Accellera and is used to model verification intent in semiconductor design.

Power Consumption

Components of power consumption

Power Cycle Sequencing

Power domain shutdown and startup

Power Definitions

Definitions of terms related to power

Power Delivery Network (PDN)

Moving power around a device.

Power Estimation

How is power consumption estimated

Power Gating

Reducing power by turning off parts of a design

Power Gating Retention

Special flop or latch used to retain the state of the cell when its main power supply is shut off.

Power Isolation

Addition of isolation cells around power islands

Power Issues

Power reduction at the architectural level

Power Management Coverage

Ensuring power control circuitry is fully verified

Power Management IC (PMIC)

An integrated circuit that manages the power in an electronic device or module, including any device that has a battery that gets recharged.

Power MOSFETs

A power semiconductor used to control and convert electric power.

Power Semiconductors

A power IC is used as a switch or rectifier in high voltage power applications.

Power Semiconductors Report: A Deep Dive Into Materials, Manufacturing & Business

Power Supply Noise

Noise transmitted through the power delivery network

Power Switching

Controlling power for power shutoff

Power Techniques

Power-Aware Design

Techniques that analyze and optimize power in a design

Power-Aware Test

Test considerations for low-power circuitry

PPA (Power, Performance, Area)

Fundamental tradeoffs made in semiconductor design for power, performance and area.

Printed Circuit Board (PCB)

The design, verification, assembly and test of printed circuit boards

Process

Process Power Optimizations

power optimization techniques at the process level

Process Variation

Variability in the semiconductor manufacturing process

Processor Utilization

A measurement of the amount of time processor core(s) are actively in use.

Processors

An integrated circuit or part of an IC that does logic and math processing.

Property Specification Language

Verification language based on formal specification of behavior

Quantum Computing

A different way of processing data using qubits.

Radio Frequency (RF)

Issues that pertain to Radio Frequency (RF) analog

Random Telegraph Noise

Random trapping of charge carriers

Rapid Thermal Anneal (RTA), Rapid Thermal Processing (RTP)

The process of rapidly heating wafers.

Redistribution Layers (RDLs)

Copper metal interconnects that electrically connect one part of a package to another.

Reliability Verification

Design verification that helps ensure the robustness of a design and reduce susceptibility to premature or catastrophic electrical failures.

ReRAM materials

Materials used to manufacture ReRAMs

Resistive RAM (ReRAM/RRAM)

Memory utilizing resistive hysteresis

Reticle

Synonymous with photomask.

Rich Interactive Test Database (RITdb)

A proposed test data standard aimed at reducing the burden for test engineers and test operations.

RISC-V

An open-source ISA used in designing integrated circuits at lower cost.

Root of Trust

Trusted environment for secure functions.

RTL (Register Transfer Level)

An abstraction for defining the digital portions of a design

RTL Power Optimizations

Optimization of power consumption at the Register Transfer Level

RTL Signoff

A series of requirements that must be met before moving past the RTL phase

RVM

Verification methodology based on Vera

SAT Solver

Algorithm used to solve problems

Scan Test

Additional logic that connects registers into a shift register or scan chain for increased test efficiency.

Scoreboard

Mechanism for storing stimulus in testbench

SCV SystemC Verification

Testbench support for SystemC

Self-Aligned Double Patterning (SADP)

A form of double patterning.

Sensor Fusion

Combining input from multiple sensor types.

Sensor Signal Conditioner (SSC)

An IC that conditions an analog sensor signal and converts to it digital before sending to a microcontroller.

Sensors

Sensors are a bridge between the analog world we live in and the underlying communications infrastructure.

serializer/deserializer (SerDes)

A transmission system that sends signals over a high-speed connection from a transceiver on one chip to a receiver on another. The transceiver converts parallel data into serial stream of data that is re-translated into parallel on the receiving end.

Shift Left

In semiconductor development flow, tasks once performed sequentially must now be done concurrently.

Shmooing, Shmoo test, Shmoo plot

Sweeping a test condition parameter through a range and obtaining a plot of the results.

Short Channel Effects

When channel lengths are the same order of magnitude as depletion-layer widths of the source and drain, they cause a number of issues that affect design.

Shot Noise

Quantization noise

Side Channel Attacks

A class of attacks on a device and its contents by analyzing information using different access methods.

Silent Data Corruption (SDC)

Undetected errors in data output from an integrated circuit.

Silicon Carbide (SiC)

A wide-bandgap technology used for FETs and MOSFETs for power transistors.

Silicon Photonics

The integration of photonic devices into silicon

Simulation

A simulator exercises of model of hardware

Simulation Acceleration

Special purpose hardware used to accelerate the simulation process.

Simultaneous Switching Noise

Disturbance in ground voltage

Small Language Models (SLMs)

Soft IP

Synthesizable IP block

Software-Defined Vehicles (SDV)

Software-Driven Verification

Verification methodology utilizing embedded processors

Software/Hardware Interface for Multicore/Manycore (SHIM) processors

Defines an architecture description useful for software design

SPICE

Circuit Simulator first developed in the 70s

Spiking Neural Network (SNN)

A type of neural network that attempts to more closely model the brain.

Spin-Orbit Torque MRAM (SOT-MRAM)

A type of MRAM with separate paths for write and read.

Standard Essential Patent

A patent that has been deemed necessary to implement a standard.

Standard Test Data Format (STDF)

The most commonly used data format for semiconductor test information.

Standards

Standards are important in any industry.

Startup Funding in China eBook: Notable investments in the semiconductor industry

Static Random Access Memory (SRAM)

SRAM is a volatile memory that does not require refresh

Stimulus Constraints

Constraints on the input to guide random generation process

Stochastics, Stochastic-Induced Defects

Random variables that cause defects on chips during EUV lithography.

STT-MRAM

An advanced type of MRAM

Substrate Biasing

Use of Substrate Biasing

Substrate Noise

Coupling through the substrate.

System In Package (SiP)

A method for bundling multiple ICs to work together as a single chip.

System on Chip (SoC)

A system on chip (SoC) is the integration of functions necessary to implement an electronic system onto a single substrate and contains at least one processor

SystemC

A class library built on top of the C++ language used for modeling hardware

SystemC-AMS

Analog and mixed-signal extensions to SystemC

SystemVerilog

Industry standard design and verification language

Tensor Processing Unit (TPU)

Google-designed ASIC processing unit for machine learning that works with TensorFlow ecosystem.

Testbench

Software used to functionally verify a design

Thermal Noise

Noise related to heat

Through-Silicon Vias (TSVs)

Through-Silicon Vias are a technology to connect various die in a stacked die configuration.

Trace

Transistors

Basic building block for both analog and digital integrated circuits.

Transition Rate Buffering

Minimizing switching times

Triple Patterning

A multi-patterning technique that will be required at 10nm and below.

Tunnel FET

A type of transistor under development that could replace finFETs in future process technologies.

UL 4600 – Standard for Safety for the Evaluation of Autonomous Products

Standard for safety analysis and evaluation of autonomous vehicles.

Unified Coverage Interoperability Standard (Verification)

The Unified Coverage Interoperability Standard (UCIS) provides an application programming interface (API) that enables the sharing of coverage data across software simulators, hardware accelerators, symbolic simulations, formal tools or custom verification tools.

Unified Power Format (UPF)

Accellera Unified Power Format (UPF)

Universal Chiplet Interconnect Express (UCIe)

Die-to-die interconnect specification.

Universal Verification Methodology (UVM)

Verification methodology

URM

SystemVerilog version of eRM

Utility Patent

Patent to protect an invention

Vera

Hardware Verification Language

Verification

Verification IP (VIP)

A pre-packaged set of code used for verification.

Verification Methodologies

A standardized way to verify integrated circuit designs.

Verification Plan

A document that defines what functional verification is going to be performed

Verilog

Hardware Description Language in use since 1984

Verilog Procedural Interface

Procedural access to Verilog objects

Verilog-AMS

Analog extensions to Verilog

VHDL

Hardware Description Language

Virtual Prototype

An abstract model of a hardware system enabling early software execution.

VMM

Verification methodology built by Synopsys

Voice control, speech recognition, voice-user interface (VUI)

Using voice/speech for device command and control.

Volatile Memory

Memory that loses storage abilities when power is removed.

Voltage Islands

Use of multiple voltages for power reduction

Von Neumann Architecture

The basic architecture for most computing today, based on the principle that data needs to move back and forth between a processor and memory.

Wafer Fab Testing

Verifying and testing the dies on the wafer after the manufacturing.

Wafer Inspection

The science of finding defects on a silicon wafer.

Wi-Fi

A brand name for a group of wireless networking protocols and technology,

Wide I/O: memory interface standard for 3D IC

3D memory interface standard

Wirebonding

Creating interconnects between IC and package using a thin wire.

Wireless

A way of moving data without wires.

X Architecture

IC interconnect architecture

X Verification

X Propagation causes problems

Yield Management System (YMS)

A data-driven system for monitoring and improving IC yield and reliability.

Zero-Day Vulnerabilities, Attacks

A vulnerability in a product’s hardware or software discovered by researchers or attackers that the producing company does not know about and therefore does not have a fix for yet.