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Top Stories

Can A Computer Science Student Be Taught To Design Hardware?

To fill the talent gap, CS majors could be taught to design hardware, and the EE curriculum could be adapted or even shortened.
Published on February 17th, 2026 byLiz Allan

Does Your RISC-V Core Meet The Standard?

Verifying an extensible processor is more than a one-step process, especially when software compatibility is important.
Published on January 29th, 2026 byBrian Bailey

Multi-Die Assemblies Require More Detailed Test Plan Earlier

Understanding connectivity issues and interactions are only part of the problem; ECOs can cause unexpected problems in other areas.
Published on January 29th, 2026 byAnn Mutschler

Startup Funding: Q4 2025

More and bigger funding rounds for AI chips and AI for making chips; 75 companies raise $3 billion.
Published on January 19th, 2026 byJesse Allen

When To Move To Multi-Die Assemblies

Multiple factors are involved in deciding when and whether to disaggregate a planar SoC.
Published on December 23rd, 2025 byAnn Mutschler

2025 – A Year Of Change And Anticipation

Unexpected change rewards those who are quick to adjust, but all aspects of a system must be adjusted to keep growth going.
Published on December 23rd, 2025 byBrian Bailey

Programmable Chips Evolve For Shifting Needs

Designers are utilizing an array of programmable or configurable ICs to keep pace with rapidly changing technology and AI. DSPs remain key.
Published on December 23rd, 2025 byLiz Allan

AI Plays Multiple Roles Within EDA

The application of AI into design tools and flows will take several forms, each independent, but all potentially working together.
Published on November 25th, 2025 byBrian Bailey

FPGAs Find New Workloads In The High-Speed AI Era

Growing use cases include life science AI, reducing memory and I/O bottlenecks, data prepping, wireless networking, and as insurance for evolving p...
Published on November 25th, 2025 byLiz Allan

The Real-World Impact Of Silicon Lifecycle Management On ...

Designing resilient chips with SLM can help combat aging effects, security threats, and get to market faster with higher yields.
Published on November 25th, 2025 byAnn Mutschler

More Top Stories »



Round Tables

The Future For Formal Verification

Will a formal specification be part of the future, or will we continue to see natural language specifications? Will formal successfully break out o...
Published on November 19th, 2025 byBrian Bailey

Formal Verification’s Value Grows

But to increase adoption, formal tools have to lower barriers and make it possible for a wider group of people to be able to deploy successfully. L...
Published on November 5th, 2025 byBrian Bailey

Advances In Formal Verification Technology

It's the only way to prove that a design is correct. Recent advances continue to make it better.
Published on October 30th, 2025 byBrian Bailey

How 3D-IC Will Change Chip Design

Stacking dies will dramatically improve performance, but it's still a work in progress.
Published on October 8th, 2025 byEd Sperling

How To Cool 3D-ICs

Tool chains need improvement as chipmakers begin stacking AI chips, increasing the thermal density and unpredictability over time.
Published on October 1st, 2025 byEd Sperling

More Roundtables »



Multimedia

Software-Defined Systems

Advantages and pitfalls for developing hardware using high-level software languages.
Published on January 26th, 2026 byEd Sperling

Challenges In Moving Data In Chips

How to ensure the right data arrives at a shared memory at the right time.
Published on January 14th, 2026 byEd Sperling

Changes In Mixed-Signal IC Verification

Why digital and analog engineers must now find common ground.
Published on November 19th, 2025 byEd Sperling

Multi-Die Verification

How to keep everything synchronized in a chiplet-based design.
Published on October 13th, 2025 byEd Sperling

Benefits And Challenges Of Using Chiplets

Coherent vs. non-coherent interfaces, heterogeneous vs. homogeneous, and other considerations with chiplets.
Published on September 24th, 2025 byEd Sperling

More Multimedia »



See All Posts in System-Level Design »See All Posts in IoT, Security & Automotive »See All Posts in Test, Measurement & Analytics »See All Posts in Manufacturing, Packaging & Materials »

Latest Blogs

Making Formal Normal

Formal Verification First: How AI Supports But Cannot Rep...

In verification, speed without provable correctness is not progress.
February 13, 2026
NoC NoC

Solving Real-World AI Bottlenecks

Tightly coordinated data movement and low-latency on-chip storage for real-ti...
February 2, 2026
First By Design

How The EDA Industry Will Evolve In 2026

The factors reshaping how teams work and the tools they use.
January 29, 2026
A System Perspective

Opening The Door To STCO: Hierarchical Device Planning

Decompose overwhelming design challenges into digestible, manageable segments.
January 29, 2026
Looking Past The Horizon

Building Trust At The Silicon Level: Secure Storage Solut...

A layered defense model ensures data remains protected even if physical acces...
January 29, 2026
Intelligent System Design

Heterogeneous Multicore System IP

Reduce energy and area costs while meeting performance requirements across va...
January 29, 2026
AI Agents In Design And Verification

Autonomous ASIC Root Cause Analysis

An agentic AI-based approach to end-to-end bug resolution using both error lo...
December 23, 2025
Clock Talk

Setting Vmin With Transistor-Level PDN Telemetry

The voltage set at the regulator is rarely what the transistors actually see.
December 23, 2025
The Next Thread

Shaping The Future Of AI Processors: A Tech Threads Conve...

Modern AI systems require dynamic, adaptable software layers built to handle ...
November 25, 2025

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Can A Computer Science Student Be Taught To Design Hardware?

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