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Low Power-High Performance

Top Stories

Chiplets And 3D-ICs Add New Electrical And Mechanical Cha...

Reliability is now a system-level concern that includes everything from materials and packaging to testing with backside power.
Published on February 12th, 2026 byAnn Mutschler

UCIe’s Major Technical Components Are Now In Place

Version 3.0 of the interconnect standard doubles bandwidth and supports new use cases and enhanced manageability.
Published on February 12th, 2026 byBryon Moyer

Minimum Energy Per Query

How much of the energy consumed in an AI chip is spent doing something useful? This question affects everything from software to system architectur...
Published on February 12th, 2026 byBrian Bailey

Balancing Training, Quantization, And Hardware Integratio...

Evolving challenges and strategies in AI/ML model deployment and hardware optimization have a big impact on NPU architectures.
Published on January 26th, 2026 byAnn Mutschler

Addressing Critical Tradeoffs In NPU Design

Flexibility, future-proofing, and performance considerations for neural processing units.
Published on January 21st, 2026 byAnn Mutschler

How And Why To Optimize NPUs

PPA constraints need to be paired with real workloads, but they also need to be flexible to account for future changes.
Published on January 15th, 2026 byAnn Mutschler

Liquid Cooling Gains Traction In Data Centers

There are numerous ways to remove heat from chips, and more are on the way.
Published on January 15th, 2026 byBryon Moyer

Will 2026 Be Dominated By AI?

Artificial intelligence has become central to almost all advances happening within semiconductors and EDA, but will that continue throughout the year?
Published on January 15th, 2026 byBrian Bailey

Limited by Power

Access to power is changing the industry's view about energy efficiency, which impacts all levels of the system stack and abstractions.
Published on December 11th, 2025 byBrian Bailey

AI Buildout Makes HPC Simulation More Challenging

Complexity mounts, driven by multiple dies, larger and more complex systems, and the incessant demand for performance improvements everywhere.
Published on December 11th, 2025 byAnn Mutschler

More Top Stories »



Round Tables

Balancing Training, Quantization, And Hardware Integratio...

Evolving challenges and strategies in AI/ML model deployment and hardware optimization have a big impact on NPU architectures.
Published on January 26th, 2026 byAnn Mutschler

Addressing Critical Tradeoffs In NPU Design

Flexibility, future-proofing, and performance considerations for neural processing units.
Published on January 21st, 2026 byAnn Mutschler

How And Why To Optimize NPUs

PPA constraints need to be paired with real workloads, but they also need to be flexible to account for future changes.
Published on January 15th, 2026 byAnn Mutschler

Chiplet Ecosystem Slowly Emerges

Before the transition can be made from custom chiplet environments to a standardized off-the-shelf open marketplace, an ecosystem must be created.
Published on July 23rd, 2025 byBrian Bailey

When Can I Buy A Chiplet?

A chiplet ecosystem is under development, but many barriers must be overcome before a thriving marketplace can exist.
Published on July 17th, 2025 byBrian Bailey

More Roundtables »



Multimedia

Changes In Chip Architectures At The Edge

How to build an efficient and flexible multi-die system for edge AI.
Published on February 4th, 2026 byEd Sperling

LPDDR6: Not Just For Mobile Anymore

Why and how the go-to-DRAM for low-power devices is pushing beyond its roots.
Published on November 3rd, 2025 byEd Sperling

Critical Factors For Storing Data In DRAM

New concerns and challenges for memory in AI data centers.
Published on October 27th, 2025 byEd Sperling

The Rise Of AI Co-Processors

Keeping AI hardware current and relevant is becoming a challenge.
Published on September 29th, 2025 byEd Sperling

The Evolution of DRAM

How and why this tried-and-true memory is changing.
Published on September 8th, 2025 byEd Sperling

More Multimedia »



See All Posts in Low Power-High Performance »See All Posts in IoT, Security & Automotive »See All Posts in Test, Measurement & Analytics »See All Posts in Manufacturing, Packaging & Materials »

Latest Blogs

Embedded ML Design

The On-Device LLM Revolution

Why 3B to 30B models are moving to the edge — and what that means for silicon.
February 20, 2026
A Bit About Memory

AI Inference Needs A Mix-And-Match Memory Strategy

Matching memory technology to the inference workload phase is necessary to ac...
February 12, 2026
Best Of Both: LP & HP

Formal Verification Fundamentals Remain Non-Negotiable In...

Managing complexity without compromising mathematical rigor.
February 12, 2026
Everything Low Power

AI, GPU, And HPC Data Centers: The Infrastructure Behind ...

As rack densities rise and cooling architectures diversify, design mistakes b...
February 12, 2026
IP And LP In SoCs

Power Leadership At 2nm: Foundation IP Optimized For Next...

Innovation spanning process, design, and architecture can unlock new levels o...
February 12, 2026
At The Core

Scaling llama.cpp On Neoverse N2: Solving Cross-NUMA Perf...

NUMA-aware optimizations can deliver up to 55% faster text generation.
February 12, 2026
MIPI And Beyond

Exploring The Latest Innovations In MIPI D-PHY And MIPI C...

Enhanced performance and flexibility for the next generation of high-speed ...
January 15, 2026
Inside Edge AI Processing

Next Generation AI: Transitioning Inference From The Clou...

High utilization, low memory movement, and broad model compatibility can coex...
December 11, 2025

Knowledge Centers
Entities, people and technologies explored


  Trending Articles

AI’s Impact On Engineering Jobs May Be Different Than Expected

Workflows and the addition of new capabilities are happening much faster than with previous technologies, and new grads may be vital in that transition.

Can A Computer Science Student Be Taught To Design Hardware?

To fill the talent gap, CS majors could be taught to design hardware, and the EE curriculum could be adapted or even shortened.

Chiplet Fundamentals For Engineers: eBook

A 65-page in-depth research report on the next phase of device scaling.

Securing Hardware For The Quantum Era

Quantum computers may become a security threat as early as next year, and that threat will continue to grow over the next several years.

Balancing Training, Quantization, And Hardware Integration In NPUs

Evolving challenges and strategies in AI/ML model deployment and hardware optimization have a big impact on NPU architectures.

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