Ann Mutschler

(all posts)
Ann Mutschler is senior executive editor at Semiconductor Engineering.

Author's Latest Posts

Chiplets And 3D-ICs Add New Electrical And Mechanical Challenges

ByAnn Mutschler - 12 Feb, 2026 - Comments: 1

Key Takeaways• Chiplets and 3D-IC architectures add new thermal-mechanical stresses that can affect the reliability of entire systems.• As chiplets are assembled into packages, defectivity targets become more stringent for each component in a system.• Traditional silos are breaking down, forcing design teams to address issues such as materials choices that previously were handled by...» read more

Securing Hardware For The Quantum Era

ByAnn Mutschler - 05 Feb, 2026 - Comments: 0

Key Takeaways: Quantum threats to security are already real. Adversaries are already harvesting data that will be decrypted later by quantum computers. Quantum computers capable of breaking RSA and ECC may arrive as early as next year. Asymmetric encryption algorithms like RSA and ECC will become inadequate against quantum threats, while symmetric encryption (such as AES) is less vul...» read more

Multi-Die Assemblies Require More Detailed Test Plan Earlier

ByAnn Mutschler - 29 Jan, 2026 - Comments: 0

Key Takeaways Design for test takes on new urgency in complex multi-die assemblies, where it can be used to minimize downstream errors and the cost of fixing them. DFT needs to be increasingly detailed due to more connections and the inability to access some components. DFT strategies need to be developed earlier and may require multiple testing approaches.Multi-die assembl...» read more

Balancing Training, Quantization, And Hardware Integration In NPUs

ByAnn Mutschler - 26 Jan, 2026 - Comments: 0

Experts At The Table: AI/ML is driving a steep ramp in neural processing unit (NPU) design activity for everything from data centers to edge devices such as PCs and smartphones. Semiconductor Engineering sat down to discuss this with Jason Lawley, director of product marketing, AI IP at Cadence; Sharad Chole, chief scientist and co-founder at Expedera; Steve Roddy, chief marketing officer at Qu...» read more

Addressing Critical Tradeoffs In NPU Design

ByAnn Mutschler - 21 Jan, 2026 - Comments: 1

Experts At The Table: AI/ML are driving a steep ramp in neural processing unit (NPU) design activity for everything from data centers to edge devices such as PCs and smartphones. Semiconductor Engineering sat down with Jason Lawley, director of product marketing, AI IP at Cadence; Sharad Chole, chief scientist and co-founder at Expedera; Steve Roddy, chief marketing officer at Quadric; Steven W...» read more

How And Why To Optimize NPUs

ByAnn Mutschler - 15 Jan, 2026 - Comments: 0

Automotive Outlook: 2026

ByAnn Mutschler - 08 Jan, 2026 - Comments: 0

The automotive industry stands at a crossroads entering 2026, facing a complex interplay of global tariffs, evolving electric vehicle (EV) dynamics, and the infusion of AI into just about everything.As manufacturers and suppliers navigate recent financing shifts and regulatory changes, they also must address consumer concerns over EV affordability and range, OEM concerns over when to develo...» read more

When To Move To Multi-Die Assemblies

ByAnn Mutschler - 23 Dec, 2025 - Comments: 0

As chip designs become larger and more complex, especially for AI and high-performance computing workloads, it's often not feasible to fit everything onto a single planar die. But determining when to move to a multi-die assembly isn't always straightforward.Multi-die approaches have some well-documented benefits. They allow designers to split functions across different dies, which can impro...» read more

AI Workloads at the Edge: Ensuring Performance, Privacy, and Security

ByAnn Mutschler - 17 Dec, 2025 - Comments: 0

Experts At The Table: Semiconductor Engineering gathered a group of experts to discuss why some AI workloads are better suited for on-device processing to achieve consistent performance, avoid network connectivity issues, reduce cloud computing costs, and ensure privacy. The panel included Frank Ferro, group director in the Silicon Solutions Group at Cadence; Eduardo Montanez, vice president a...» read more

AI Buildout Makes HPC Simulation More Challenging

ByAnn Mutschler - 11 Dec, 2025 - Comments: 0

Simulations of semiconductors and systems are becoming bigger, more complex, and increasingly necessary, mirroring everything that is happening to the hardware itself — particularly in AI data centers.The move beyond monolithic chips to multi-die assemblies now requires solving some thorny multi-physics challenges, such as thermal and power delivery, which are increasingly difficult to mo...» read more

← Older posts

Sponsors

Newsletter Signup

Recent Comments

Robert Boissy onCan A Computer Science Student Be Taught To Design Hardware?
Hank Walker onCan A Computer Science Student Be Taught To Design Hardware?
fieke khan onBump Co-Planarity And Inconsistencies Cause Yield, Reliability Issues
Rajiv onChip Industry Week in Review
Guy van der Walt - Thermco onChiplets And 3D-ICs Add New Electrical And Mechanical Challenges
Stephen W onChiplet Fundamentals For Engineers: eBook
ShrdMem256 onThe Verification Conundrum
Brendan McGuire onWafer Probe Struggles To Adapt To Multi-Die Assemblies
NobodyTestedThis onThe Verification Conundrum
Fiber Techs San Francisco onAgentic AI In Chip Manufacturing
SF Fiber Techs onOxides Bring Low Leakage Transistors To Leading-Edge Memories
humic onAddressing Critical Tradeoffs In NPU Design
Dr. Dev Gupta onLiquid Cooling Gains Traction In Data Centers
Mikko Utriainen, Chipmetrics onMetrology Digs Deep To Produce Next-Generation 3D NAND
Raymond Doerr onWafer Bonding Mechanisms Using SiCN Films For Hybrid Bonding Applications In 3D Integration
Hoyong Lee onChiplets Vs. Soft IP: Different In Almost Every Way
Nano Banana AI onBlog Review: Dec. 17
JS Paek onThermal Management In 3D-IC: Modeling Hotspots, Materials, & Cooling Strategies
Larry K onChiplets Vs. Soft IP: Different In Almost Every Way
Seceon.Inc onResilient And Optimized GenAI Systems
Linda Christensen onAI With Open And Scaled Data Sharing in IC Manufacturing (NIST)
komputer onAI With Open And Scaled Data Sharing in IC Manufacturing (NIST)
Sree onThe Thermal Trap: How Dielectrics Limit Device Performance
David Muncier onChina GenAI: Who Will Fill The Vacuum?
acp onIs There Still a Future for Hard Disk Drives?
Carlos Borer onLegacy Process Nodes Going Strong
Raj Sodhi onAI Meets Device Modeling: Transforming Compact Modeling With Machine Learning
Jaynarayan Tudu onSemiconductor Test Faces Technology Shifts In The AI Era
Mihai Buta onWhy In-Memory Computation Is So Important For Edge AI
Silver Luis onThe Competitive Advantage Of SRAM PUF Technology
Gretchen Patti onAdvanced Packaging: A Key Technology For The Next Generation Of Electronics
Ev roach onAI Bubble Or Boom?
Kathleen Murphy-Weber onChip Industry Week in Review
Raz onMulti-Die Verification
Paul C onScaling Memory With Molybdenum
JWS onScaling Memory With Molybdenum
Klein miller onElectrifying Everything: Power Moves Toward ICs
Team at Rise Design Automation onWhat Does Semiconductor Disruption Look Like?
masa mizuno onPhysics Limits Interposer Line Lengths
Lou Covey onWhat Does Semiconductor Disruption Look Like?
Ricardo Shiroma onComplex Mix Of Processors At The Edge
Cor onGlass Substrates Gain Momentum
Daya Young onNew Antennas And Advanced ICs Needed For 6G
Subramanian Srikanteswara Iyer onManufacturing At The Limits
Doug La Tulipe onColoring Optical Signals For More Bandwidth In Data Centers
WH onThe Hidden Cost Of Contact Resistance
Raymond Doerr onMetrology Under Pressure: Detecting Defects in Fine-Pitch Hybrid Bonding
Raymond Doerr onManufacturing At The Limits
Mallikarjun onThe Evolution of DRAM
Klein Miller onDemocratizing Design: How The CHIPS Act Is Reshaping EDA And Semiconductor Innovation
Klein Miller onLessons From 30 Years In The Trenches On The Future Of Semiconductor Manufacturing
Jonathan Kolber onPreparing For The Quantum Computing Age
Pramod Gupta onChallenges In Stacking HBM
Madeline Lueilwitz onReconfigurable Single-Walled CNT FeFET (Univ. of Pennsylvania, Yonsei et al.)
Anne Meixner onNeed For KGD Drives Singulated Die Screening
Capt kirk onDesigning A Better Clock Network
Alex Martin onAI Effort And Money Misplaced
Hamilton Carter onAI Effort And Money Misplaced
Ilmu Komunikasi onReconfigurable Single-Walled CNT FeFET (Univ. of Pennsylvania, Yonsei et al.)
Giovanni Lostumbo onWill New Processor Architectures Raise Energy Efficiency?
Brendon Berg onESD Guns, Transients And Testing…Oh My!
GD onAll About Interconnects
Raimo onCrisis Ahead: Power Consumption In AI Data Centers
Fred Chen onLaser-Focused Results: Improving EUV Line Edge Roughness With Ion Beam Etching
Fred Chen onMany Options For EUV Photoresists, No Clear Winner
Amba Prasad onAdvanced Packaging Fundamentals for Semiconductor Engineers: eBook
Shakir Ullah onThe Race To Replace Silicon
Hwaiyu Geng, P.E. onAccelerating Semiconductor Process Development Using Virtual Design Of Experiments
Larry Gus Christiansen onReducing Risk In The Semiconductor Supply Chain
Vikas Sharma onRTL Signoff vs. Functional Signoff: What’s The Difference?
Simone onCrisis Ahead: Power Consumption In AI Data Centers
Ron Lavallee onCan Today’s Processor Architectures Be More Efficient?
Rashid onCan Today’s Processor Architectures Be More Efficient?
Joseph Fjelstad onWhen Can I Buy A Chiplet?
Craig Lytle onCan Today’s Processor Architectures Be More Efficient?
Partha Thirumalai onCognichip: Using AI To Speed Complex Chip Design
Gopal raju onAdvanced Packaging Fundamentals for Semiconductor Engineers: eBook
Lawrence Kushner onDemocratizing Design: How The CHIPS Act Is Reshaping EDA And Semiconductor Innovation
Ken Rygler onDisruptive Changes Ahead For Photomasks?
Jan Hoppe onNeed For KGD Drives Singulated Die Screening
B.S. DeepakSubramanyan onHBM Roadmap: Next-Gen High-Bandwidth Memory Architectures (KAIST’s TERALAB)
Dr. Subhash L. Shinde , Booz Allen, Ex. Univ. of Notre Dame, Ex. Sandia National Labs., Ex. IBM. onThe Race To Glass Substrates
Traian MUNTEAN (Honorary Professor) onA Balanced Approach To Verification
Amba Prasad onHBM Roadmap: Next-Gen High-Bandwidth Memory Architectures (KAIST’s TERALAB)
sam onHBM Roadmap: Next-Gen High-Bandwidth Memory Architectures (KAIST’s TERALAB)
Lentz onAgentic AI In Chip Design
adam onRISC-V’s Increasing Influence
Jon Taylor onRISC-V’s Increasing Influence
Roi Mit onThe DAC Valuation
Janis Robin Schamberger onChip Industry Week in Review
Rashid Kukkady onNew Data Center Protocols Tackle AI
Peter Bennet onThe DAC Valuation
Dan Ganousis onOptimizing Data Movement
DFTguy onRevolutionizing Semiconductor Development With GPU-Enhanced Atomistic Modeling
1945x onLaser-Focused Results: Improving EUV Line Edge Roughness With Ion Beam Etching
Jason Kennerly onMany Options For EUV Photoresists, No Clear Winner
Marc Swinnen onDevelopment Flows For Chiplets
Warren Savage onDevelopment Flows For Chiplets
N. L. Kamaruzzaman onSecurity Risks Mount For Aerospace, Defense Applications
IT onThree-Way Race To 3D-ICs
Marzieh SalarRahimi onAdvanced Packaging Fundamentals for Semiconductor Engineers: eBook
Harry Foster onTape-Out Failures Are The Tip Of The Iceberg
Brian Bailey onTape-Out Failures Are The Tip Of The Iceberg
Purple music onTape-Out Failures Are The Tip Of The Iceberg
Messika onTape-Out Failures Are The Tip Of The Iceberg
Al onTape-Out Failures Are The Tip Of The Iceberg
Svetlana Morozova onGPU Analysis Identifying Performance Bottlenecks That Cause Throughput Plateaus In Large-Batch Inference
universitywafer onAdvancements In Silicon Device Technology And Design Driving New SLM Monitor Categories
Dr. Dev Gupta onPackaging With Fewer People And Better Results
Michael Current onAdvanced Packaging Fundamentals for Semiconductor Engineers: eBook
Jack G on3D-IC For The Masses
Marc Greenberg onImplementing AI Activation Functions
Dr. D. onBig Changes Ahead For Interposers And Substrates
Dante onGPU Or ASIC For LLM Scale-Up?
Gretchen Patti onWhat Exactly Are Chiplets And Heterogeneous Integration?
Rob McCance onThe Seven Pillars Of IC Package Physical Design
Lullaby onTimes Are Changing For EDA
RF onMany Options For EUV Photoresists, No Clear Winner
ETechBuy onExperimental Characterization Results and State-of-the-Art Device-Level Studies of DRAM Read Disturbance
Fred Chen onMany Options For EUV Photoresists, No Clear Winner

Marketplace T

Privacy Overview

This website uses cookies to improve your experience while you navigate through the website. The cookies that are categorized as necessary are stored on your browser as they are essential for the working of basic functionalities of the website. We also use third-party cookies that help us analyze and understand how you use this website. We do not sell any personal information.

By continuing to use our website, you consent to our Privacy Policy. If you access other websites using the links provided, please be aware they may have their own privacy policies, and we do not accept any responsibility or liability for these policies or for any personal data which may be collected through these sites. Please check these policies before you submit any personal information to these sites.

Necessary

Always Enabled

Necessary cookies are absolutely essential for the website to function properly. This category only includes cookies that ensures basic functionalities and security features of the website. These cookies do not store any personal information.

Non-necessary

Any cookies that may not be particularly necessary for the website to function and is used specifically to collect user personal data via analytics, ads, other embedded contents are termed as non-necessary cookies. It is mandatory to procure user consent prior to running these cookies on your website.

SAVE & ACCEPT

Movatterモバイル変換