Changes to the LLVM IR¶

• …

• Added thebyref attribute to better represent argument passingfor theamdgpu_kernel calling convention.

• Added type parameter to thesret attribute to continue work onremoving pointer element types.

• Thellvm.experimental.vector.reduce family of intrinsics have been renamedto drop the “experimental” from the name, reflecting their now fully supportedstatus in the IR.

Changes to building LLVM¶

• The internalllvm-build Python script and the associatedLLVMBuild.txtfiles used to describe the LLVM component structure have been removed andreplaced by a pureCMake approach, where each component stores extraproperties in the created targets. These properties are processed once allcomponents are defined to resolve library dependencies and produce the headerexpected by llvm-config.

Changes to TableGen¶

• The new “TableGen Programmer’s Reference” replaces the “TableGen LanguageIntroduction” and “TableGen Language Reference” documents.

• The syntax for specifying an integer range in a range list has changed.The old syntax used a hyphen in the range (e.g.,{0-9}). The new syntaxuses the “…” range punctuation (e.g.,{0...9}). The hyphen syntaxis deprecated.

Changes to the AArch64 Backend¶

During this release …

• Lots of improvements to generation of Windows unwind data; the unwinddata is optimized and written in packed form where possible, reducingthe size of unwind data (pdata and xdata sections) by around 60%compared with LLVM 11. The generation of prologs/epilogs is tweakedwhen targeting Windows, to increase the chances of being able to usethe packed unwind info format.

• Support for creating Windows unwind data using.seh_* assemblerdirectives.

• Produce proper assembly output for the Windows target, including:lo12: relocation specifiers, to allow the assembly outputto actually be assembled.

• Changed the assembly comment string for MSVC targets to// (consistentwith the MinGW and ELF targets), freeing up; to be used asstatement separator.

Changes to the ARM Backend¶

During this release …

Changes to the MIPS Target¶

During this release …

Changes to the PowerPC Target¶

Optimization:

• Made improvements to loop unroll-and-jam including fix to respect userprovided #pragma unroll-and-jam for loops on targets other than ARM.

• Improved PartialInliner allowing it to handle code regions in a switchstatements.

• Improved PGO support on AIX by building and linking with compiler-rt profilelibrary.

• Add support for Epilogue Vectorization and enabled it by default.

CodeGen:

• POWER10 support* Implementation of PC Relative addressing in LLD including the associated

  linker optimizations.

  • Add support for the new matrix multiplication (MMA) instructions to Clangand LLVM.

  • Implementation of Power10 builtins.

• Scheduling enhancements* Add a new algorithm to cluster more loads/stores if the DAG is not too

  complicated.

  • Enable the PowerPC scheduling heuristic for Power10.

• Target dependent passes tuning* Enhance LoopStrengthReduce/PPCLoopInstrFormPrep pass for PowerPC,

  especially for P10 intrinsics.

  • Enhance machine combiner pass to reduce register pressure for PowerPC.

  • Improve MachineSink to do more sinking based on register pressure and aliasanalysis.

• General improvements* Complete the constrained floating point operations support.* Improve the llvm-exegesis support.* Improve the stack clash protection to probe the gap between stackptr and

  realigned stackptr.

  • Improve the IEEE long double support for Power8.

  • Enable MemorySSA for LoopSink.

  • Enhance LLVM debugging functionality via options such as -print-changed and-print-before-changed.

  • Add builtins for Power9 (i.e. darn, xvtdiv, xvtsqrt etc).

  • Add options to disable all or part of LoopIdiomRecognizePass.

  • Add support for printing the DDG in DOT form allowing for visual inspectionof the Data Dependence Graph.

  • Remove the QPX support.

  • Significant number of bug fixes including all the fixes necessary toachieve a clean test run for Julia.

AIX Support:

• Compiler-rt support* Add support for building compiler-rt for AIX and 32-bit Power targets.* Made compiler-rt the default rtlib for AIX.

• General Improvements* Enable the AIX extended AltiVec ABI under option -mabi=vec-extabi.* Add partial C99 complex type support.* Implemente traceback table for functions (encodes vector information,

  emits exception handling).

  • Implemente code generation for C++ dynamic initialization and finalization.of non-local variables for use with the -bcdtors option of the AIX linker.

  • Add new option -mignore-xcoff-visibility.

  • Enable explicit sections on AIX.

  • Enable -f[no-]data-sections on AIX and set -fdata-sections to be the defaulton AIX.

  • Enable -f[no-]function-sections.

  • Add support for relocation generation using the large code model.

  • Add pragma align natural and sorted out pragma pack stack effect.

Changes to the X86 Target¶

During this release …

• The ‘mpx’ feature was removed from the backend. It had been removed from clangfrontend in 10.0. Mention of the ‘mpx’ feature in an IR file will print amessage to stderr, but IR should still compile.

• Support for-march=alderlake,-march=sapphirerapids,-march=znver3 and-march=x86-64-v[234] has been added.

• The assembler now has support for {disp32} and {disp8} pseudo prefixes forcontrolling displacement size for memory operands and jump displacements. Theassembler also supports the .d32 and .d8 mnemonic suffixes to do the same.

• A new function attribute “tune-cpu” has been added to support -mtune like gcc.This allows microarchitectural optimizations to be applied independent fromthe “target-cpu” attribute or TargetMachine CPU which will be used to selectInstruction Set. If the attribute is not present, the tune CPU will followthe target CPU.

• Support forHRESET instructions has been added.

• Support forUINTR instructions has been added.

• Support forAVXVNNI instructions has been added.

Changes to the AMDGPU Target¶

During this release …

• The newbyref attribute is now the preferred method forrepresenting aggregate kernel arguments.

Changes to the AVR Target¶

During this release …

Changes to the WebAssembly Target¶

During this release …

Changes to the OCaml bindings¶

Changes to the C API¶

Changes to the Go bindings¶

Changes to the DAG infrastructure¶

Changes to the Debug Info¶

During this release …

• The DIModule metadata is extended with a field to indicate if it is amodule declaration. This extension enables the emission of debug infofor a Fortran ‘use <external module>’ statement. For more informationon what the debug info entries should look like and how the debuggercan use them, please see test/DebugInfo/X86/dimodule-external-fortran.ll.

Changes to the LLVM tools¶

• llvm-readobj and llvm-readelf behavior has changed to report an error whenexecuted with no input files instead of reading an input from stdin.Reading from stdin can still be achieved by specifying- as an input file.

• llvm-mca supports serialization of the timeline and summary views.The–json command line option prints a JSON representation ofthese views to stdout.

Changes to LLDB¶

Changes to Sanitizers¶

The integer sanitizer-fsanitize=integer now has a new sanitizer:-fsanitize=unsigned-shift-base. It’s not undefined behavior for an unsignedleft shift to overflow (i.e. to shift bits out), but it has been the source ofbugs and exploits in certain codebases in the past.

Many Sanitizers (asan, cfi, lsan, msan, tsan, ubsan) have support formusl-based Linux distributions. Some of them may be rudimentary.