Kollipara et al., 2009
| Publication | Publication Date | Title |
|---|---|---|
| US10884955B2 (en) | Stacked and folded above motherboard interposer | |
| Zerbe et al. | 1.6 Gb/s/pin 4-PAM signaling and circuits for a multidrop bus | |
| EP3058468B1 (en) | Receiver architecture for memory reads | |
| JP3539898B2 (en) | Package routing method for integrated circuit signals | |
| US6449166B1 (en) | High capacity memory module with higher density and improved manufacturability | |
| Shin et al. | Signal integrity design and analysis of Universal Chiplet Interconnect Express (UCIe) channel in silicon interposer for advanced package | |
| US11756905B2 (en) | Package interface with improved impedance continuity | |
| Beyene et al. | Advanced modeling and accurate characterization of a 16 Gb/s memory interface | |
| Kollipara et al. | Evaluation of a module based memory system with an LCP flex interconnect | |
| Lee et al. | High speed differential I/O overview and design challenges on Intel enterprise server platforms | |
| US11955436B2 (en) | Self-equalized and self-crosstalk-compensated 3D transmission line architecture with array of periodic bumps for high-speed single-ended signal transmission | |
| Kollipara et al. | Design and testing of a high speed module based memory system | |
| Beyene et al. | Signal and power integrity analysis of a 256-GB/s double-sided IC package with a memory controller and 3D stacked DRAM | |
| Sharawi et al. | The design and simulation of a 400/533Mbps DDR-II SDRAM memory interconnect bus | |
| Kollipara et al. | Evaluation of high density liquid crystal polymer based flex interconnect for supporting greater than 1 TB/s of memory bandwidth | |
| Beyene et al. | Design and analysis of a TB/sec memory system | |
| Kim et al. | Signal integrity design and analysis of a multilayer test interposer for LPDDR4 memory test with silicone rubber-based sheet contact | |
| Beyene et al. | System performance comparisons of coreless and standard packages for data rate beyond 20 Gbps | |
| Yuan et al. | Design and modeling of a 3.2 Gbps/pair memory channel | |
| Beyene et al. | Design and analysis of 12.8 Gb/s single-ended signaling for memory interface | |
| Na et al. | ASIC packaging challenges with high speed interfaces | |
| Chandrasekhar et al. | Impact of Die Pin Capacitance and Package Crosstalk on DDR4 Channel Jitter | |
| Soman et al. | High speed DDR interface timing closure |