Movatterモバイル変換


[0]ホーム

URL:


Cherry, 1988 - Google Patents

Pearl: A CMOS timing analyzer

Cherry, 1988

ViewPDF
Document ID
6400097416385611026
Author
Cherry J
Publication year
Publication venue
Proceedings of the 25th ACM/IEEE Design Automation Conference

External Links

Snippet

Pearl is a timing analyxer that has been used to verify both full custom VLSI and gate array designs. Bather than verify that a design meets a given clock-wg, Pearl automatically determines the minimum error free clock period and duty cycles. Delay equations compiled …
Continue reading atwww.researchgate.net (PDF) (other versions)

Classifications

The classifications are assigned by a computer and are not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the classifications listed.
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • G06F17/5022Logic simulation, e.g. for logic circuit operation
    • G06F17/5031Timing analysis
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • G06F17/5036Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5068Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5081Layout analysis, e.g. layout verification, design rule check
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • G06F17/504Formal methods
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5045Circuit design
    • G06F17/505Logic synthesis, e.g. technology mapping, optimisation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5045Circuit design
    • G06F17/5054Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5068Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5077Routing
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/30Information retrieval; Database structures therefor; File system structures therefor
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/70Fault tolerant, i.e. transient fault suppression
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G06F1/04Generating or distributing clock signals or signals derived directly therefrom
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/78Power analysis and optimization
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses

Similar Documents

PublicationPublication DateTitle
CherryPearl: A CMOS timing analyzer
US7162706B2 (en)Method for analyzing and validating clock integration properties in circuit systems
US7650583B2 (en)Method for determining maximum operating frequency of a filtered circuit
Chawla et al.MOTIS-An MOS timing simulator
Ruehli et al.Circuit analysis, logic simulation, and design verification for VLSI
US5392227A (en)System and method for generating electronic circuit simulation models having improved accuracy
Shepard et al.Harmony: Static noise analysis of deep submicron digital integrated circuits
US20050066298A1 (en)System and method for probabilistic criticality prediction of digital circuits
US6480816B1 (en)Circuit simulation using dynamic partitioning and on-demand evaluation
US5978571A (en)Method and apparatus for synchronous circuit simulation design by eliminating unneeded timing behaviors prior to simulation run-time
Chakraborty et al.Min-max timing analysis and an application to asynchronous circuits
NewtonTiming, logic and mixed-mode simulation for large MOS integrated circuits
US6560571B1 (en)Method and apparatus for prioritizing the order in which checks are performed on a node in an integrated circuit
US6654936B2 (en)Method and apparatus for determining the strengths and weaknesses of paths in an integrated circuit
Rao et al.Network partitioning and ordering for MOS VLSI circuits
Wallace et al.Plug-in timing models for an abstract timing verifier
US6321365B1 (en)System and method for detecting storage nodes that are susceptible to charge sharing
US6718522B1 (en)Electrical rules checker system and method using tri-state logic for electrical rule checks
Abednazari et al.BAS: A BTI-based aging aware synthesis in FPGAs
US6367062B1 (en)System and method for detecting an excessive number of series-connected pass FETs
GolshanDesign Verification
US6701290B1 (en)Method and apparatus for evaluating the design quality of network nodes
Kuentzer et al.Addressing Single-Event-Multiple-Transient Faults in Asynchronous RH-Click Controllers
JohannesDelay characterization and hierarchical timing verification for synchronous circuits
Yuan et al.Static power analysis for power-driven synthesis

[8]
ページ先頭

©2009-2025 Movatter.jp