Cherry, 1988
ViewPDF| Publication | Publication Date | Title |
|---|---|---|
| Cherry | Pearl: A CMOS timing analyzer | |
| US7162706B2 (en) | Method for analyzing and validating clock integration properties in circuit systems | |
| US7650583B2 (en) | Method for determining maximum operating frequency of a filtered circuit | |
| Chawla et al. | MOTIS-An MOS timing simulator | |
| Ruehli et al. | Circuit analysis, logic simulation, and design verification for VLSI | |
| US5392227A (en) | System and method for generating electronic circuit simulation models having improved accuracy | |
| Shepard et al. | Harmony: Static noise analysis of deep submicron digital integrated circuits | |
| US20050066298A1 (en) | System and method for probabilistic criticality prediction of digital circuits | |
| US6480816B1 (en) | Circuit simulation using dynamic partitioning and on-demand evaluation | |
| US5978571A (en) | Method and apparatus for synchronous circuit simulation design by eliminating unneeded timing behaviors prior to simulation run-time | |
| Chakraborty et al. | Min-max timing analysis and an application to asynchronous circuits | |
| Newton | Timing, logic and mixed-mode simulation for large MOS integrated circuits | |
| US6560571B1 (en) | Method and apparatus for prioritizing the order in which checks are performed on a node in an integrated circuit | |
| US6654936B2 (en) | Method and apparatus for determining the strengths and weaknesses of paths in an integrated circuit | |
| Rao et al. | Network partitioning and ordering for MOS VLSI circuits | |
| Wallace et al. | Plug-in timing models for an abstract timing verifier | |
| US6321365B1 (en) | System and method for detecting storage nodes that are susceptible to charge sharing | |
| US6718522B1 (en) | Electrical rules checker system and method using tri-state logic for electrical rule checks | |
| Abednazari et al. | BAS: A BTI-based aging aware synthesis in FPGAs | |
| US6367062B1 (en) | System and method for detecting an excessive number of series-connected pass FETs | |
| Golshan | Design Verification | |
| US6701290B1 (en) | Method and apparatus for evaluating the design quality of network nodes | |
| Kuentzer et al. | Addressing Single-Event-Multiple-Transient Faults in Asynchronous RH-Click Controllers | |
| Johannes | Delay characterization and hierarchical timing verification for synchronous circuits | |
| Yuan et al. | Static power analysis for power-driven synthesis |