Liu, 2018
ViewPDF| Publication | Publication Date | Title |
|---|---|---|
| US6886065B2 (en) | Improving signal integrity in differential signal systems | |
| Mellitz et al. | Channel operating margin (COM): Evolution of channel specifications for 25 Gbps and beyond | |
| Liu | USB3. x Linear Redriver Signal Conditioning Theory and Practical Tuning Method | |
| DIMM | Technical Reference | |
| CN103970699A (en) | Method for debugging FPGA pre-emphasis equilibrium value | |
| Correia et al. | Performance comparison of different encoding schemes in backplane channel at 25Gbps+ | |
| Hong et al. | An accurate jitter estimation technique for efficient high speed I/O testing | |
| Marin et al. | 40 GHz PCB Interconnect Validation: Expectations vs. Reality. | |
| Kim et al. | Experimental investigation for enhancement of timing margin of single-ended parallel bus by optimizing phase response of signal modes | |
| Antonini et al. | Eye pattern evaluation in high-speed digital systems analysis by using MTL modeling | |
| Zhang et al. | Transmission Line Intra-pair Skew Analysis and Management on PCIe 6.0 | |
| Degerstrom et al. | Plated-Through-Hole Via Design Specifications for 112G Serial Links | |
| Chu et al. | An efficient stress pattern based on VMRQ-PRBS for DDR training | |
| Beyene et al. | Return loss characterization and analysis of high-speed serial interface | |
| Yao et al. | Simulation Method of 32Gbps Signal Transmission Considering Xtalk Impact Using Probability Density Function | |
| Pandey | Ensuring high signal quality in PCIe Gen3 channels | |
| SureshKumar et al. | Signal Integrity Measurement Issue Debugging for HDMI2. 1 CRLS Topology: A Case Study | |
| Majumder et al. | Reconstruction of a single square pulse originally having 40 ps width coming from a lossy and noisy channel in a point to point interconnect | |
| Moon et al. | Generalized ccICN (component contribution Integrated Crosstalk Noise) for PAM-N | |
| Kanaan | Optimization of Eye Diagram Based on Adaptive Decision Feedback Equalizer for High Speed Digital System | |
| Yoon et al. | Crosstalk Analysis in Add-In Card structure for High-Speed SerDes Channels with PCIe Gen6 | |
| Neves et al. | S-parameters: Signal integrity analysis in the blink of an eye | |
| Patel | Contributors and Supporters | |
| Healey et al. | Beta and Epsilon Point Update | |
| Bokhari | Signal integrity considerations for the PCB implementation of multi-gigabit SERDES links |