Kim et al., 2014
ViewPDF| Publication | Publication Date | Title |
|---|---|---|
| Kim et al. | Bounding memory interference delay in COTS-based multi-core systems | |
| Kim et al. | Bounding and reducing memory interference in COTS-based multi-core systems | |
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| Hassan et al. | Bounding dram interference in cots heterogeneous mpsocs for mixed criticality systems | |
| Usui et al. | DASH: Deadline-aware high-performance memory scheduler for heterogeneous systems with hardware accelerators | |
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| Ausavarungnirun et al. | Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems | |
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| Muralidhara et al. | Reducing memory interference in multicore systems via application-aware memory channel partitioning | |
| Wu et al. | Worst case analysis of DRAM latency in multi-requestor systems | |
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| Valsan et al. | MEDUSA: a predictable and high-performance DRAM controller for multicore based embedded systems | |
| Hassan et al. | Analysis of memory-contention in heterogeneous cots mpsocs | |
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| Guo et al. | A requests bundling DRAM controller for mixed-criticality systems | |
| Wu et al. | A composable worst case latency analysis for multi-rank dram devices under open row policy | |
| Modi et al. | CABARRE: Request response arbitration for shared cache management | |
| Mutlu et al. | Parallelism-aware batch scheduling: Enabling high-performance and fair shared memory controllers | |
| US20170192720A1 (en) | Prioritization of order ids in dram scheduling | |
| Ausavarungnirun | Techniques for shared resource management in systems with throughput processors | |
| Abdelhalim et al. | A tight holistic memory latency bound through coordinated management of memory resources | |
| Chung et al. | Enforcing last-level cache partitioning through memory virtual channels | |
| Song et al. | Single-tier virtual queuing: An efficacious memory controller architecture for MPSoCs with multiple realtime cores |