DIGITAL-TO-ANALOG CONVERTER (DAC) DIGITAL PREDISTORTION (DPD)
CROSS-REFERENCE TO RELATED APPLICATION(S)
[0001] This application claims priority to Israel Application No. 311517, filed March 17, 2024, which is hereby incorporated by reference herein.
TECHNICAL FIELD
[0002] Certain aspects of the present disclosure generally relate to electronic circuits and, more particularly, to techniques for digital predistortion for a digital-to-analog converter.
BACKGROUND
[0003] Wireless communication devices are widely deployed to provide various communication services such as telephony, video, data, messaging, broadcasts, and so on. Such wireless communication devices may transmit and/or receive radio frequency (RF) signals via any of various suitable radio access technologies (RATs) including, but not limited to, Fifth Generation (5G) New Radio (NR), Long Term Evolution (LTE), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Wideband CDMA (WCDMA), Global System for Mobility (GSM), Bluetooth, Bluetooth Low Energy (BLE), ZigBee, wireless local area network (WLAN) RATs (e.g., WiFi), and the like.
[0004] A wireless communication network may include a number of base stations that can support communication for a number of mobile stations. A mobile station (MS) may communicate with a base station (BS) via a downlink and an uplink. The downlink (or forward link) refers to the communication link from the base station to the mobile station, and the uplink (or reverse link) refers to the communication link from the mobile station to the base station. A base station may transmit data and control information on the downlink to a mobile station and/or may receive data and control information on the uplink from the mobile station. The base station and/or mobile station may include a digital-to-analog converter (DAC) for conversion of signals from the digital domain to the analog domain. SUMMARY
[0005] The systems, methods, and devices of the disclosure each have several aspects, no single one of which is solely responsible for its desirable attributes. Without limiting the scope of this disclosure as expressed by the claims which follow, some features will now be discussed briefly. After considering this discussion, and particularly after reading the section entitled “Detailed Description,” one will understand how the features of this disclosure provide advantages that include reduced area and power consumption.
[0006] Certain aspects of the present disclosure are directed towards an apparatus for wireless communication. The apparatus generally includes: a baseband processor; a first baseband path coupled to the baseband processor and including a first digital predistortion (DPD) circuit and a first digital-to-analog converter (DAC), an output of the first DPD circuit being coupled to an input of the first DAC; a second baseband path coupled to the baseband processor and including a second DPD circuit and a second DAC, an output of the second DPD circuit being coupled to an input of the second DAC; a first combiner with a first input coupled to the first baseband path and a second input coupled to the second baseband path; and an amplifier coupled to an output of the first combiner.
[0007] Certain aspects of the present disclosure are directed towards a method for wireless communication. The method generally includes: receiving, from a baseband processor, a first baseband signal at an input of a first DPD circuit of a first baseband path, the first baseband path including a first DAC with an input coupled to an output of the first DPD circuit; receiving, from the baseband processor, a second baseband signal at an input of a second DPD circuit of a second baseband path, the second baseband path including a second DAC with an input coupled to an output of the second DPD circuit; generating a first adjusted baseband signal and a second adjusted baseband signal via the first DPD circuit and the second DPD circuit based on the first baseband signal and the second baseband signal, respectively; generating a first analog signal via the first DAC and a second analog signal via the second DAC based on the first adjusted baseband signal and the second adjusted baseband signal, respectively; and generating a combined signal via a combiner based on the first analog signal and the second analog signal; and amplifying the combined signal to generate an amplified signal for transmission. [0008] Certain aspects of the present disclosure are directed towards an apparatus for wireless communication. The apparatus generally includes: a baseband processor; a baseband path coupled to the baseband processor and including a DPD circuit and a DAC, an output of the DPD circuit being coupled to an input of the DAC; a first DPD feedback path coupled between a node of the baseband path and the DPD circuit; an amplifier having an input coupled to the baseband path; and a second DPD feedback path coupled between an output of the amplifier and the baseband processor.
[0009] To the accomplishment of the foregoing and related ends, the one or more aspects comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative features of the one or more aspects. These features are indicative, however, of but a few of the various ways in which the principles of various aspects may be employed, and this description is intended to include all such aspects and their equivalents.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] So that the manner in which the above-recited features of the present disclosure can be understood in detail, a more particular description, briefly summarized above, may be had by reference to aspects, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only certain typical aspects of this disclosure and are therefore not to be considered limiting of its scope, for the description may admit to other equally effective aspects.
[0011] FIG. l is a diagram of an example wireless communications network, in which aspects of the present disclosure may be practiced.
[0012] FIG. 2 is a block diagram conceptually illustrating a design of an example base station (BS) and user equipment (UE), in which aspects of the present disclosure may be practiced.
[0013] FIG. 3 is a block diagram of an example radio frequency (RF) transceiver, in which aspects of the present disclosure may be practiced. [0014] FIG. 4 illustrates a transmitter including a digital-to-analog converter (DAC) digital predistortion (DPD) circuit, in accordance with certain aspects of the present disclosure.
[0015] FIG. 5 illustrates an example baseband path having a DAC DPD circuit and a feedback path for calibration, in accordance with certain aspects of the present disclosure.
[0016] FIG. 6 illustrates an example baseband path operated in mission mode, in accordance with certain aspects of the present disclosure.
[0017] FIG. 7 illustrates an example implementation of a high-pass filter (HPF) for a DAC DPD circuit, in accordance with certain aspects of the present disclosure.
[0018] FIG. 8 is a graph illustrating correction input signals provided to a lookup table (LUT) based on data input signals, in accordance with certain aspects of the present disclosure.
[0019] FIG. 9 is a graph illustrating multiple data input signals associated with the same correction input signal, in accordance with certain aspects of the present disclosure.
[0020] FIG. 10 is a graph illustrating baseband path response correction using interpolation, in accordance with certain aspects of the present disclosure.
[0021] FIG. 11 illustrates an example current-steering cell for a DAC, in accordance with certain aspects of the present disclosure.
[0022] FIG. 12 is a flow diagram illustrating example operations for wireless communication, in accordance with certain aspects of the present disclosure.
[0023] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one aspect may be beneficially utilized on other aspects without specific recitation.
DETAILED DESCRIPTION
[0024] The linearity of baseband circuits of in-phase and quadrature (I/Q) transmitters impacts the error vector magnitude (EVM), spectrum emission mask (SEM), and adjacent channel leakage ratio (ACLR), as well as harmonics of the modulating signal. The linearity specifications on baseband circuits may result in increased power consumption (e.g., reduced power efficiency) of circuits like digital-to-analog converters (DACs) due to the usage of higher voltage supply rails. Moreover, the baseband filter (BBF) may also use a higher voltage supply rail in order to increase the linearity of the BBF and a wider bandwidth with higher transconductance (gm) and supply currents. In addition, the high linearity specifications of the baseband hardware make it challenging to use powerefficient passive mixers in many cases. Stringent linearity specifications may also lead to usage of DAC segmentation and more thermometer bits, which typically increases the silicon area, as well as the usage of designs that facilitate accurate DAC unit element matching, which tends to increase the transceiver area. In certain aspects, to reduce/relax the linearity specifications of the baseband circuits from the DAC to the BBF, the nonlinearity of the transceiver in the baseband domain may be corrected (or at least reduced). For example, certain aspects may correct (or at least reduce) the nonlinearity of the baseband paths for in-phase (I) and quadrature (Q) paths separately via digital predistortion to enable the use of more nonlinear and closer-to-compression circuits in a DAC, a BBF, and a mixer.
[0025] Various aspects of the disclosure are described more fully hereinafter with reference to the accompanying drawings. This disclosure may, however, be embodied in many different forms and should not be construed as limited to any specific structure or function presented throughout this disclosure. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Based on the teachings herein one skilled in the art should appreciate that the scope of the disclosure is intended to cover any aspect of the disclosure disclosed herein, whether implemented independently of or combined with any other aspect of the disclosure. For example, an apparatus may be implemented or a method may be practiced using any number of the aspects set forth herein. In addition, the scope of the disclosure is intended to cover such an apparatus or method which is practiced using other structure, functionality, or structure and functionality in addition to or other than the various aspects of the disclosure set forth herein. It should be understood that any aspect of the disclosure disclosed herein may be embodied by one or more elements of a claim. [0026] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.
[0027] As used herein, the term “connected with” in the various tenses of the verb “connect” may mean that element A is directly connected to element B or that other elements may be connected between elements A and B (i.e., that element A is indirectly connected with element ). In the case of electrical components, the term “connected with” may also be used herein to mean that a wire, trace, or other electrically conductive material is used to electrically connect elements^ and B (and any components electrically connected therebetween).
An Example Wireless System
[0028] FIG. 1 illustrates an example wireless communications network 100, in which aspects of the present disclosure may be practiced. For example, the wireless communications network 100 may be a New Radio (NR) system (e.g., a Fifth Generation (5G) NR network), an Evolved Universal Terrestrial Radio Access (E-UTRA) system (e.g., a Fourth Generation (4G) network), a Universal Mobile Telecommunications System (UMTS) (e.g., a Second Generation/Third Generation (2G/3G) network), or a code division multiple access (CDMA) system (e.g., a 2G/3G network), or may be configured for communications according to an IEEE standard such as one or more of the 802.11 standards, etc.
[0029] As illustrated in FIG. 1, the wireless communications network 100 may include a number of base stations (BSs) 1 lOa-z (each also individually referred to herein as “BS 110” or collectively as “BSs 110”) and other network entities. A BS may also be referred to as an access point (AP), an evolved Node B (eNodeB or eNB), a next generation Node B (gNodeB or gNB), or some other terminology.
[0030] A BS 110 may provide communication coverage for a particular geographic area, sometimes referred to as a “cell,” which may be stationary or may move according to the location of a mobile BS. In some examples, the BSs 110 may be interconnected to one another and/or to one or more other BSs or network nodes (not shown) in wireless communications network 100 through various types of backhaul interfaces (e.g., a direct physical connection, a wireless connection, a virtual network, or the like) using any suitable transport network. In the example shown in FIG. 1, the BSs 110a, 110b, and 110c may be macro BSs for the macro cells 102a, 102b, and 102c, respectively. The BS 1 lOx may be a pico BS for a pico cell 102x. The BSs 1 lOy and 1 lOz may be femto BSs for the femto cells 102y and 102z, respectively. A BS may support one or multiple cells.
[0031] The BSs 110 communicate with one or more user equipments (UEs) 120a-y (each also individually referred to herein as “UE 120” or collectively as “UEs 120”) in the wireless communications network 100. A UE may be fixed or mobile and may also be referred to as a user terminal (UT), a mobile station (MS), an access terminal, a station (STA), a client, a wireless device, a mobile device, or some other terminology. A user terminal may be a wireless device, such as a cellular phone, a smartphone, a personal digital assistant (PDA), a handheld device, awearable device, a wireless modem, a laptop computer, a tablet, a personal computer, etc.
[0032] The BSs 110 are considered transmitting entities for the downlink and receiving entities for the uplink. The UEs 120 are considered transmitting entities for the uplink and receiving entities for the downlink. As used herein, a “transmitting entity” is an independently operated apparatus or device capable of transmitting data via a frequency channel, and a “receiving entity” is an independently operated apparatus or device capable of receiving data via a frequency channel. In the following description, the subscript “d ” denotes the downlink, the subscript “np” denotes the uplink. Nup UEs may be selected for simultaneous transmission on the uplink, Ndn UEs may be selected for simultaneous transmission on the downlink. Nup may or may not be equal to Ndn, and Nup and Ndn may be static values or can change for each scheduling interval. Beamsteering or some other spatial processing technique may be used at the BSs 110 and/or UEs 120.
[0033] The UEs 120 (e.g., 120x, 120y, etc.) may be dispersed throughout the wireless communications network 100, and each UE 120 may be stationary or mobile. The wireless communications network 100 may also include relay stations (e.g., relay station 1 lOr), also referred to as relays or the like, that receive a transmission of data and/or other information from an upstream station (e.g., a BS 110a or a UE 120r) and send a transmission of the data and/or other information to a downstream station (e.g., a UE 120 or a BS 110), or that relays transmissions between UEs 120, to facilitate communication between devices.
[0034] The BSs 110 may communicate with one or more UEs 120 at any given moment on the downlink and uplink. The downlink (i.e., forward link) is the communication link from the BSs 110 to the UEs 120, and the uplink (i.e., reverse link) is the communication link from the UEs 120 to the BSs 110. A UE 120 may also communicate peer-to-peer with another UE 120.
[0035] The wireless communications network 100 may use multiple transmit and multiple receive antennas for data transmission on the downlink and uplink. BSs 110 may be equipped with a number Nap of antennas to achieve transmit diversity for downlink transmissions and/or receive diversity for uplink transmissions. A set Nu of UEs 120 may receive downlink transmissions and transmit uplink transmissions. Each UE 120 may transmit user-specific data to and/or receive user-specific data from the BSs 110. In general, each UE 120 may be equipped with one or multiple antennas. The Nu UEs 120 can have the same or different numbers of antennas.
[0036] The wireless communications network 100 may be a time division duplex (TDD) system or a frequency division duplex (FDD) system. For a TDD system, the downlink and uplink share the same frequency band. For an FDD system, the downlink and uplink use different frequency bands. The wireless communications network 100 may also utilize a single carrier or multiple carriers for transmission. Each UE 120 may be equipped with a single antenna (e.g., to keep costs down) or multiple antennas (e.g., where the additional cost can be supported).
[0037] A network controller 130 (also sometimes referred to as a “system controller”) may be in communication with a set of BSs 110 and provide coordination and control for these BSs 110 (e.g., via a backhaul). In certain cases (e.g., in a 5G NR system), the network controller 130 may include a centralized unit (CU) and/or a distributed unit (DU). In certain aspects, the network controller 130 may be in communication with a core network 132 (e.g., a 5G Core Network (5GC)), which provides various network functions such as Access and Mobility Management, Session Management, User Plane Function, Policy Control Function, Authentication Server Function, Unified Data Management, Application Function, Network Exposure Function, Network Repository Function, Network Slice Selection Function, etc.
[0038] In certain aspects of the present disclosure, the BSs 110 and/or the UEs 120 may include a transmitter implemented with DAC DPD, as described in more detail herein.
[0039] FIG. 2 illustrates example components of BS 110a and UE 120a (e.g., from the wireless communications network 100 of FIG. 1), in which aspects of the present disclosure may be implemented.
[0040] On the downlink, at the BS 110a, a transmit processor 220 may receive data from a data source 212, control information from a controller/processor 240, and/or possibly other data (e.g., from a scheduler 244). The various types of data may be sent on different transport channels. For example, the control information may be designated for the physical broadcast channel (PBCH), physical control format indicator channel (PCFICH), physical hybrid automatic repeat request (HARQ) indicator channel (PHICH), physical downlink control channel (PDCCH), group common PDCCH (GC PDCCH), etc. The data may be designated for the physical downlink shared channel (PDSCH), etc. A medium access control (MAC)-control element (MAC-CE) is a MAC layer communication structure that may be used for control command exchange between wireless nodes. The MAC-CE may be carried in a shared channel such as a PDSCH, a physical uplink shared channel (PUSCH), or a physical sidelink shared channel (PSSCH).
[0041] The processor 220 may process (e.g., encode and symbol map) the data and control information to obtain data symbols and control symbols, respectively. The transmit processor 220 may also generate reference symbols, such as for the primary synchronization signal (PSS), secondary synchronization signal (SSS), PBCH demodulation reference signal (DMRS), and channel state information reference signal (CSI-RS).
[0042] A transmit (TX) multiple-input, multiple-output (MIMO) processor 230 may perform spatial processing (e.g., precoding) on the data symbols, the control symbols, and/or the reference symbols, if applicable, and may provide output symbol streams to the modulators (MODs) in transceivers 232a-232t. Each modulator in transceivers 232a- 232t may process a respective output symbol stream (e.g., for orthogonal frequency division multiplexing (OFDM), etc.) to obtain an output sample stream. Each of the transceivers 232a-232t may further process (e.g., convert to analog, amplify, filter, and upconvert) the output sample stream to obtain a downlink signal. Downlink signals from the transceivers 232a-232t may be transmitted via the antennas 234a-234t, respectively.
[0043] At the UE 120a, the antennas 252a-252r may receive the downlink signals from the BS 110a and may provide received signals to the transceivers 254a-254r, respectively. The transceivers 254a-254r may condition (e.g., filter, amplify, downconvert, and digitize) a respective received signal to obtain input samples. Each demodulator (DEMOD) in the transceivers 232a-232t may further process the input samples (e.g., for OFDM, etc.) to obtain received symbols. A MIMO detector 256 may obtain received symbols from all the demodulators in transceivers 254a-254r, perform MIMO detection on the received symbols if applicable, and provide detected symbols. A receive processor 258 may process (e.g., demodulate, deinterleave, and decode) the detected symbols, provide decoded data for the UE 120a to a data sink 260, and provide decoded control information to a controller/processor 280.
[0044] On the uplink, at UE 120a, a transmit processor 264 may receive and process data (e.g., for the physical uplink shared channel (PUSCH)) from a data source 262 and control information (e.g., for the physical uplink control channel (PUCCH)) from the controller/processor 280. The transmit processor 264 may also generate reference symbols for a reference signal (e.g., the sounding reference signal (SRS)). The symbols from the transmit processor 264 may be precoded by a TX MIMO processor 266 if applicable, further processed by the modulators (MODs) in transceivers 254a-254r (e.g., for single-carrier frequency division multiplexing (SC-FDM), etc.), and transmitted to the BS 110a. At the BS 110a, the uplink signals from the UE 120a may be received by the antennas 234, processed by the demodulators in transceivers 232a-232t, detected by a MIMO detector 236 if applicable, and further processed by a receive processor 238 to obtain decoded data and control information sent by the UE 120a. The receive processor 238 may provide the decoded data to a data sink 239 and the decoded control information to the controller/processor 240.
[0045] The memories 242 and 282 may store data and program codes for BS 110a and UE 120a, respectively. The memories 242 and 282 may also interface with the controllers/processors 240 and 280, respectively. A scheduler 244 may schedule UEs for data transmission on the downlink and/or uplink.
[0046] In certain aspects of the present disclosure, the transceivers 232 and/or the transceivers 254 may be implemented with DAC DPD, as described in more detail herein.
[0047] NR may utilize orthogonal frequency division multiplexing (OFDM) with a cyclic prefix (CP) on the uplink and downlink. NR may support half-duplex operation using time division duplexing (TDD). OFDM and single-carrier frequency division multiplexing (SC-FDM) partition the system bandwidth into multiple orthogonal subcarriers, which are also commonly referred to as tones, bins, etc. Each subcarrier may be modulated with data. Modulation symbols may be sent in the frequency domain with OFDM and in the time domain with SC-FDM. The spacing between adjacent subcarriers may be fixed, and the total number of subcarriers may be dependent on the system bandwidth. The system bandwidth may also be partitioned into subbands. For example, a subband may cover multiple resource blocks (RBs).
Example RF Transceiver
[0048] FIG. 3 is a block diagram of an example radio frequency (RF) transceiver circuit 300, in accordance with certain aspects of the present disclosure. The RF transceiver circuit 300 includes at least one transmit (TX) path 302 (also known as a “transmit chain”) for transmitting signals via one or more antennas 306 and at least one receive (RX) path 304 (also known as a “receive chain”) for receiving signals via the antennas 306. When the TX path 302 and the RX path 304 share an antenna 306, the paths may be connected with the antenna via an interface 308, which may include any of various suitable RF devices, such as a switch, a duplexer, a diplexer, a multiplexer, and the like.
[0049] Receiving in-phase (I) and/or quadrature (Q) baseband analog signals from a digital-to-analog converter (DAC) 310, the TX path 302 may include a baseband filter (BBF) 312, a mixer 314, a driver amplifier (DA) 316, and a power amplifier (PA) 318. The BBF 312, the mixer 314, the DA 316, and the PA 318 may be included in a radio frequency integrated circuit (RFIC). For certain aspects, the PA 318 may be external to the RFIC. In some aspects, a DAC DPD may be implemented to increase the linearity associated with the DAC 310, the BBF 312, and/or mixer 314, as described in more detail herein.
[0050] The BBF 312 filters the baseband signals received from the DAC 310, and the mixer 314 mixes the filtered baseband signals with a transmit local oscillator (LO) signal to convert the baseband signal of interest to a different frequency (e.g., upconvert from baseband to a radio frequency). This frequency-conversion process produces the sum and difference frequencies between the LO frequency and the frequencies of the baseband signal of interest. The sum and difference frequencies are referred to as the “beat frequencies.” The beat frequencies are typically in the RF range, such that the signals output by the mixer 314 are typically RF signals, which may be amplified by the DA 316 and/or by the PA 318 before transmission by the antenna(s) 306. While one mixer 314 is illustrated, several mixers may be used to upconvert the filtered baseband signals to one or more intermediate frequencies and to thereafter upconvert the intermediate frequency (IF) signals to a frequency for transmission.
[0051] The RX path 304 may include a low noise amplifier (LNA) 324, a mixer 326, and a baseband filter (BBF) 328. The LNA 324, the mixer 326, and the BBF 328 may be included in one or more RFICs, which may or may not be the same RFIC that includes the TX path components. RF signals received via the antenna(s) 306 may be amplified by the LNA 324, and the mixer 326 mixes the amplified RF signals with a receive local oscillator (LO) signal to convert the RF signal of interest to a different baseband frequency (e.g., downconvert). The baseband signals output by the mixer 326 may be filtered by the BBF 328 before being converted by an analog-to-digital converter (ADC) 330 to digital I and/or Q signals for digital signal processing.
[0052] Certain transceivers may employ frequency synthesizers with a variablefrequency oscillator (e.g., a voltage-controlled oscillator (VCO) or a digitally controlled oscillator (DCO)) to generate a stable, tunable LO with a particular tuning range. Thus, the transmit LO may be produced by a TX frequency synthesizer 320, which may be buffered or amplified by amplifier 322 before being mixed with the baseband signals in the mixer 314. Similarly, the receive LO may be produced by an RX frequency synthesizer 332, which may be buffered or amplified by amplifier 334 before being mixed with the RF signals in the mixer 326. For certain aspects, a single frequency synthesizer may be used for both the TX path 302 and the RX path 304. In certain aspects, the TX frequency synthesizer 320 and/or RX frequency synthesizer 332 may include a frequency multiplier, such as a frequency doubler, that is driven by an oscillator (e.g., a VCO) in the frequency synthesizer.
[0053] A controller 336 (e.g., controller/processor 280 in FIG. 2) may direct the operation of the RF transceiver circuit 300A, such as transmitting signals via the TX path 302 and/or receiving signals via the RX path 304. The controller 336 may be a processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field- programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof. A memory 338 (e.g., memory 282 in FIG. 2) may store data and/or program codes for operating the RF transceiver circuit 300. The controller 336 and/or the memory 338 may include control logic (e.g., complementary metal-oxide-semiconductor (CMOS) logic).
[0054] While FIGs. 1-3 provide wireless communications as an example application in which certain aspects of the present disclosure may be implemented to facilitate understanding, certain aspects described herein may be used for any of various other suitable systems.
Example Techniques for Digital Pre-Distortion (DPP)
[0055] The linearity of baseband circuits of in-phase and quadrature (EQ) (e.g., or other multi-phase) transmitters impacts various quality parameters of the transmitter, such as the error vector magnitude (EVM), spectrum emission mask (SEM), and adjacent channel leakage ratio (ACER). Linearity specifications make it difficult to design power- and-area-efficient digital-to-analog converters (DACs) for a transceiver due to the usage of higher supply voltage rails and designing good unit element matching for improved linearity. Relaxed linearity specifications for the DAC allow for fewer thermometer bits to be used, reducing area consumption. The baseband filter (BBF) may also be simplified if linearity specifications are relaxed, lowering gain-bandwidth (GBW) products and supply headroom and facilitate simpler architectures.
[0056] Some digital-predistortion (DPD) techniques reduce a power amplifier’s memoryless and memory nonlinearity (e.g., nonlinearity having a memory effect). The power amplifier (PA) DPD operates on the radio frequency (RF) signal as the DPD attempts to reduce the nonlinear response of the PA. Some DPD techniques target heavy nonlinearity and a strong memory effect in the PA and may be sophisticated, using an envelope memory polynomial or memory polynomial (e.g., may use many multipliers and adders to implement the polynomial for DPD).
[0057] Certain aspects of the present disclosure are directed towards a DAC DPD that attempts to correct the nonlinearity of each baseband path, including the DAC and the BBF, and in some cases, the mixer of the baseband path. The DAC DPD may be performed independently of the PA DPD and may offer power and area savings for each DAC, BBF, and/or mixer of the transmitter. The DAC DPD described herein enables simpler architectures and allows for the usage of lower supply headroom circuits, reducing area and power consumption.
[0058] FIG. 4 illustrates a transmitter 400, including DAC DPD circuitry 410, in accordance with certain aspects of the present disclosure. As shown, the transmitter 400 may include multiple baseband paths for processing in-phase (I), quadrature (Q), I with a 45° phase offset (145), and Q with a phase 45° offset (Q45) signals. For example, the transmitter 400 may include an I baseband path having an I DAC (labeled “DAC I”) with an output coupled to an input of an I BBF (labeled “BBF I”) with an output coupled to an input of an I mixer (labeled “Mixer I”). The DAC I may convert an I signal from a baseband processor 402 from the digital domain to the analog domain. The analog I signal may be provided to BBF I to generate a filtered analog I signal, which is then up- converted from a baseband frequency to radio frequency (RF) using the I mixer. In some cases, one mixer is used to convert the baseband signal from the baseband frequency to an intermediate frequency (IF), and another mixer is used to convert the signal from the IF to RF.
[0059] Similarly, the transmitter 400 may include an 145 baseband path having an 145 DAC (labeled “DAC I45”) with an output coupled to an input of an 145 BBF (labeled “BBF I45”) with an output coupled to an input of an 145 mixer (labeled “Mixer_I45”). The transmitter 400 may include a Q baseband path having a Q DAC (labeled “DAC Q”) with an output coupled to an input of a Q BBF (labeled “BBF Q”) with an output coupled to an input of a Q mixer (labeled “Mixer Q”). The transmitter 400 may also include a Q45 baseband path having a Q45 DAC (labeled “DAC Q45”) with an output coupled to an input of a Q45 BBF (labeled “BBF Q45”) with an output coupled to an input of a Q45 mixer (labeled “Mixer_Q45”). As shown, each of the 1, 145, Q, and Q45 mixers receives a local oscillator (LO) signal for up-conversion of signals from respective BBFs. The RF signals from the I, Q, 145, Q45 mixers may be provided to a combiner 404 to yield a combined signal for amplification via the PA 318 for transmission.
[0060] As shown, a transmitter 400 may include a feedback path for PA DPD. For example, the feedback path may include a feedback receiver 406 (e.g., for downconversion of the PA output signal) and a feedback ADC 408 (labeled “FBADC”) for conversion of the down-converted PA output signal from the analog domain to the digital domain. The digital feedback signal generated by the ADC 408 may be provided to the baseband processor 402, which may include a PA DPD circuit used to correct (or at least reduce) the nonlinearity associated with the PA based on the feedback signal.
[0061] In some aspects of the present disclosure, each of the I, 145, Q, and Q45 baseband paths may include a DAC DPD circuit, such as the I DAC DPD circuit (labeled “D AC DPD I”), the 145 DAC DPD circuit (labeled “DAC DPD I45”), the Q DAC DPD circuit (labeled “DAC DPD Q”), and the Q45 DAC DPD circuit (labeled “DAC DPD Q45”), respectively. The DAC DPD circuits may be configured to reduce nonlinearity associated with DACs of respective baseband paths, and in some aspects, reduce the nonlinearity associated with BBFs of respective baseband paths. The DAC DPD circuits may also be configured to reduce nonlinearity associated with a mixer coupled to each of the respective baseband paths, as described in more detail herein.
[0062] In some aspects, the DAC DPD circuits for the I, Q, 145, and Q45 paths may be calibrated (e.g., trained) separately to reduce nonlinearity. For example, the DAC DPD circuits may be coupled to respective DAC DPD feedback paths. In certain aspects, each of the DAC DPD feedback paths may be coupled between a node of respective baseband paths and respective DPD circuits for calibration. For example, the feedback paths may be coupled to the respective outputs of the 1, 145, Q, and Q45 BBFs. The feedback paths may include feedback ADC (FBADC) circuitry 412 configured to convert respective output signals of the I, 145, Q, and Q45 BBFs from the analog domain to the digital domain, based on which respective 1, 145, Q, and Q45 DAC DPD circuits are calibrated to reduce the nonlinearity associated with respective DACs and BBFs during mission mode. [0063] In some aspects, the feedback paths for the DAC DPD circuits may be coupled to the outputs of respective 1, 145, Q, and Q45 mixers, allowing the DAC DPD circuits to reduce the nonlinearity associated with respective mixers. The up-converted signals from the I, 145, Q, and Q45 mixers may be down-converted using down-conversion circuitry 414 before being provided to FBADC 412 for conversion to the digital domain and used to calibrate the respective DAC DPDs. In this manner, the DAC DPD circuits may be calibrated to account for not only the nonlinearity of respective DACs and BBFs, but also the nonlinearity of respective mixers, as described.
[0064] FIG. 5 illustrates an example baseband path having a DAC DPD circuit 502 and a feedback path for calibrating (e.g., training) the DAC DPD circuit 502, in accordance with certain aspects of the present disclosure. The DAC DPD circuit 502 may be coupled to a non-ideal DAC and BBF, such as the DAC and BBF of a baseband path described with respect to FIG. 4 such as DAC I and BBF I. The calibration may involve using iterative measurements and estimates of polynomial coefficients for the DAC DPD circuit in presence of a high-pass filter (HPF) to capture the frequency-dependent effects of the DAC and BBF nonlinearity. The polynomial coefficients and the filter parameters may be identified during calibration by methods such as gradient descent and error reduction. For example, the DAC DPD circuit 502 may include a digital HPF 506 (labeled “HPF a”) configured to receive a digital input signal (e.g., digital input bits), also referred to as a baseband signal, from the baseband processor. The HPF 506 has an output coupled to an input of a DPD correction circuit 508 (e.g., implementing a signal adjustment based on a polynomial) where the DPD correction circuit 508 generates an adjusted signal provided to an input of a combiner 510, where another input of the combiner 510 receives the digital input signal. The combiner 510 combines the digital input signal with the adjusted signal from the DPD correction circuit 508 to yield an adjusted baseband signal.
[0065] The adjusted baseband signal from the DAC DPD circuit 502 may be provided to the baseband processing circuitry 504 including a DAC and BBF. In FIG. 5, the baseband processing circuitry 504 is represented by an ideal DAC 512, an analog-domain HPF 514 (labeled “HPFa”), and a nonlinearity model circuit 516, the output of which is combined with the output of the ideal DAC 512 using combiner 518. The output of the combiner 518 is provided to a low-pass filter (LPF) 520, representing the BBF. During calibration, the baseband processing circuitry 504 may include the DAC and BBF to be calibrated, such as the DAC I and BBF I described with respect to FIG. 4. The baseband processing circuitry 504 generates an analog output voltage.
[0066] The nonlinearity of the DAC, BBF, and DAC to BBF interface degrades at higher frequencies. The increased nonlinearity at higher frequencies is modeled by the HPF 514 (e.g., providing greater magnitude for high-frequency signals provided to the nonlinearity model circuit 516). The HPF 514 has lower gains at direct-current (DC) and higher gains at higher frequencies, creating increased nonlinearity at higher frequencies. The DAC DPD circuit 502 also includes the HPF 506 to correct for the increased nonlinearity at higher frequencies. That is, higher frequency components associated with the digital input signal have a higher magnitude at the output of the HPF 506, and thus, higher frequency components receive a greater amount of DPD correction by the correction circuit 508.
[0067] The analog output voltage generated by the baseband processing circuitry 504 may be provided to an input of an ADC 522 of the feedback path for generating a digital signal based on the analog output voltage. The digital signal may be provided to a filter equalization circuit 524 configured to remove (e.g., cancel) the filtering effect of the LPF 520 to yield a signal representing the nonlinearity of the baseband processing circuitry 504, as described in more detail herein. The output signal yeqUaiized is subtracted from the digital input signal via combiner 526 (e.g., also referred to herein as a “comparison circuit”) to generate an error signal. The error signal may be provided to a DPD block update circuit 528 used to control the HPF and DPD correction circuit 508 to reduce the nonlinearity of the baseband processing circuitry 504. In other words, as described, iterative measurements of error signals in response to different DAC DPD polynomial coefficients and BBF parameters may be performed until the baseband path nonlinearity reaches a threshold.
[0068] In some aspects, a small-signal multi-tone input signal may be provided to the DAC to characterize the BBF (e.g., LPF 520) droop while not exercising the nonlinearities of the BBF. Once the BBF is characterized, the filter equalization circuit 524 may be used to remove the effect of the LPF (e.g., without the associated nonlinearity) during calibration so that the output signal yeqUaiized from the equalization circuit 524 represents the baseband path nonlinearity (e.g., without the filtering characteristics of the LPF), as described.
[0069] Based on the generated error signal from the combiner 526, the DPD block update circuit 528 updates the parameters of the HPF 506 and/or polynomial coefficients of the DPD correction circuit 508 to reduce the nonlinearity associated with the baseband path. The DPD block update circuit varies parameters until the error at the output of the combiner 526 is minimized (or at least meets an error threshold). The calibration process described with respect to FIG. 5 may be iterative and involve multiple iterations to converge. Once the calibration (e.g., training) is complete, the calibration parameters may be used during mission mode, as described in more detail with respect to FIG. 6.
[0070] In some aspects, a scalable gain stage 590 may be coupled between the HPF 506 and DPD correction circuit 508. The gain stage 590 may have a constant gain to increase the magnitude of the high-pass filtered signal from the HPF 506 before being provided to the correction circuit 508. In some aspects, the gain of the gain stage 590 may be set (e.g., selected via baseband processor 402) based on a modulation scheme used for transmission. Different modulation schemes may have different peak-to-average ratios and signal peaks that would warrant different gain amounts for the gain stage 590.
[0071] FIG. 6 illustrates an example baseband path operated in mission mode after calibration, in accordance with certain aspects of the present disclosure. As shown, once the polynomial coefficients for the DPD correction circuit 508 are identified during calibration, the DPD correction may be implemented using a look-up table (LUT) 602, storing adjustment values to be applied to digital input signals for DPD correction. The DAC DPD circuit 502 may drive the baseband processing circuitry 504, which may include a non-ideal DAC 604 (e.g., DAC I of FIG. 4) and a non-ideal BBF 606 (e g., BBF I of FIG. 4).
[0072] Certain aspects are directed towards measuring the nonlinearity of the baseband paths (e.g., I, Q, 145, Q45 paths described with respect to FIG. 4) separately during calibration and creating digital predistortion using the DAC DPD circuit 502. The digital predistortion may be implemented using any suitable architecture. In some aspects, the predistortion or modification of the incoming digital input signal (e.g., input bits) may be performed using the LUT 602 preceded with a filter (e.g., HPF 506) to amplify the high-frequency nonlinearities. The calibration process described herein reduces the error signal as the output of combiner 526, estimates coefficients of the nonlinear terms to be used to create the LUT 602, and calculates the predistortion filter (e.g., parameters of HPF 506) to create a low-cost memory effect. As described, the scalable gain stage 590 may be coupled between the HPF 506 and LUT 602 used to implement DPD correction. The gain of the gain stage 590 may be set based on the modulation scheme used for transmission, as described herein.
[0073] FIG. 7 illustrates an example implementation of the HPF 506, in accordance with certain aspects of the present disclosure. As shown, the HPF 506 may include a D flip flop 702 having an output Q coupled to an input of a gain element 704. The D flip flop 702 may apply a delay to the digital input x[n] (e.g., baseband signal from baseband processor 402 during a clock cycle n, n being a positive integer). In other words, the data input of the flip flop 702 may receive the digital input x[n] while the digital input x[n-l] during a previous clock cycle is at the output Q of the flip flop 702. The digital input x[n- 77 is provided to the gain element 704 to apply a gain k. The output of the gain element 704 is subtracted from the digital input x[n] via combiner 706 to yield a digital signal represented by equation: x[n] — k x x[n — 1]
In this manner, the HPF 506 captures the majority of the memory effect associated with the baseband path frequency dependent nonlinearity. HPF 506 may be calibrated to mimic the effect of HPF 514 described with respect to FIG. 5. HPF 514 may be a simple 2-tap digital filter, in some implementations.
[0074] The digital signal at the output of the combiner 706 is provided to the LUT and is predistorted (modified) based on a correction input signal (e.g., correction bits indicating the amount of correction that should be applied to the digital signal to obtain a linear response). The correction input signal selects a predistortion (e.g., adjustment value) stored in the LUT to be applied to the digital signal and may be selected based on the digital input x[n] to the baseband path. The predistorted signal (e.g., adjusted baseband signal) is then provided to the DAC 604 for conversion to the analog domain and to the BBF 606 to yield a filtered baseband signal. [0075] FIG. 8 is a graph 800 illustrating correction input signals provided to LUT 602 based on data input signals (e.g., baseband signals) of a baseband path, in accordance with certain aspects of the present disclosure. The line 804 represents a linear response associated with the baseband path (e.g., DAC I and BBF I, and in some cases, Mixer l of FIG. 4) while curve 802 represents an actual response of the baseband path without DPD. As shown, for each data input signal, a correction input may be provided to the LUT 602 to implement DPD and increase the linearity of the baseband path response. For example, for data input signal 806, the correction input signal 808 may be provided to the LUT based on previous training (calibration) to implement the correction represented by arrow 810. Storing a correction input signal for each of the data input signals may result in the LUT being overly large (e.g., 65,536 adjustment values may have to be stored for a 16-bit DAC). Thus, in certain aspects, the LUT may only store a single correction input signal for multiple data input signals to reduce the memory overhead associated with the LUT.
[0076] FIG. 9 is a graph 900 illustrating multiple data input signals associated with the same correction input signal, in accordance with certain aspects of the present disclosure. For example, the subset 902 of data input signals may be associated with correction input signal 904, resulting in the baseband path response 906. In the example described with respect to graph 900, for multiple data input signals (e.g., DAC codes), one correction input signal is used. As a result, only one of the subset 902 of the data input signals may result in the baseband path response falling on the line 804 representing a linear response. Moreover, the transition from one correction input signal (e.g., correction input signal 904) to another correction input signal (e.g., correction input signal 908) may result in high-frequency components in the DAC response, causing increased quantization noise. In some aspects, one or more correction inputs (e.g., for the selection of adjustment values stored in the LUT) may be identified using interpolation to reduce the quantization noise associated with the DAC.
[0077] FIG. 10 is a graph 1000 illustrating baseband path response correction using interpolation, in accordance with certain aspects of the present disclosure. For example, for one or more data input signals, the associated correction input signal may be identified using interpolation. For instance, for data input signal 1004, the associated correction input signal may be determined using interpolation based on correction input signals 904, 908, resulting in the baseband path response 1006.
[0078] The DAC DPD correction techniques described herein enable a new class of transmitters where efficiency can be achieved by using a low supply rail DAC and BBF while consuming smaller silicon area. Certain aspects allow for a transmitter to leverage simpler and easier DAC designs by compensating for the memory effect of the baseband path nonlinearity as described.
[0079] FIG. 11 illustrates an example current-steering cell 1101 for a DAC, in accordance with certain aspects of the present disclosure. As shown, by using the DAC DPD techniques described herein, the voltage rail of the current-steering cell 1100 may be reduced (e.g., from 1.9 V used for current-steering cell 1100 to 1.15 V used for currentsteering cell 1101, in some implementations), allowing for a reduction in the power consumption of the DAC. Moreover, the number of transistors used to implement the current source for the current steering-cell may be reduced. For example, the current source 1102 of cell 1100 may use six transistors coupled in cascode, whereas the current source 1103 of cell 1101 may use only three transistors coupled in cascode, allowing for a reduction in the size of the DAC. Thus, the techniques described herein lower the headroom specifications of the DAC, reducing power consumption while also reducing the area consumption of the DAC. The specification regarding the DAC's maximum common-mode voltage (VCM) may be relaxed, allowing for a more efficient BBF design.
[0080] FIG. 12 is a flow diagram illustrating example operations 1200 for wireless communication, in accordance with certain aspects of the present disclosure. The operations 1200 may be performed, for example, by a wireless device, such as a wireless device including the transmitter 400 of FIG. 4, which may include the circuitry described with respect to FIGs. 5-7.
[0081] At block 1202, the wireless device may receive, from a baseband processor (e.g., baseband processor 402), a first baseband signal at an input of a first DPD circuit (e.g., DPD circuit 502 of FIG. 6, which may correspond to one of DAC DPD I, DAC DPD Q, DAC DPD I45, or DAC DPD Q45 of FIG. 4) of a first baseband path, the first baseband path including a first DAC (e.g., DAC 604 of FIG. 6, which may correspond to one of DAC I, DAC Q, DAC I45, or DAC Q45 of FIG. 4) with an input coupled to an output of the first DPD circuit.
[0082] At block 1204, the wireless device may receive, from the baseband processor, a second baseband signal at an input of a second DPD circuit (e.g., DPD circuit 502 of FIG. 6, which may correspond to another one of DAC DPD I, DAC DPD Q, DAC DPD I45, or DAC DPD Q45 of FIG. 4) of a second baseband path, the second baseband path including a second DAC (e.g., DAC 604 of FIG. 6, which may correspond to another one of DAC I, DAC Q, DAC I45, or DAC Q45 of FIG. 4) with an input coupled to an output of the second DPD circuit.
[0083] At block 1206, the wireless device may generate a first adjusted baseband signal and a second adjusted baseband signal via the first DPD circuit and the second DPD circuit based on the first baseband signal and the second baseband signal, respectively. At block 1208, the wireless device may generate a first analog signal via the first DAC and a second analog signal via the second DAC based on the first adjusted baseband signal and the second adjusted baseband signal, respectively.
[0084] At block 1210, the wireless device may generate a combined signal via a combiner (e.g., combiner 404 of FIG. 4) based on the first analog signal and the second analog signal, and at block 1212, amplifies (e.g., via PA 318) the combined signal to generate an amplified signal for transmission.
[0085] In some aspects, the wireless device may generate one or more first feedback signals via a first feedback path coupled between a node of the first baseband path and the first DPD circuit. A first adjustment value used to generate the first adjusted baseband signal may be identified based on the one or more first feedback signals. The wireless device may also generate one or more second feedback signals via a second feedback path coupled between a node of the second baseband path and the second DPD circuit. A second adjustment value used to generate the second adjusted baseband signal may be identified based on the one or more second feedback signals.
[0086] The wireless device may filter the first baseband signal using a HPF (e.g., HPF 506 of FIG. 6), the first adjusted baseband signal being generated based on the filtered first baseband signal. The wireless device may generate (e.g., via combiner 510) a signal representing a difference between the first baseband signal and the first adjusted baseband signal. The first analog signal may be generated based on the signal. In some aspects, the wireless device may apply a gain to the filtered first baseband signal based on a modulation scheme for the transmission. In some aspects, the first DPD circuit may include a LUT (e.g., LUT 602 of FIG. 6) storing adjustment values used to generate the first adjusted baseband signal.
Example Aspects
[0087] In addition to the various aspects described above, specific combinations of aspects are within the scope of the present disclosure, some of which are detailed below:
[0088] Aspect 1 : An apparatus for wireless communication, comprising: a baseband processor; a first baseband path coupled to the baseband processor and including a first digital predistortion (DPD) circuit and a first digital-to-analog converter (DAC), an output of the first DPD circuit being coupled to an input of the first DAC; a second baseband path coupled to the baseband processor and including a second DPD circuit and a second DAC, an output of the second DPD circuit being coupled to an input of the second DAC; a first combiner with a first input coupled to the first baseband path and a second input coupled to the second baseband path; and an amplifier coupled to an output of the first combiner.
[0089] Aspect 2: The apparatus of Aspect 1, further comprising: a first feedback path coupled between a node of the first baseband path and the first DPD circuit; and a second feedback path coupled between a node of the second baseband path and the second DPD circuit.
[0090] Aspect 3 : The apparatus of Aspect 2, wherein the first feedback path comprises: a comparison circuit having a first input coupled to an input of the first baseband path and a second input coupled to the node of the first baseband path; and a DPD update circuit having an input coupled to an output of the comparison circuit and a first output coupled to the first DPD circuit.
[0091] Aspect 4: The apparatus of Aspect 3, wherein the first DPD circuit comprises a filter coupled between the input of the first baseband path and the first DPD circuit, wherein the DPD update circuit comprises a second output coupled to the filter. [0092] Aspect 5: The apparatus of Aspect 3 or 4, wherein the first feedback path further comprises an analog-to-digital converter (ADC) coupled between the node of the first baseband path and the first input of the comparison circuit.
[0093] Aspect 6: The apparatus according to any of Aspects 3-5, wherein: the first baseband path comprises a baseband filter (BBF); and the first feedback path further comprises a filter equalization circuit coupled between the node of the first baseband path and the first input of the comparison circuit and configured to cancel a filtering effect of the BBF to generate a signal representing a nonlinearity of the BBF.
[0094] Aspect ?: The apparatus according to any of Aspects 2-6, further comprising: a first mixer having an input coupled to the first baseband path and an output coupled to one of the inputs of the first combiner; and a second mixer having an input coupled to the second baseband path and an output coupled to another one of the inputs of the first combiner, wherein: the first feedback path is coupled between the output of the first mixer and the first DPD circuit; and the second feedback path is coupled between the output of the second mixer and the second DPD circuit.
[0095] Aspect 8: The apparatus of Aspect 7, wherein: the first feedback path comprises first down-conversion circuitry coupled between the output of the first mixer and the first DPD circuit; and the second feedback path comprises second downconversion circuitry coupled between the output of the second mixer and the second DPD circuit.
[0096] Aspect 9: The apparatus according to any of Aspects 2-8, wherein: the first baseband path further comprises a first baseband filter (BBF), the first feedback path being coupled between an output of the first BBF and the first DPD circuit; and the second baseband path further comprises a second BBF, the second feedback path being coupled between an output of the second BBF and the second DPD circuit.
[0097] Aspect 10: The apparatus according to any of Aspects 1-9, wherein the first baseband path comprises an in-phase (I) baseband path and wherein the second baseband path comprises a quadrature (Q) baseband path.
[0098] Aspect 11 : The apparatus of Aspect 10, further comprising: an I with a 45° phase offset (145) baseband path having a third DPD circuit coupled to a third DAC; a Q with a 45° phase offset (Q45) baseband path having a fourth DPD circuit coupled to a fourth DAC, wherein a third input of the first combiner is coupled to the 145 baseband path and wherein a fourth input of the first combiner is coupled to the Q45 baseband path; a first feedback path coupled between a node of the I baseband path and the first DPD circuit; a second feedback path coupled between a node of the Q baseband path and the second DPD circuit; a third feedback path coupled between a node of the 145 baseband path and the third DPD circuit; and a fourth feedback path coupled between a node of the Q45 baseband path and the fourth DPD circuit.
[0099] Aspect 12: The apparatus according to any of Aspects 1-11, wherein the first DPD circuit comprises a DPD correction circuit and a high-pass filter (HPF) coupled between an input of the first DPD circuit and an input of the DPD correction circuit, the input of the first DPD circuit being coupled to the baseband processor.
[0100] Aspect 13: The apparatus of Aspect 12, wherein the first DPD circuit comprises a second combiner having a first input coupled to the input of the first DPD circuit and a second input coupled to an output of the DPD correction circuit.
[0101] Aspect 14: The apparatus of Aspect 12 or 13, wherein the first DPD circuit further comprises a gain stage coupled between the HPF and the DPD correction circuit.
[0102] Aspect 15: The apparatus of Aspect 14, wherein a gain associated with the gain stage is configured to be set based on a modulation scheme for transmission using the first baseband path.
[0103] Aspect 16: The apparatus according to any of Aspects 1-15, wherein the first DPD circuit comprises a lookup table (LUT) configured to store adjustment values to be applied to digital input values from the baseband processor based on one or more correction input values.
[0104] Aspect 17: The apparatus according to any of Aspects 1-16, wherein the first DPD circuit comprises a lookup table (LUT) configured to store a first adjustment value for a first subset of digital input values from the baseband processor and a second adjustment value for a second subset of the digital input values. [0105] Aspect 18: The apparatus of Aspect 17, wherein the baseband processor is configured to determine at least one third adjustment value using interpolation based on the first adjustment value and the second adjustment value.
[0106] Aspect 19: A method for wireless communication, comprising: receiving, from a baseband processor, a first baseband signal at an input of a first DPD circuit of a first baseband path, the first baseband path including a first DAC with an input coupled to an output of the first DPD circuit; receiving, from the baseband processor, a second baseband signal at an input of a second DPD circuit of a second baseband path, the second baseband path including a second DAC with an input coupled to an output of the second DPD circuit; generating a first adjusted baseband signal and a second adjusted baseband signal via the first DPD circuit and the second DPD circuit based on the first baseband signal and the second baseband signal, respectively; generating a first analog signal via the first DAC and a second analog signal via the second DAC based on the first adjusted baseband signal and the second adjusted baseband signal, respectively; and generating a combined signal via a combiner based on the first analog signal and the second analog signal; and amplifying the combined signal to generate an amplified signal for transmission.
[0107] Aspect 20: The method of Aspect 19, further comprising: generating one or more first feedback signals via a first feedback path coupled between a node of the first baseband path and the first DPD circuit, wherein a first adjustment value used to generate the first adjusted baseband signal is identified based on the one or more first feedback signals; and generating one or more second feedback signals via a second feedback path coupled between a node of the second baseband path and the second DPD circuit, wherein a second adjustment value used to generate the second adjusted baseband signal is identified based on the one or more second feedback signals.
[0108] Aspect 21 : The method of Aspect 19 or 20, further comprising filtering the first baseband signal using a high-pass filter (HPF), the first adjusted baseband signal being generated based on the filtered first baseband signal.
[0109] Aspect 22: The method of Aspect 21, further comprising generating a signal representing a difference between the first baseband signal and the first adjusted baseband signal, wherein the first analog signal is generated based on the signal. [0110] Aspect 23 : The method of Aspect 21 or 22, further comprising applying a gain to the filtered first baseband signal based on a modulation scheme for the transmission.
[0111] Aspect 24: The method according to any of Aspects 19-23, wherein the first DPD circuit comprises a lookup table (LUT) storing adjustment values used to generate the first adjusted baseband signal.
[0112] Aspect 25: An apparatus for wireless communication, comprising: a baseband processor; a baseband path coupled to the baseband processor and including a digital predistortion (DPD) circuit and a digital-to-analog converter (DAC), an output of the DPD circuit being coupled to an input of the DAC; a first DPD feedback path coupled between a node of the baseband path and the DPD circuit; an amplifier having an input coupled to the baseband path; and a second DPD feedback path coupled between an output of the amplifier and the baseband processor.
[0113] The above description provides examples, and is not limiting of the scope, applicability, or examples set forth in the claims. Changes may be made in the function and arrangement of elements discussed without departing from the scope of the disclosure. Various examples may omit, substitute, or add various procedures or components as appropriate. For instance, the methods described may be performed in an order different from that described, and various steps may be added, omitted, or combined. Also, features described with respect to some examples may be combined in some other examples. For example, an apparatus may be implemented or a method may be practiced using any number of the aspects set forth herein. In addition, the scope of the disclosure is intended to cover such an apparatus or method which is practiced using other structure, functionality, or structure and functionality in addition to, or other than, the various aspects of the disclosure set forth herein. It should be understood that any aspect of the disclosure disclosed herein may be embodied by one or more elements of a claim.
[0114] The various operations of methods described above may be performed by any suitable means capable of performing the corresponding functions. The means may include various hardware and/or software component(s) and/or module(s), including, but not limited to a circuit, an application-specific integrated circuit (ASIC), or processor. Generally, where there are operations illustrated in figures, those operations may have corresponding counterpart means-plus-function components.
[0115] As used herein, a phrase referring to “at least one of’ a list of items refers to any combination of those items, including single members. As an example, “at least one of a, b. or c” is intended to cover: a, b. c, a-b. a-c, b-c. and a-b-c, as well as any combination with multiples of the same element (e.g., a-a. a-a-a. a-a-b. a-a-c. a-b-b, a- c-c, b-b, b-b-b, b-b-c, c-c, and c-c-c or any other ordering of a, b. and c).
[0116] The methods disclosed herein comprise one or more steps or actions for achieving the described method. The method steps and/or actions may be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and/or use of specific steps and/or actions may be modified without departing from the scope of the claims.
[0117] It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes, and variations may be made in the arrangement, operation, and details of the methods and apparatus described above without departing from the scope of the claims.