相关申请的交叉引用CROSS-REFERENCE TO RELATED APPLICATIONS
本申请要求于2023年8月31日提交给中国专利局的中国专利申请No.202311128877.4的优先权，其全部内容通过引用合并于此。This application claims priority to Chinese Patent Application No. 202311128877.4 filed with the China Patent Office on August 31, 2023, the entire contents of which are incorporated herein by reference.
本公开涉及但不限于通信设备技术领域。The present disclosure relates to, but is not limited to, the technical field of communication devices.
随着高速通信技术的高速发展，通信设备的吞吐量越来越大，对接收机的串行器和解串器(SerDes，Serializer/Deserializer)系统的速度要求也越来越高。为了支撑速率的提升，采用先进集成电路工艺是必然趋势。With the rapid development of high-speed communication technology, the throughput of communication equipment is getting higher and higher, and the speed requirements for the serializer and deserializer (SerDes) system of the receiver are also getting higher and higher. In order to support the increase in speed, the use of advanced integrated circuit technology is an inevitable trend.
然而，先进工艺普遍采用低电源电压设计，与高速模数转换器的输入缓冲器对电源电压的要求不匹配。However, advanced processes generally use low power supply voltage designs, which do not match the power supply voltage requirements of the input buffers of high-speed analog-to-digital converters.
发明内容Summary of the invention
本公开实施例提供一种输入缓冲器、一种模数转换器、一种接收机。Embodiments of the present disclosure provide an input buffer, an analog-to-digital converter, and a receiver.
第一方面，本公开实施例提供一种输入缓冲器，包括：第一电流镜模块、第一源跟随模块、第一共栅极放大模块、第一尾电流源模块、第一耦合电容；所述第一电流镜模块与第一公共电平端、第一节点、第二节点连接，配置为分配所述第一源跟随模块与所述第一共栅极放大模块的电流比例；所述第一源跟随模块与所述第二节点、第一输入端、第一输出端连接；所述第一共栅极放大模块与所述第一节点、所述第一输出端、第一偏置电压端连接；所述第一尾电流源模块与第二公共电平端、第二偏置电压端、所述第一输出端连接，配置为为所述第一源跟随模块、所述第一共栅极放大模块提供电流偏置；所述第一耦合电容与所述第一输入端、所述第一节点连接。In the first aspect, an embodiment of the present disclosure provides an input buffer, comprising: a first current mirror module, a first source follower module, a first common-gate amplifier module, a first tail current source module, and a first coupling capacitor; the first current mirror module is connected to a first common level terminal, a first node, and a second node, and is configured to distribute a current ratio between the first source follower module and the first common-gate amplifier module; the first source follower module is connected to the second node, a first input terminal, and a first output terminal; the first common-gate amplifier module is connected to the first node, the first output terminal, and a first bias voltage terminal; the first tail current source module is connected to the second common level terminal, the second bias voltage terminal, and the first output terminal, and is configured to provide current bias for the first source follower module and the first common-gate amplifier module; the first coupling capacitor is connected to the first input terminal and the first node.
第二方面，本公开实施例提供一种模数转换器，包括本公开实施例第一方面所述的输入缓冲器。In a second aspect, an embodiment of the present disclosure provides an analog-to-digital converter, comprising the input buffer described in the first aspect of the embodiment of the present disclosure.
第三方面，本公开实施例提供一种接收机，包括本公开实施例第二方面所述的模数转换器。In a third aspect, an embodiment of the present disclosure provides a receiver, comprising the analog-to-digital converter described in the second aspect of the embodiment of the present disclosure.
图1是一种共栅极放大结构的示意图；FIG1 is a schematic diagram of a common gate amplifier structure;
图2是本公开实施例中一种输入缓冲器的示意图；FIG2 is a schematic diagram of an input buffer according to an embodiment of the present disclosure;
图3是本公开实施例中另一种输入缓冲器的示意图；FIG3 is a schematic diagram of another input buffer in an embodiment of the present disclosure;
图4是本公开实施例中又一种输入缓冲器的示意图；FIG4 is a schematic diagram of another input buffer according to an embodiment of the present disclosure;
图5是本公开实施例中再一种输入缓冲器的示意图。FIG. 5 is a schematic diagram of yet another input buffer according to an embodiment of the present disclosure.
为使本领域的技术人员更好地理解本公开的技术方案，下面结合附图对本公开提供的输入缓冲器、模数转换器、接收机进行详细描述。In order to enable those skilled in the art to better understand the technical solution of the present disclosure, the input buffer, analog-to-digital converter, and receiver provided by the present disclosure are described in detail below with reference to the accompanying drawings.
在下文中将参考附图更充分地描述示例实施例，但是所述示例实施例可以以不同形式来体现且不应当被解释为限于本文阐述的实施例。反之，提供这些实施例的目的在于使本公开透彻和完整，并将使本领域技术人员充分理解本公开的范围。Example embodiments will be described more fully below with reference to the accompanying drawings, but the example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, the purpose of providing these embodiments is to make the present disclosure thorough and complete and to enable those skilled in the art to fully understand the scope of the present disclosure.
在不冲突的情况下，本公开各实施例及实施例中的各特征可相互组合。In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.
如本文所使用的，术语“和/或”包括一个或多个相关列举条目的任何和所有组合。As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
本文所使用的术语仅用于描述特定实施例，且不意欲限制本公开。如本文所使用的，单数形式“一个”和“该”也意欲包括复数形式，除非上下文另外清楚指出。还将理解的是，当本说明书中使用术语“包括”和/或“由……制成”时，指定存在所述特征、整体、步骤、操作、元件和/或组件，但不排除存在或添加一个或多个其它特征、整体、步骤、操作、元件、组件和/或其群组。The terms used herein are only used to describe specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "comprising" and/or "made of" are used in this specification, the presence of the features, wholes, steps, operations, elements and/or components is specified, but the presence or addition of one or more other features, wholes, steps, operations, elements, components and/or groups thereof is not excluded.
除非另外限定，否则本文所用的所有术语(包括技术和科学术语)的含义与本领域普通技术人员通常理解的含义相同。还将理解，诸如那些在常用字典中限定的那些术语应当被解释为具有与其在相关技术以及本公开的背景下的含义一致的含义，且将不解释为具有理想化或过度形式上的含义，除非本文明确如此限定。Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted as having an idealized or overly formal meaning unless explicitly defined as such herein.
使用共栅极放大结构来补偿源跟随结构的插损是一种经济有效的方案。该方案将共栅级放大管放到源级跟随器的下方，二者处于同一个支路中。如图1所示，源跟随管M11的栅极与输入端Vin连接、第一极与输出端Vout连接、第二极与电源端VDD连接，共栅极放大管M12的栅极与偏置电压端VG连接、第一极接地、第二级与输出端Vout连接，电容CL一极与输出端Vout连接、另一极接地，电阻Rs一端与输入端Vs连接、另一端与输入端Vin连接，电容CR一极与输入端Vin连接、另一极接地，IB、ICR、IZL表示电流；其中，共栅极放大管M12放在源跟随管M11下方，M12对M11结构的高频插损形成补偿，实现带宽拓展。为保证该结构可以正常工作，需要源跟随管M11、共栅极放大管M12以及作为微电流源的MOS管均工作在饱和区。这就要求输入电压足够高以保证足够的电压裕度，而这一点在低电压设计中很难做到。Using a common-gate amplifier structure to compensate for the insertion loss of a source follower structure is an economical and effective solution. This solution places the common-gate amplifier tube below the source follower, and the two are in the same branch. As shown in FIG1 , the gate of the source follower tube M11 is connected to the input terminalVin , the first electrode is connected to the output terminalVout , and the second electrode is connected to the power supply terminalVDD. The gate of the common-gate amplifier tube M12 is connected to the bias voltage terminalVG , the first electrode is grounded, the second stage is connected to the output terminalVout , one electrode of the capacitorCL is connected to the output terminalVout , and the other electrode is grounded. One end of the resistorRs is connected to the input terminalVs , and the other end is connected to the input terminalVin . One electrode of the capacitorCR is connected to the input terminal Vin,and the other electrode is grounded. IB , ICR , and IZL represent currents. Among them, the common-gate amplifier tube M12 is placed below the source follower tube M11, and M12 compensates for the high-frequency insertion loss of the M11 structure to achieve bandwidth expansion. To ensure that the structure can work properly, the source follower tube M11, the common gate amplifier tube M12 and the MOS tube as a micro-current source need to work in the saturation region. This requires the input voltage to be high enough to ensure sufficient voltage margin, which is difficult to achieve in low-voltage design.
有鉴于此，第一方面，参照图2至图5，本公开实施例提供一种输入缓冲器，包括：第一电流镜模块101、第一源跟随模块102、第一共栅极放大模块103、第一尾电流源模块104、第一耦合电容C1；第一电流镜模块101与第一公共电平端、第一节点Q1、第二节点Q2连接，配置为分配第一源跟随模块102与第一共栅极放大模块103的电流比例；第一源跟随模块102与第二节点Q2、第一输入端Vin,p、第一输出端Vout,p连接；第一共栅极放大模块103与第一节点Q1、第一输出端Vout,p、第一偏置电压端Vbcg连接；第一尾电流源模块104与第二公共电平端、第二偏置电压端Vb、第一输出端Vout,p连接，配置为为第一源跟随模块102、第一共栅极放大模块103提供电流偏置；第一耦合电容C1与第一输入端Vin,p、第一节点Q1连接。In view of this, in a first aspect, referring to FIGS. 2 to 5 , an embodiment of the present disclosure provides an input buffer, comprising: a first current mirror module 101, a first source follower module 102, a first common gate amplifier module 103, a first tail current source module 104, and a first coupling capacitor C1; the first current mirror module 101 is connected to a first common level terminal, a first node Q1, and a second node Q2, and is configured to distribute a current ratio between the first source follower module 102 and the first common gate amplifier module 103; the first source follower module 102 is connected to the second node Q2, a first input terminal Vin,p , and a first output terminal Vout,p ; the first common gate amplifier module 103 is connected to the first node Q1, a first output terminal Vout,p , and a first bias voltage terminal Vbcg ; the first tail current source module 104 is connected to a second common level terminal, a second bias voltage terminal Vb , and a first output terminal Vout,p , and is configured to provide a current bias for the first source follower module 102 and the first common gate amplifier module 103; the first coupling capacitor C1 is connected to the first input terminal Vin,p , the first node Q1 is connected.
在本公开实施例中，输入信号Vinp由第一输入端Vin,p输入后分成两路，一路经过第一源跟随模块102并输出到第一输出端Vout,p，另一路经过第一耦合电容C1耦合到第一共栅极放大模块103并输出到第一输出端Vout,p，输出信号Voutp即为第一源跟随模块102和第一共栅极放大模块103的输出之和，第一源跟随模块102和第一共栅极放大模块103的输出通过第一输出端Vout,p叠加输出。In the embodiment of the present disclosure, the input signal Vinp is input by the first input terminal Vin,p and then divided into two paths. One path passes through the first source follower module 102 and is output to the first output terminal Vout,p , and the other path passes through the first coupling capacitor C1 to be coupled to the first common-gate amplifier module 103 and is output to the first output terminal Vout,p . The output signal Voutp is the sum of the outputs of the first source follower module 102 and the first common-gate amplifier module 103. The outputs of the first source follower module 102 and the first common-gate amplifier module 103 are superimposed and output through the first output terminal Vout,p .
本公开实施例通过将第一源跟随模块102、第一共栅极放大模块103分别设置两个支路中，构成并联关系，能够降低输入输出电压，从而能够应用到低压输入设计中，有利于实现先进集成电路工艺。The disclosed embodiment arranges the first source follower module 102 and the first common gate amplifier module 103 in two branches respectively to form a parallel relationship, which can reduce the input and output voltages, so that it can be applied to low-voltage input design, which is conducive to the realization of advanced integrated circuit technology.
在本公开实施例中，源跟随结构和共栅极放大结构分别用两条支路实现。调节共栅极放大对缓冲器电路带宽补偿能力，除了可以调整共栅管M12的尺寸，还可以改变电流镜电流大小和比例，增加了设计自由度和灵活性。In the disclosed embodiment, the source follower structure and the common gate amplification structure are implemented with two branches respectively. The ability of the common gate amplification to compensate for the buffer circuit bandwidth can be adjusted. In addition to adjusting the size of the common gate tube M12, the current mirror current size and ratio can also be changed, which increases the design freedom and flexibility.
在一些实施例中，输入缓冲器为全差分结构。In some embodiments, the input buffer is a fully differential structure.
相应地，在一些实施例中，参照图3，输入缓冲器还包括：第二电流镜模块201、第二源跟随模块202、第二共栅极放大模块203、第二尾电流源模块204、第二耦合电容C2；第二电流镜模块201与第一公共电平端、第三节点Q3、第四节点Q4连接，配置为分配第二源跟随模块202与第二共栅极放大模块203的电流比例；第二源跟随模块202与第四节点Q4、第二输入端Vin,n、第二输出端Vout,n连接；第二共栅极放大模块203与第三节点Q3、第二输出端Vout,n、第一偏置电压端Vbcg连接；第二尾电流源模块204与第二公共电平端、第二偏置电压端Vb、第二输出端Vout,n连接，配置为为第二源跟随模块202、第二共栅极放大模块203提供电流偏置；第二耦合电容C2与第二输入端Vin,n、第三节点Q3连接。Accordingly, in some embodiments, referring to FIG. 3 , the input buffer further includes: a second current mirror module 201, a second source follower module 202, a second common gate amplifier module 203, a second tail current source module 204, and a second coupling capacitor C2; the second current mirror module 201 is connected to the first common level terminal, the third node Q3, and the fourth node Q4, and is configured to distribute the current ratio of the second source follower module 202 and the second common gate amplifier module 203; the second source follower module 202 is connected to the fourth node Q4, the second input terminal Vin,n , and the second output terminal Vout,n ; the second common gate amplifier module 203 is connected to the third node Q3, the second output terminal Vout,n , and the first bias voltage terminal Vbcg ; the second tail current source module 204 is connected to the second common level terminal, the second bias voltage terminal Vb , and the second output terminal Vout,n , and is configured to provide current bias for the second source follower module 202 and the second common gate amplifier module 203; the second coupling capacitor C2 is connected to the second input terminal Vin,n , and the third node Q3.
在本公开实施例中，输入信号Vinn由第二输入端Vin,n输入后分成两路，一路经过第二源跟随模块202并输出到第二输出端Vout,n，另一路经过第二耦合电容C2耦合到第二共栅极放大模块203并输出到第二输出端Vout,n，输出信号Voutn即为第二源跟随模块202和第二共栅极放大模块203的输出之和，第二源跟随模块202和第二共栅极放大模块203的输出通过第二输出端Vout,n叠加输出。In the embodiment of the present disclosure, the input signal Vinn is input from the second input terminal Vin,n and then divided into two paths. One path passes through the second source follower module 202 and is output to the second output terminal Vout,n , and the other path passes through the second coupling capacitor C2 and is coupled to the second common-gate amplifier module 203 and is output to the second output terminal Vout,n . The output signal Voutn is the sum of the outputs of the second source follower module 202 and the second common-gate amplifier module 203. The outputs of the second source follower module 202 and the second common-gate amplifier module 203 are superimposed and output through the second output terminal Vout,n .
相应地，在一些实施例中，第一输入端Vin,p与第二输入端Vin,n互为差分输入，第一输出端Vout,p与第二输出端Vout,n互为差分输出。Accordingly, in some embodiments, the first input terminal Vin,p and the second input terminal Vin,n are differential inputs to each other, and the first output terminal Vout,p and the second output terminal Vout,n are differential outputs to each other.
在一些实施例中，参照图4、图5，第一电流镜模块101包括第一晶体管M1、第二晶体管M2；第一晶体管M1的栅极连接第二节点Q2、第一极连接第一公共电平端、第二极连接第二节点Q2；第二晶体管M2的栅极连接第二节点Q2、第一极连接第一公共电平端，第二极连接第一节点Q1。In some embodiments, referring to Figures 4 and 5, the first current mirror module 101 includes a first transistor M1 and a second transistor M2; the gate of the first transistor M1 is connected to the second node Q2, the first electrode is connected to the first common level end, and the second electrode is connected to the second node Q2; the gate of the second transistor M2 is connected to the second node Q2, the first electrode is connected to the first common level end, and the second electrode is connected to the first node Q1.
在一些实施例中，第一源跟随模块102包括第三晶体管M3；第三晶体管M3的栅极连接第一输入端Vin,p、第一极连接第一输出端Vout,p、第二极连接第二节点Q2。In some embodiments, the first source follower module 102 includes a third transistor M3 ; the third transistor M3 has a gate connected to the first input terminal Vin,p , a first electrode connected to the first output terminal Vout,p , and a second electrode connected to the second node Q2 .
在一些实施例中，第一共栅极放大模块103包括第四晶体管M4；第四晶体管M4的栅极连接第一偏置电压端Vbcg、第一极连接第一节点Q1、第二极连接第一输出端Vout,p。In some embodiments, the first common-gate amplifier module 103 includes a fourth transistor M4 ; the fourth transistor M4 has a gate connected to the first bias voltage terminal Vbcg , a first electrode connected to the first node Q1 , and a second electrode connected to the first output terminal Vout,p .
在一些实施例中，第一尾电流源模块104包括第五晶体管M5；第五晶体管M5的栅极连接第二偏置电压端Vb、第一极连接第二公共电平端、第二极连接第一输出端Vout,p。In some embodiments, the first tail current source module 104 includes a fifth transistor M5; The gate is connected to the second bias voltage terminal Vb , the first electrode is connected to the second common level terminal, and the second electrode is connected to the first output terminal Vout,p .
在一些实施例中，参照图4、图5，第二电流镜模块201包括第六晶体管M6、第七晶体管M7；第六晶体管M6的栅极连接第四节点Q4、第一极连接第一公共电平端、第二极连接第四节点Q4；第七晶体管M7的栅极连接第四节点Q4、第一极连接第一公共电平端，第二极连接第三节点Q3。In some embodiments, referring to Figures 4 and 5, the second current mirror module 201 includes a sixth transistor M6 and a seventh transistor M7; the gate of the sixth transistor M6 is connected to the fourth node Q4, the first electrode is connected to the first common level end, and the second electrode is connected to the fourth node Q4; the gate of the seventh transistor M7 is connected to the fourth node Q4, the first electrode is connected to the first common level end, and the second electrode is connected to the third node Q3.
在一些实施例中，第二源跟随模块202包括第八晶体管M8；第八晶体管M8的栅极连接第二输入端Vin,n、第一极连接第二输出端Vout,n、第二极连接第四节点Q4。In some embodiments, the second source follower module 202 includes an eighth transistor M8 ; the eighth transistor M8 has a gate connected to the second input terminal Vin,n , a first electrode connected to the second output terminal Vout,n , and a second electrode connected to the fourth node Q4 .
在一些实施例中，第二共栅极放大模块203包括第九晶体管M9；第九晶体管M9的栅极连接第一偏置电压端Vbcg、第一极连接第三节点Q3、第二极连接第二输出端Vout,n。In some embodiments, the second common-gate amplification module 203 includes a ninth transistor M9 ; the ninth transistor M9 has a gate connected to the first bias voltage terminal Vbcg , a first electrode connected to the third node Q3 , and a second electrode connected to the second output terminal Vout,n .
在一些实施例中，第二尾电流源模块204包括第十晶体管M10；第十晶体管M10的栅极连接第二偏置电压端Vb、第一极连接第二公共电平端、第二极连接第二输出端Vout,n。In some embodiments, the second tail current source module 204 includes a tenth transistor M10 ; the tenth transistor M10 has a gate connected to the second bias voltage terminal Vb , a first electrode connected to the second common level terminal, and a second electrode connected to the second output terminal Vout,n .
在一些实施例中，参照图4，第一公共电平端为电源电压端VDD，第二公共电平端为接地端，第一晶体管M1、第二晶体管M2、第四晶体管M4、第六晶体管M6、第七晶体管M7、第九晶体管M9为N型晶体管；第三晶体管M3、第五晶体管M5、第八晶体管M8、第十晶体管M10为P型晶体管。In some embodiments, referring to FIG. 4 , the first common level terminal is a power supply voltage terminal VDD, the second common level terminal is a ground terminal, the first transistor M1, the second transistor M2, the fourth transistor M4, the sixth transistor M6, the seventh transistor M7, and the ninth transistor M9 are N-type transistors; the third transistor M3, the fifth transistor M5, the eighth transistor M8, and the tenth transistor M10 are P-type transistors.
在一些实施例中，参照图5，第一公共电平端为接地端，第二公共电平端为电源电压端VDD，第一晶体管M1、第二晶体管M2、第四晶体管M4、第六晶体管M6、第七晶体管M7、第九晶体管M9为P型晶体管；第三晶体管M3、第五晶体管M5、第八晶体管M8、第十晶体管M10为N型晶体管。In some embodiments, referring to FIG. 5 , the first common level terminal is a ground terminal, the second common level terminal is a power supply voltage terminal VDD, the first transistor M1, the second transistor M2, the fourth transistor M4, the sixth transistor M6, the seventh transistor M7, and the ninth transistor M9 are P-type transistors; the third transistor M3, the fifth transistor M5, the eighth transistor M8, and the tenth transistor M10 are N-type transistors.
第二方面，本公开实施例提供一种模数转换器，包括本公开实施例第一方面所述的输入缓冲器。In a second aspect, an embodiment of the present disclosure provides an analog-to-digital converter, comprising the input buffer described in the first aspect of the embodiment of the present disclosure.
第三方面，本公开实施例提供一种接收机，包括本公开实施例第二方面所述的模数转换器。In a third aspect, an embodiment of the present disclosure provides a receiver, comprising the analog-to-digital converter described in the second aspect of the embodiment of the present disclosure.
在一些实施例中，接收机为高速SerDes接收机。In some embodiments, the receiver is a high-speed SerDes receiver.
在本公开实施例中，输入信号由第一输入端输入后分成两路，一路经过第一源跟随模块并输出到第一输出端，另一路经过第一耦合电容耦合到第一共栅极放大模块并输出到第一输出端，输出信号即为第一源跟随模块和第一共栅极放大模块的输出之和，第一源跟随模块和第一共栅极放大模块的输出通过第一输出端叠加输出。本公开实施例通过将第一源跟随模块、第一共栅极放大模块分别设置两个支路中，构成并联关系，能够降低输入输出电压，从而能够应用到低压输入设计中，有利于实现先进集成电路工艺。In the disclosed embodiment, the input signal is divided into two paths after being input from the first input terminal, one path passes through the first source follower module and is output to the first output terminal, and the other path passes through the first coupling capacitor to couple to the first common gate amplifier module and is output to the first output terminal, and the output signal is the sum of the outputs of the first source follower module and the first common gate amplifier module, and the outputs of the first source follower module and the first common gate amplifier module are superimposed and output through the first output terminal. The disclosed embodiment can reduce the input and output voltages by respectively setting the first source follower module and the first common gate amplifier module in two branches to form a parallel relationship, so that it can be applied to low-voltage input design, which is conducive to the realization of advanced integrated circuit technology.
本文已经公开了示例实施例，并且虽然采用了具体术语，但它们仅用于并仅应当被解释为一般说明性含义，并且不用于限制的目的。在一些实例中，对本领域技术人员显而易见的是，除非另外明确指出，否则可单独使用与特定实施例相结合描述的特征、特性和/或元素，或可与其它实施例相结合描述的特征、特性和/或元件组合使用。因此，本领域技术人员将理解，在不脱离由所附的权利要求阐明的本公开的范围的情况下，可进行各种形式和细节上的改变。Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for limiting purposes. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly noted, features, characteristics, and/or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and/or elements described in conjunction with other embodiments. Therefore, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311128877.4ACN119576832A (en) | 2023-08-31 | 2023-08-31 | Input buffer, analog-to-digital converter, receiver |
| CN202311128877.4 | 2023-08-31 |
| Publication Number | Publication Date |
|---|---|
| WO2025044814A1true WO2025044814A1 (en) | 2025-03-06 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/CN2024/113111PendingWO2025044814A1 (en) | 2023-08-31 | 2024-08-19 | Input buffer, analog-to-digital converter, and receiver |
| Country | Link |
|---|---|
| CN (1) | CN119576832A (en) |
| WO (1) | WO2025044814A1 (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101159432A (en)* | 2007-11-13 | 2008-04-09 | 东南大学 | CMOS type differential interface circuit |
| CN102096079A (en)* | 2009-12-12 | 2011-06-15 | 杭州中科微电子有限公司 | Method for constructing radio frequency front end of multi-mode multi-band satellite navigation receiver and module thereof |
| CN103701533A (en)* | 2013-12-20 | 2014-04-02 | 天津大学 | Standard SiGe bipolar complementary metal-oxide-semiconductor transistor (BiCMOS) process-based optoelectronic integrated receiver |
| US20140159807A1 (en)* | 2012-12-07 | 2014-06-12 | Lsi Corporation | Multiple-clock, noise-immune slicer with offset cancellation and equalization inputs |
| CN111525961A (en)* | 2020-04-27 | 2020-08-11 | 联合微电子中心有限责任公司 | Analog front-end circuit of optical receiver and optical receiver |
| CN113131879A (en)* | 2019-12-31 | 2021-07-16 | 圣邦微电子（北京）股份有限公司 | Amplifier for switching body bias and follower |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101159432A (en)* | 2007-11-13 | 2008-04-09 | 东南大学 | CMOS type differential interface circuit |
| CN102096079A (en)* | 2009-12-12 | 2011-06-15 | 杭州中科微电子有限公司 | Method for constructing radio frequency front end of multi-mode multi-band satellite navigation receiver and module thereof |
| US20140159807A1 (en)* | 2012-12-07 | 2014-06-12 | Lsi Corporation | Multiple-clock, noise-immune slicer with offset cancellation and equalization inputs |
| CN103701533A (en)* | 2013-12-20 | 2014-04-02 | 天津大学 | Standard SiGe bipolar complementary metal-oxide-semiconductor transistor (BiCMOS) process-based optoelectronic integrated receiver |
| CN113131879A (en)* | 2019-12-31 | 2021-07-16 | 圣邦微电子（北京）股份有限公司 | Amplifier for switching body bias and follower |
| CN111525961A (en)* | 2020-04-27 | 2020-08-11 | 联合微电子中心有限责任公司 | Analog front-end circuit of optical receiver and optical receiver |
| Publication number | Publication date |
|---|---|
| CN119576832A (en) | 2025-03-07 |
| Publication | Publication Date | Title |
|---|---|---|
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