HYBRID MODE VOLTAGE REGULATOR
CROSS-REFERENCES TO RELATED APPLICATION
[0001] This application claims priority to Indian patent application No. 202241030640 entitled HYBRID MODE VOLTAGE REGULATOR filed on 27 June 2022.
FIELD OF INVENTION
[0002] The present disclosure generally relates to switching voltage regulators and more particularly, to improved proportional-integral-derivative (PID) controller.
DESCRIPTION OF THE RELATED ART
[0003] A conventional dc-dc converter uses Type-Ill or proportional-integral-derivative (PID) compensator, which could be implemented in analog or digital. While an analog controller provides good de accuracy, it requires an error amplifier and PWM modulator which are quite challenging to design at high speed. The digital controller provides the flexibility of programming and consumes lesser area on the chip but requires high resolution analog-to-digital converter and digital PWM which again are quite challenging to design at high speed.
[0004] Maja Dukik et al presented a digitally controlled analog PID, where a high-speed digitally controlled analog PID controller which combines the best features from both the analog implementation and the digital implementation. The controller allows tunability of the PID gains over a large frequency range, while also providing precise control of the system and reproducibility of the gain parameters. However, in order to achieve digital control of the gain parameters, some of the resistors were replaced with digital-to-analog converters. These DACs convert digital control data into a certain resistance value using a resistor ladder network. The use of additional hardware challenges the space needs in current devices. [0005] US 20220190720A1 describes a DC - DC converter including a switching buck regulator in which the controller uses two Voltage Controlled Oscillators (VCO) , two Voltage control Delay Lines (VCDL) and a phase detector instead of an operational amplifier and comparator, to implement the PID control system. Accordingly, the DC - DC converter can reduce a delay of a compensation circuit of the switching buck regulator. However the use of VCDL in PD path limits the transient response due to nonlinearity and limited dynamic range.
[0006] A time-based control technique combines the benefits of both analog and digital. By using time as the processing variable, it eliminates the need for wide bandwidth amplifiers, large on-chip compensation capacitors, PWM modulators, high resolution ADC and digital pulse width modulator (DPWM), while still operating with CMOS-level digital-like signals. In other words, the time-based approach combines the advantages of both analog (high accuracy, low quiescent current) and digital (low voltage operation, smaller area and process scalability) controllers. However, the use of voltage-controlled delay lines (VCDL) in the proportional and derivative (PD) path limits the transient performance of the time-based converter.
SUMMARY OF THE INVENTION
[0007] The invention describes an improved switching DC-DC voltage regulator device that operates under PID control. The voltage regulator uses a mixed- mode PID controller where it utilizes the benefits of both analog and digital circuits. The integral control processed in an analog circuit, and the proportional and differential control processed via a digital circuit. The integral control is processed in an analog circuit using a voltage- controlled oscillator (VCO) integrated with a clock divider and phase generator. The controller implements the VCO as a time-based analog-to-digital converter (ADC) to convert the error code into a digital code including the integral component. The VCO integrator is configured to output a frequency directly proportional to the integrated value. The VCO in the integral path is overclocked and implemented as time-based ADC, to select the VCO phase. The proportional and derivative path is processed digitally which includes a quantizer for quantizing the error signal, a differentiator for determining the rate of change of the error signal, and a summing junction for combining the proportional and derivative components. A second VCO, integrated with a clock divider, generates a reference clock signal. A phase mux is used to selectively combine the proportional and derivative components with the integrally generated clock signal based on a control signal to generate the regulated voltage.
[0008] In one aspect, the feedback signal is send to a first voltage-controlled-oscillator (VCO which is connected to a clock divider and phase generator, through a first path, to supply the integral component of the signal to the mux. The first VCO is further connected to a quantizer, through a second path, to generate a digital signal. The digital signal generated is passed through a digital differentiator. This digital signal and the differentiated signal of the same are input to a summing junction. The output of the summing junction is given as input to the phase mux which combines the proportional and derivative components with the integrally generated clock signal.
[0009] The control signal from the mux is provided along with the reference clock signal from the second VCO to a processing circuitry which may perform tasks such as signal conditioning, feedback processing, and output voltage control. The processing circuitry may include components like a synchronous rectification control (SRFF) and dead time logic to ensure efficient and controlled power transfer. It may also include voltage sensing and feedback mechanisms to monitor the regulated voltage and adjust the control signals accordingly. The output of the processing circuitry is connected to a load.
[0010] In another aspect the derivative and proportional path of the voltage regulator may be further implemented by an analog circuit using a first Voltage Control Delay Line (VCDL) and a second Voltage Control Delay Line (VCDL). Both the VCDLs are connected in series to the output of the phase mux of the mixed mode PID controller. The output of the second Voltage Control Delay Line is given as control signal to the processing circuitry.
[0011] The invention in various embodiments may be implemented in multiphase mode. The improved mixed mode PID controller implements multiphase mode by employing a phase mux corresponding to each of the multiple phases. The multiple phase inputs from the integral path are fed to each of the corresponding phase mux along with the signal from the proportional and differential path. Each phase mux combines the proportional and derivative components along with the integrally generated clock signals to generate the regulated voltage for the corresponding phase.
[0012] The invention further discloses an improved switching DC-DC voltage regulator that operates in a combined analog and digital mode PID control in which the PID controller consists of an Analog to Digital Converter (ADC) to convert analog feedback voltage to digital code. The digital code is processed by a Digital Compensator, which generates the phase select code. The Digital Compensator may operate in different modes, such as Proportional Derivative (PD), Proportional Integral (PI), or Proportional Integral Derivative (PID). The feedback voltage and the reference voltage is given as input to the ADC. The output of the ADC is fed to the Digital Compensator. A first voltage-controlled oscillator (VCO) is integrated with a clock divider and phase generator, generating a clock signal with adjustable frequency and phase. A second VCO integrated with a clock divider generates a reference clock signal. A phase mux combines the phase select code from the Digital Compensator and the clock phases from the integral VCO, and generates control signals required for the voltage regulation process. The output of the phase mux is given to a processing circuitry combines these control signals from the phase mux with the reference clock signal from the second VCO's integrated clock divider to generate a controlled voltage output. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] The invention has other advantages and features, which will be more readily apparent from the following detailed description of the invention and the appended claims, when taken in conjunction with the accompanying drawings, in which:
[0014] Figure 1 illustrates single phase DC-DC converter using hybrid mode time-based PID controller
[0015] Figure 2 illustrates multi-phase DC-DC converter using hybrid mode time-based PID controller
[0016] Figure 3 illustrates the design of voltage regulator with a derivative and proportional path implemented using VCDL in the analog loop.
[0017] Figure 4 illustrates an embodiment which realizes the digital path using an ADC instead of VCO.
[0018] Figure 5 illustrates the difference in transient response, while using analog control and mixed mode PID controller.
DETAILED DESCRIPTION OF THE EMBODIMENTS
[0019] While the invention has been disclosed with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the invention. In addition, many modifications may be made to adapt to a particular situation or material to the teachings of the invention without departing from its scope.
[0020] Throughout the specification and claims, the following terms take the meanings explicitly associated herein unless the context clearly dictates otherwise. The meaning of “a”, “an”, and “the” include plural references. The meaning of “in” includes “in” and “on.” Referring to the drawings, like numbers indicate like parts throughout the views. Additionally, a reference to the singular includes a reference to the plural unless otherwise stated or inconsistent with the disclosure herein.
[0021] The invention in various embodiments proposes a hybrid-mode switching DC-DC voltage regulator (100) configured to operate under Proportional-Integral-Derivative (PID) controller (HO), wherein the integral part processed in an analog circuit and the proportional and derivative control processed by a digital circuit. The hybrid-mode PID controller uses VCO (111) as integrator which is analog in nature, it offers the accuracy of an analog controller. Instead of using a separate ADC, the hybrid-mode PID controller utilizes the voltage-controlled oscillator (VCO) used in the integral path as time-based ADC in order to convert the error into a digital code. The hybrid-mode PID in various embodiments replaces the VCDL based Proportional -Derivative with digital PD. The use of VCO integrator also reduces the resolution requirement of time-based ADC. The DC- DC converter in various embodiments may be implemented to work in single phase mode, as in FIG 1, or in multi-phase mode, as in FIG 2.
[0022] The invention in various embodiments provides implicit phase matching and hence does not require additional phase balancing circuits. The pulse frequency modulation (PFM) mode can be implemented by reducing the frequency of a voltage- controlled oscillator (VCO) as a function of load current. Since lower VCO frequency reduces the bandwidth under light load conditions and degrades transient response when converter transitions between PFM-PWM modes. In order to improve the transient response during mode transition dynamic clock frequency is used. A non-synchronous transient detector provides instant information about a transient event which is used to immediately switch the VCOs from low to a high frequency without waiting for the load current information.
[0023] In various embodiments, a hybrid-mode DC-DC voltage regulator (100) as shown in FIG. 1 to regulate an output voltage which combines the advantage of both digital and analog circuits is disclosed. The regulator (100) includes a PID controller that uses voltage-controlled-oscillator (VCO) integral control and a digital Proportional -Derivative (PD) and processing circuitry (120) to process the output from the PID control, to provide a regulated output voltage based on a load current in the load circuit.
[0024] In some embodiments, the regulator (100) is a time-based voltage regulator. In various embodiments, PID controller (HO) includes a first VCO (111) configured to receive a feedback voltage based on a load current and generate multiple phase shifted output signals. Further, the PID controller includes a second VCO (112) configured to generate reference clock signals. This first VCO (111) is integrated with a clock divider and phase generator (113) to generate a clock signal with adjustable frequency and phase.
[0025] In various embodiments the digital proportional and derivative (PD) control path of the PID controller comprises a quantizer (114) configured to quantize the error signal, discretizing it for further processing, a differentiator (115) to calculate the rate of change of the error signal by providing the derivative component of the control loop. The proportional and derivative components are then summed at a summing junction (116).
[0026] In various embodiments, a second VCO (112) integrated with a clock divider (118) is utilized to generate a reference clock signal, in the controller. A phase mux (117) is configured to selectively combine the proportional and derivative components with the clock signal generated by the first VCO (111). This combination is determined by a control signal and results in the generation of the regulated voltage.
[0027] In various embodiments, a phase mux (117) configured to select a single phase signal in response to clock phases generated by the clock divider and phase generator in the integral path. The phase selector may be configured to activate or deactivate one or more phases.
[0028] The controller utilizes the VCO (111) in the integral path as a time-based analog- to-digital converter (ADC) for converting the error code into a digital code that includes the integral component. By utilizing the VCO in the integral path as an ADC, the hybrid mode PID controller retains the accuracy associated with analog controllers. Analog controllers are known for their ability to provide precise and continuous control, particularly when it comes to integrating signals over time. The VCO, serving as an analog integrator, preserves this accuracy by allowing the integral component of the error to be calculated using analog techniques.
[0029] In various embodiments, the PID controller (110) using the VCO as an ADC, the resolution requirement for the time-based ADC is reduced. Digital PD control typically demands high-resolution ADCs to accurately represent the error signal and perform precise derivative calculations. However, the use of the VCO integrator as an ADC allows for a relaxation of this high-resolution requirement. Since the integral component, which is crucial for accurate control, is obtained from the VCO integrator, the resolution requirement for the ADC responsible for PD control can be reduced. This reduction in resolution alleviates the need for a high-resolution ADC and can lead to cost savings and simplified implementation.
[0030] In various embodiments, the integral VCO (111) includes a plurality of phases configured to be enabled or disabled by the phase selector based on a load current. When a high voltage is applied to the VCOs (Voltage-Controlled Oscillators), the VCO runs at a higher frequency than its typical operating range. The factor 2N*Fsw represents the frequency at which the VCO is overclocked, where N is the number of phases in the VCO and Fsw is the desired switching frequency. The selected phases of the VCO signal obtained through the ADC are then used to generate a Pulse Width Modulation (PWM) signal.
[0031] The N- bit digital control implemented in the device of the invention may be obtained using two method embodiments. In one embodiment of the method, the VCO may be overclocked at 2N*Fsw hence producing N-bit count in one clock cycle of Fsw where Fsw=l/Tsw is the converter switching frequency. N-bit control code in this case may be generated by counting the number of feedback VCO clock cycles in one clock period of reference switching period (Tsw).
[0032] In another embodiment of the method, out of the N bits, M Least Significant Bits (LSB) may be used to select one of the 2M phases. VCO is overclocked at 2N'M*Fsw which after clock dividing by N-M produces total of 2N phases. To generate the M-bit LSB control code, the phases of the feedback VCO (FB VCO) are compared with the phases of the reference VCO (REF VCO). This phase comparison allows the determination of the M-bit control code. On the other hand, the N-M Most Significant Bits (MSB) control code is generated by counting the feedback VCO clock cycles within one clock period of the reference switching period (Tsw).
[0033] The device of the invention is configured to generate PWM signals implicitly, without using a separate PWM modulator. Instead, the desired PWM signal may be obtained directly from the VCO integrator. When the VCO is used as an integrator, the voltage integrated over time may be considered as an analog representation of the desired PWM signal.
[0034] In a single-phase controller as shown in FIG. 1, only one of the 2N*Fsw VCO phases is utilized to generate the Pulse Width Modulation (PWM) signal. PWM modulation technique controls the width of pulses in a periodic signal while keeping the frequency constant. By adjusting the width of the pulses, the average value of the signal may be manipulated. By selecting one phase out of 2N *Fsw, the VCO generates a PWM signal that carries information about the desired control action. This PWM signal is then used in conjunction with the digital PD controller to regulate the VCO's behaviour. The resolution of the PWM signal determines the granularity of control that may be achieved. The digital PD controller processes the error signals and adjusts the duty cycle of each phase's PWM signal to regulate the VCO's output. [0035] In various embodiments, the switching DC-DC voltage controller is configured to operate in multi -phase mode (200) as shown in FIG. 2. In a multi-phase controller, equally spaced multiple phases of the VCO are employed to generate the PWM signal. The number of phases, N, is greater than one, and each phase is equally spaced in the VCO's period. For example, in a 4-phase VCO, the phases would be 0°, 90°, 180°, and 270°. For N phase voltage controller, clock phases from the integral path and the control signals corresponding to each of the phases from the digital PD path are fed to a phase mux (217- 1, 217-2... 217-n) corresponding to each of the multiple phases, to generate the regulated voltage at the corresponding phase.
[0036] In one embodiment of the device, an analog derivative and proportional part is additionally incorporated for obtaining faster settling times, improved control response, and enhanced stability as shown in FIG. 3. The derivative and proportional analog loop is implemented using two Voltage Control Delay Lines (VCDL) (301,302) connected in series to the phase mux of the mixed mode PID controller. The first VCDL (301), which implements the proportional part, receives the control signal generated from the phase mux (317) as input. The second VCDL (302) implements the derivative part and the output control signal is given to the processing unit (320). By adjusting the delays within the VCDLs, the control signal may be precisely timed and synchronized within the analog loop. This ensures accurate and synchronized control actions, facilitating better performance and control accuracy.
[0037] In an alternate embodiment of the device, as shown in FIG. 4, a separate Analog to Digital Converter (ADC) (414) is employed instead of using the Voltage-Controlled Oscillator (VCO) as both an integrator and an ADC. The digital path is implemented by a circuitry comprising an Analog to Digital Converter (ADC) (414) and a digital compensator (415). The ADC (414) converts the analog feedback voltage into a digital code. It samples the analog voltage at specific intervals and quantizes the difference between the sampled value and the reference voltage into discrete digital codes. This digital code is further processed by the digital compensator (415) to generate the phase select code used by the phase mux (417). The digital compensator can be designed as a Proportional Derivative (PD), Proportional Integral (PI), or Proportional Integral Derivative (PID) compensator, depending on the desired control characteristics and system requirements. The phase select code generated by the digital compensator (415) is used by the phase mux (417) to control the regulated output voltage.
[0038] The invention has many advantages as set forth herein. The overclocked integral VCO is used as time-based ADC which is used to select the VCO phases and provide a large signal change in PWM signal for better transient response. Use of the VCO integrator as A/D converter completely eliminates the need of an explicit A/D to implement the digital PD (proportional -derivative) control. The use of VCO integrator also relaxes the need of high resolution A/D converter. Highly digital nature of the controller makes it easier to operate at lower voltages in advanced process node where analog controller finds it difficult to provide the desired performance.
[0039] A conventional de -de converter uses Type-Ill or proportional-integral-derivative (PID) compensator, which could be implemented in analog or digital. While analog controller provides good de accuracy, ideally infinite, it requires error amplifier and PWM modulator which are quite challenging to design at high speed. Digital controller provides flexibility of programming and consumes lesser area on the chip but requires high resolution analog-to-digital converter and digital PWM which again are quite challenging to design at high speed. The proposed time-based control technique combines the benefits of both analog and digital. By using time as the processing variable, it eliminates the need for wide bandwidth amplifiers, large on-chip compensation capacitors, PWM modulator, high resolution ADC and digital pulse width modulator (DPWM), while still operating with CMOS-level digital-like signals.
[0040] Although the detailed description contains many specifics, these should not be construed as limiting the scope of the invention but merely as illustrating different examples and aspects of the invention. It should be appreciated that the scope of the invention includes other embodiments not discussed herein. Various other modifications, changes and variations which will be apparent to those skilled in the art may be made in the arrangement, operation and details of the system and method of the present invention disclosed herein without departing from the spirit and scope of the invention as described here, and as delineated in the claims appended hereto.
EXAMPLE
[0041] Example 1: Design of a 6-bit Resolution Mixed-Mode PID Controller
[0042] The following parameters and calculations are considered based on the given specifications in order to achieve 6-bit resolution in the digital Proportional-Derivative (PD) path.
6-bits resolution (N=6) is achieved by running the VCOs at 8 times (3-bits) of FSW.
VCOs with 8 delay cells derived using 3 LSB bits of the desired resolution Switching Frequency, Fsw = 50MHz
VCO frequency, FVco = 400MHz (8xFsw) derived using 3 MSB bits
Tvco= 1/Fvco= 2.5ns
Time step (1 LSB) = 2.5ns/8 = 0.3125ns
With FSW set at 50 MHz, the time step of 0.3125 ns provides the desired 6-bit resolution. This means that there are a total of 64 time steps (26 = 64) to represent the full range of control in the PD path.
[0043] Negative feedback loop forces two VCOs, namely the Feedback VCO and the Reference VCO, to be locked in frequency .this means their frequencies are equal.
FVCO_FB= FVCO_REF-
Since the two VCOs are identical the only condition for lock is that the output voltage (Vo) should be equal to the reference voltage (VREF) VQ-VREF.
[0044] When two VCOs are not locked (VQAVREF), VCO acting as an analog integrator in phase domain, integrates the frequency error until the VCOs are locked in frequency with phase difference required to generate the desired duty cycle for Vo =VREF- During a transient, if a Vo drifts away from VREF, the VCOs lose the frequency locked state. VCOs acting as an integrator, integrate the frequency error until the VCOs are lock in frequency with phase difference required to generate the desired duty cycle for VQ=VREF-
[0045] During transient, either on load change or line change, the loop needs to react fast and provide sudden change in duty cycle for transient correction. Since analog loop is slow in nature due to integrator, the fast change in duty cycle is achieved by the digital PD (proportional-derivative) loop. The difference in transient correction while using the analog loop and mixed mode PID controller is shown in FIG. 5. The 6-bit digital control code (DCIRL<5 :0>) is generated by converting the voltage error into frequency error through VCOs and then counter and phase detectors, as by generating the M-bit LSB code design procedure.
[0046] The 6-bit digital control code is used select one of the 64 phases to provide instant duty cycle correction. Once the transient is corrected, the control code, DCTRL<5 :0> becomes 0. Any error in the duty cycle is further corrected by the analog integral loop making V0=VREF.