SYSTEM-ON-CHIP FOR LOW-SPEED NOISE-RESISTANT DATA TRANSMISSION
Inventors: Andrey Orlov, Vasiliy Anisimov, Alexey Danilov, Andrey Puzanov, Sergey Omelchenko, Andrei Bakumenko, and Danylo
Batura .
Priority Claim/Incorporation by Reference
[0001] The present application claims priority to U.S.
Provisional Patent Applications: 62/440,884 filed on
December 30, 2016 entitled "System-on-chip for low-speed noise- resistant data transmission"; and hereby incorporates by
reference, the entire subject matter of this Provisional
Application .
Background Information
[0002] Many applications require low-speed wireless data
transfer operating on high range, where data signal is very close to noise floor at the receiving end. Receiver must receive many messages simultaneously and receive messages with random carrier frequency offset (CFO) , even when CFO is greater than the signal bandwidth. System-on-chip must include both the transmitter, receiver and dedicated resources to fulfill user tasks .
[0003] Using narrowband signals is one of simplest ways to improve efficiency and reliability of transmission, but it is limited by carrier frequency uncertainty resulting in carrier frequency offset in receiver. In most systems, carrier frequency must be relatively low compared to signal bandwidth. In some prior art solutions, signal bandwidth is increased and noise tolerance is managed using some sort of error-correction coding of just repetitions. For example, LoRa wireless protocol is widely known. It uses chirp spread spectrum, utilizing very wide bands compared to information speed of transmission. LoRa uses CDMA multiple access, which is different from the solution proposed in this invention. SigFox is another prior art solution employing multichannel receivers with carrier tracking. This solution is limited by computational inefficiency of carrier tracking systems. Also, it is algorithmically and
computationally difficult to employ error correction coding in such systems, as they are limited by noise tolerance of carrier tracking systems.
Summary
[0004] Described is a system-on-chip comprising a hardware digital baseband modulator and demodulator, of at least two processor cores, of optional radio frequency frontend and optional signal parameters estimation modules.
[0005] The system-on-chip architecture includes transceiver that can receive signals with large carrier offsets so the embodiment can receive narrowband signals in Local Power Area Wide Area Network (LPWAN) . In addition, the system-on-chip includes error correction code coder/decoder modules, or other means of
providing error correction capabilities to increase power efficiency and provide resistance to interference and collision. It includes hardware digital signal processing modules which provide well-known narrowband modulation/demodulation
(DBPSK/DQPSK) . Also, receiver module analyzes the whole band used for transmission including side guard intervals to compensate CFO.
Detailed Description
[0006] The exemplary embodiment maybe further understood with reference to the following description. The exemplary embodiment describes a system-on-chip whose architecture enhances wireless data transmission capacities such as resistance to noise and interference, resistance to carrier frequency offset including cases when CFO is greater than signal bandwidth, high power efficiency, high spectral efficiency, ability to receive and decode many simultaneous messages.
[0007] An exemplary embodiment is a system-on-chip comprising digital DBPSK/DQPSK modulator and demodulator which can
demodulate many simultaneous narrowband signals with carrier frequency offset greater than signal bandwidth and at least, one general purpose processor. Optionally, system-on-chip also contains RF analog front-end and/or signal parameters estimation modules. Also, other modules might be present, for example additional digital signal processing modules.
[0008] The system-on-chip comprising both digital and
optionally, analog transceiver and at least, two processor cores. This transceiver can receive signals with large carrier offsets relative to signal bandwidth, so the system-on-chip is able to receive narrowband signals in LPWAN systems. Using narrowband signals is one of simplest ways to improve efficiency and reliability of transmission, but it is limited by carrier frequency uncertainty resulting in carrier frequency offset in receiver. In most systems, carrier frequency must be relatively low compared to signal bandwidth. [0009] There are many transceivers available on the market today, most notably in the LPWAN market, such as Axsem ax8052, semtech sxl276, Microchip ATA8520 (SigFox) , etc.
[0010] These transceivers are usually not able to receiver narrowband messages with relatively large carrier frequency offsets. Some of transceivers, like SemTech, utilize very large bands to transmit data using some sorts of spread spectrum modulation. Other transceivers use narrowband messaging for transmitting data, but require wider bands for receiving and/or some sorts of sophisticated carrier frequency tuning on
transmitting side.
[0011] In addition to demodulator, processor cores, signal estimation modules, possible RF analog modules, the embodiment can be modified to add other hardware modules such as additional digital signal modules and more processor cores.
[0012] The embodiment includes hardware error correction code coder/decoder modules, or other means of providing error
correction capabilities to increase power efficiency and provide resistance to interference and collision.
[0013] The system-on-chip includes hardware digital signal processing modules to provide well-known narrowband
modulation/demodulation (DBPSK/DQPSK) . Narrowband modulation with time and frequency division multiple access is quite spectrally efficient as compared to the code-division multiple access .
[0014] The receiver module analyzes the whole band used for transmission including side guard intervals to compensate CFO. Fourier-based analysis might be used, and to increase its frequency resolution, additional frequency shifts might be applied to time domain data before conversion to frequency domain .
[0015] System-on-chip includes hardware cores for transmission and receiving of narrowband signals as well as hardware FEC encoder and decoder thereby improving power-efficiency and allowing to dedicate one processor core for user tasks. Also, due to simultaneous multi-channel decoding capability, said system-on-chip can function as a small base-station, also having some computing power in dedicated processor core.