WO2008075292A2 - Power-on temperature sensor/spd detect - Google Patents

Abstract

A method of controlling the power consumption of a multi-functional integrated circuit, such as a serial presence detect combined with a temperature sensor, is outlined. The multi-functional integrated circuit is designed to provide one function in which all circuits are active in response to being operated under one set of conditions and to provide another function' or multiple functions in which the temperature sensor is deactivated to save power under a second set of conditions. Advantageously the conditions are established through a simple mechanism, such as varying the level of the power supply, that takes advantage of the wide operating ranges of semiconductor circuits and allows the configuration of the multi-functional integrated circuit to be set without requiring modification to software.

Description

Embedded Power Management in Serial Presence Detect Circuits

FIELD OF THE INVENTION

The invention relates to the field of electronic circuits and more particularly to serial- presence-detect circuitry such as that used for identifying memory modules within electronic microcomputers.

BACKGROUND OF THE INVENTION

Although processing power and storage capacities have increased beyond all recognition since the first introduction of microprocessors in the 1970s the underlying technology of microcomputers and their operations have remained basically the same. An important element of this underlying operation is the serial presence detect (SPD) performed when a microprocessor or microcomputer is booted (started or restarted). SPD is information stored in a RAM memory module that tells the microcomputers basic input/output system (BIOS) the module's size, data width, speed, and voltage. The BIOS uses this information to configure the memory properly for maximum reliability and performance. If a memory module does not have SPD, the BIOS assumes the memory module's information. With some memory, this does not cause problems. But SDRAM memory has to have SPD or the computer may not boot at all. If it does boot, the assumed information may cause fatal exception errors.

As such integrated circuits (ICs) have been developed to access the SPD information within RAM memory modules and as with many integrated circuit technologies there is commercial benefit of integrating additional functionality of the microcomputer into the same semiconductor die as that performing the SPD process. It is therefore common for such SPD circuits to be integrated with a self-contained temperature sensor. This provides advantages such as reduced component count, reduced inventory, smaller microcomputer footprint, and reduced cost. However, the resulting integrated circuit has increased power consumption which whilst not always critical for motherboard applications within PCs, is a critical aspect for designers of microcomputers intended for handheld, portable, and remote applications wherein their power is derived primarily from battery modules. Alternatively, employing the IC as part of a common platform for lower manufacturing costs and standardization also suffers the disadvantage of increased power consumption as not all supplied variants of the common platform require the full IC functionality.

Within a multi-function IC providing a means of adjusting power consumption in the prior art has meant providing control signaling to the integrated circuit instructing it as to which portions of the IC should be powered and which un-powered. This produces several disadvantages including a lack of backward compatibility with existing circuit designs, additional input pins, cost, to the IC package, separate programming to control the IC, increased communication requirements to what otherwise might be a very simple IC; These disadvantages offset the advantages previously outlined.

For designers of portable systems employing microcomputers every milliwatt of power saved from the operation of the device results in increased battery life, and a major commercial edge in the penetration of the device into high volume applications, such as those in consumer markets such as PDAs, cellular telephones, and portable gaming devices.

It would be advantageous to provide an integrated circuit that overcomes the above noted problems with the prior art.

SUMMARY OF THE INVENTION

In accordance with an embodiment of the invention there is provided a method comprising providing a circuit with two modes of operation, the circuit comprising a first circuit and second circuit, and providing a power supply signal; the power supply signal being other than ground. Enabling the first mode of operation when the power supply signal has a first characteristic; and enabling the second mode of operation when the power supply signal has a second characteristic.

In accordance with another embodiment of the invention there is provided an integrated circuit comprising a first circuit, a second circuit, a package pin, the package pin for receiving a power supply signal other than ground. Also provided is a decision circuit, the decision circuit electrically coupled to the package pin and responsive to a characteristic of the power supply signal, and for selecting a first mode when the characteristic is within a first range and a second mode when the characteristic is within a second other range, and a mode selection circuit responsive to a signal from the decision circuit for enabling the first circuit when first mode is selected and other than the first circuit when the second mode is selected.

In accordance with another embodiment of the invention there is provided a computer readable medium having stored therein data according to a predetermined computing device format, and upon execution of the data by a suitable computing device a design procedure for providing a design of an integrated circuit is provided. The integrated circuit comprising a first circuit, a second circuit, a package pin, the package pin for receiving a power supply signal other than ground, a decision circuit, and a mode selection circuit. The decision circuit electrically coupled to the package pin and responsive to a characteristic of the power supply signal, selecting a first mode when the characteristic is within a first range and a second mode when the characteristic is within a second range, and the mode selection circuit responsive to a signal from the decision circuit for enabling the first circuit when first mode selected and other than the first circuit when the second mode selected.

BRIEF DESCRIPTION OF THE DRAWINGS

Exemplary embodiments of the invention will now be described in conjunction with the following drawings, in which:

Fig. IA is a photograph of a typical PC motherboard showing the multiple insertion points for RAM memory modules.

Fig. IB is a photograph of a standard DRAM memory module fitting the multiple insertion points for RAM memory modules on the PC motherboard of Fig. 1.

Fig. 2 illustrates the standard 2- wire communications from the SPD circuit to the RAM memory modules. Fig. 3 illustrates schematically an exemplary embodiment of the invention within a combined SPD and temperature sensor IC.

Fig. 4 illustrates schematically an exemplary embodiment of the invention.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

Fig. IA is a photograph of a typical PC motherboard 100 showing multiple insertion points for RAM memory modules. A 184-pin DIMM socket 170 is provided, being one of four in the PC motherboard shown. Key elements to the 184-pin DIMM socket 170 are the first contact section 170, the central ridge 172 and the second contact section 173. The first and second contact sections 170 and 173 provide electrical contact to the 184 pads on the RAM memory module 160, shown in Fig. 2, when inserted into the 184-pin DIMM socket 170. The single central ridge 172 prevents incorrect insertion of other RAM memory modules.

It would be apparent to one skilled in the art that the replacement of the 184-pin DIMM socket 170 with other sockets supporting different memory modules is possible. As a result the PC motherboard 100 supports many different memory formats, physical sizes and memory capacities disposed within DIMMs. It is this configurability that lends complexity to the microcomputer and originally triggered the development of parallel presence detect, which was replaced by SPD.

Fig. IB is a photograph of a standard DRAM memory module 160 fitting the 184-pin DIMM socket 170 of the PC motherboard 100 of Fig. 1. As shown the standard DRAM memory module 160 comprises a circuit board 165 onto which a number of surface mount memory chips 161 are mounted and electrically interconnected. There are 8 surface mount memory chips 161 shown, though other numbers of memory chips are also possible. If each surface mount memory chip 161 is individually 128k then the standard DRAM memory module 160 provides 1024k (1Mb) of RAM memory for the microcomputer. If each surface mount memory chip 161 is 256k then the standard DRAM memory module 160 provides 2048k (2Mb) of RAM and so forth. Alternatively, the memory chips are other than surface mount memory chips. Also shown are first electrical contact 162, which is an array of 52 pads on each side of the circuit 165, and second electrical contact 163, which is an array of 40 pads on each side of the circuit 165. As such each side of the circuit 165 provides 92 pads, such that overall the circuit 165 has 184 pads to match the 184 contact pins in the 184-pin DIMM socket 170 of Fig. 1. Also shown is the slot 164 within the circuit 165, which matches the position and depth of the single central ridge 172 of the 184-pin DIMM socket 170 of Fig. 1. It is apparent to one skilled in the art that as semiconductor manufacturing processes improve capacity of each memory IC assembled within each surface mount memory chip 161 is optionally increased. Hence, RAM modules have expanded from several KB to many MB over the years.

Fig. 2 illustrates standard 2- wire communications from SPD circuit 220 to RAM memory modules 201 through 208. The SPD circuit 220 forms a single 6 or 8-pin surface mount package with a footprint of 2-3mm on each side. As such it forms a very small element of the PC motherboard 100 of Fig. 1, which being an industry standard ATX design has dimensions 295mm by 244mm (11.6" by 9.6") and is generally double side populated with electronics. As such the SPD circuit 220 forms about 0.01% of the ATX PC motherboard 100 footprint but without it the board cannot function. Alternatively, the SPD circuit is in another form factor.

The SPD circuit 220 operates using the Inter- Integrated Circuit (I2C) 2- wire bus interface standard and hence has clock and data ports 221 and 222 respectively providing I2C signaling to the RAM memory modules 201 through 208. The RAM memory modules 201 through 207 comply with the Joint Electron Device Engineering Council (JEDEC) standard, which requires certain parameters to be placed in the lower 128 bytes of the Electrically Erasable Programmable Read-Only Memory (EEPROM) located on each of the RAM memory modules 201 through 207. These bytes include timing parameters, manufacturer, serial number, and other useful information about the module. The JEDEC standard also denotes which two contacts of the RAM memory modules 201 through 207 are employed for SPD communications. The I2C Communications from the SPD circuit 220 comprise a serial signal clock (SCL) provided from the clock port 221 and a serial data input / output bus (SDA) electrically connected to the data port 222. The SCL is communicated to each of the RAM memory modules 201 through 207 via a first contact, which for simplicity is shown only for the first and second memory modules 201 and 202, respectively. As such, the SCL signal is provided to the ports 201a and 202a of the first and second memory modules 201 and 202, respectively. Equally the SDA is provided to the ports 201b and 202b of the first and second memory modules 201 and 202, respectively. Each of the SCL and SDA lines are connected via load resistors 21 lto a power supply VDD at terminations 231 and 232, respectively. The address of each RAM memory module 201 through 208 is established by connecting three address pins, SAO 201c and 202c, SAl 201d and 202d, and SA2 20 Ie and 202e to either a power supply rail V_DD or ground. As such the addresses for the RAM memory modules shown n Table 1.

Table 1

In operation each RAM memory module 201 through 20 has a DIMM position established by the 184-pin DIMM socket 170 it is inserted into on the PC motherboard 100. The SPD circuit 220 then communicates with each RAM memory module 201 through 207 and extracts memory data therefrom. The memory data typically comprises 255 bytes of data of which exemplary bytes are shown in Table 2.

0 Defines number of bytes written into serial memory by manufacturer

Table 2

Fig. 3 illustrates schematically an exemplary embodiment of the invention within a combined I2C SPD and temperature sensor IC 300. Shown is a surface mount 8-pin package variant of the packaging for a combined SPD and temperature sensor IC 300. Shown within the combined SPD and temperature sensor IC 300 is the ΣΛ temperature sensor 302 including bias circuit 302a, band gap reference circuit 302b, oscillator 302c, and power-on reset circuit 302d, all of which are coupled with ΣΛ modulator 302e. An output signal from the ΣΛ modulator 302e is provided to an 11-bit analog-to-digital converter 303. In operation the ΣΛ temperature sensor 302 continuously monitors and updates its temperature readings, the readings then converted to digital data and transferred to the data temperature register 304 where the data is stored in an 11-bit 2's complement format.

The digital data stored within the data temperature register 304 are read by control logic block 305 and fed to a data register block 307 wherein the temperature data extracted from the data temperature register 304 is compared with critical temperature using the critical register 307a, over temperature with the over register 307b, and under temperature with the under register 307c. Additionally the data register block 307 has a configuration block 307e and a security lock 307f. The results from the register comparisons are returned to the control logic block 305, and are optionally provided as decision data through the control I2C bus of the SPD and temperature sensor IC 300, which is implemented with bit AO being presented at pin 300a, bit Al being presented at pin 300b, and bit A2 being presented at pin 300c.

Additionally the control logic block 305 presents an event output signal at pin 30Of, which is provided via driver 308. According to the control logic block 305 decision the event output signal at pin 30Of is optionally used as an on / off switching signal such as for a fan or as an interrupt to a host. Finally, the control loop for the temperature segment of the SPD and temperature sensor IC 300 employs an SPD power management circuit 301 which communicates to / from the central logic block 305 and enables / disables the oscillator 302c and the band gap reference circuit 302b portions of the ΣΛ temperature sensor 302 as well as the power-on reset circuit 302d.

In operation the SPD power management circuit 301 determines a mode of operation of the combined SPD and temperature sensor IC 300 and allows it to manage power consumption based upon the operation of the control functions in two modes, an SPD only mode, and an SPD with temperature sensor. Within the SPD only mode, the SPD power management circuit 301 disables the oscillator 302c and band gap reference circuit 302b portions of the ΣΛ temperature sensor 302. Power dissipation in the exemplary circuit is mainly due to the on chip oscillator, which is solely used for temperature conversions and the associated bandgap circuitry. Lower power consumption of the combined SPD and temperature sensor IC 300 is achieved by turning off these elements.

When the combined SPD and temperature sensor IC 300 is operating in the SPD with temperature sensor mode the SPD power management circuit 301 enables the oscillator 302c and band gap reference circuit 302b portions of the ΣΛ temperature sensor 302. As shown in Fig. 4, the decision for which mode to operate the combined SPD and temperature sensor IC 300 in is optionally established from a simple adjustment of the power supply V_DD connection through pin 30Oe. This removes the requirements for controlling the combined SPD and temperature sensor IC 300 through its I2C control bus as implemented through bits AO, Al, and A2 which are presented at pins 300a, 300b, and 300c, respectively. The control logic block 305 also controls the SPD functions of the SPD and temperature sensor IC 300. The control block 305 communicates with the 2-wire I2C interface 306, which receives the serial signal clock (SCL) coupled at the SCL port, pin 30Oh. Received data in respect of memory modules is optionally stored within an EEPROM 312 before being transmitted through the control I2C bus of the SPD and temperature sensor IC 300 as implemented through bits AO, Al, and A2 which are presented at pins 300a, 300b, and 300c, respectively.

As shown, a part of the EEPROM 312, reserved memory 312a, is write-protected in the control software allowing it to be configured as permanent or reversible write -protect memory for storing data. It would be apparent to one skilled in the art that such data optionally include the settings for the critical register 307a, over register 307b, and under register 307c, as well as device identity, and settings for configurable hysteresis. The final two pins of the SPD and temperature sensor IC 300, which have not been outlined so far, are the Y_ss connection through pin 30Od, typically ground, and V_DD connection through pin 30Oe.

The optional storage of the received memory module data is optionally stored within the EEPROM 312 when the combined SPD and temperature sensor IC 300 is operating at a power supply voltage V_DD, as applied at pin 30Oe, that supports both read and write operations into the EEPROM 312. At lower power supply voltages the combined SPD and temperature sensor IC 300 supports only read operations from the EEPROM 312.

Hence, configuration settings are extractable from the EEPROM 312 by the central logic block 305 allowing operation of the combined SPD and temperature sensor IC 300 as designed in an SPD only mode, but not allowing a write operation into the EEPROM 312. When such write operations into the EEPROM 312 are enabled the EEPROM 312 allows storage of memory module data and temperature events.

The power consumption reduction when operating the combined SPD and temperature sensor IC 300 as outlined in the exemplary embodiment in an SPD only mode is optionally achieved by other adjustments to the operating conditions of circuit elements. Examples include but are not limited to adding other circuit functional blocks into the powered off state, such as data register block 307, 11-bit analog-to-digital converter 303, and data temperature register 304, and setting the oscillator to a lower operating frequency rather than being powered off.

Fig. 4 illustrates schematically an exemplary embodiment of the SPD power management circuit 400, being equivalent to the SPD power management circuit 301 of Fig. 3. As discussed previously with reference to Fig. 3 the SPD power management circuit 400 determines which mode the chip operates in, namely SPD only or SPD plus temperature sensor. The SPD power management circuit 400 comprises a voltage detection circuit 401 that determines whether the voltage level of the chip as provided to the voltage monitoring port 400a exceeds a predetermined amplitude or not. Consider an exemplary combined SPD and temperature sensor IC circuit 300 wherein the EEPROM supports read operations over a power supply range of 1.7V and 3.6V, write operations in 3.0V to 3.6V range, and that the oscillator 302c and bandgap circuit 302b require a power range of 3.0V to 3.6V. Hence, at a power supply threshold of say 2.6V a decision is made as to mode of the combined SPD and temperature sensor IC circuit 300. Below 2.6V the combined SPD and temperature sensor IC circuit 300 operates solely as an SPD, and above 2.6V as a combined temperature sensor and SPD. As outlined previously if the power supply voltage is below 2.6V then the EEPROM 312 still supports read operations allowing correct operation of the combined SPD and temperature sensor IC circuit 300, and at higher voltages than 2.6V the EEPROM 312 would support write operations allowing the storage of temperature events, as well as memory module data. Optionally, other voltage amplitudes form the threshold for determining a mode of operation. Further optionally, other parameters of the signal are used to determine a mode of operation.

Hence, the voltage detection circuit 401 determines the voltage level and provides a digital signal (Temp_Vd). In the exemplary embodiment Temp_Vd is LOW when the voltage is below 2.6V, and the combined SPD and temperature sensor IC circuit 300 operating in SPD only mode, and HIGH if the voltage is above 2.6V and the combined SPD and temperature sensor IC circuit 300 will be operating in combined temperature sensor and SPD mode. The elapsed time circuit 402 keeps track of elapsed time since a Power On Reset (POR) event occurred. The POR event is communicated to the elapsed time circuit 402 from the central logic block 305 through POR port 400c. The elapsed time circuit outputs a digital signal Steady_Temp, which is HIGH if a certain predetermined amount of time has elapsed since the chip came out of a reset as triggered from an external controller via the control I2C bus of the combined SPD and temperature sensor 300 to the central logic block 305. The Steady_Temp signal will be LOW when the elapsed amount of time is less than the predetermined amount of time. In this embodiment the elapsed time circuit 402 includes a counter circuit. For example, the predetermined amount of time is set to 30ms, and hence from a POR event the signal Steady_Temp is LOW for 30ms, and then transitions to HIGH.

Alternatively, the predetermined amount of time is different from 30ms. Further alternatively, the predetermined amount of time is adjustable depending upon a ramp time needed for the application within which the combined SPD and temperature sensor 300 is operating. In addition by programming the counter value in the EEPROM 312 the ramp time becomes programmable and accommodates different ramp rates. Optionally, the ramp time is established from electrical and thermal characteristics of the remaining circuitry within which the combined SPD and temperature sensor 300 is deployed.

The Steady_Temp and Temp_Vd signals are provided to a decision circuit 403. Based upon these signals, the decision circuit 403 provides a temperature mode signal Temp_Mode for determining whether to turn ON or turn OFF the elements of the combined SPD and temperature sensor IC 300 such as the oscillator 302c and band gap reference circuit 302b.

When the decision circuit 403 is implemented according to the exemplary embodiment such that Temp_Mode is only established after Steady_Temp has gone HIGH, the two signals are under different voltage and elapsed time since a POR event. This prevents initiating either mode during a period of time after a POR event wherein the voltage levels within the circuit are not fully established but ramping that would lead to erroneous states within the process. As such the decision circuit 403 provides a decision process such that only when Steady_Temp is HIGH that the output of the analog circuit 401 is looked at. If the output signal Temp_Vd of the analog circuit 401 is HIGH then the combined SPD and temperature sensor IC 300 is operating in combined mode and hence the oscillator 302c and band gap reference circuit 302b are enabled and powered. If Temp_Vd is LOW then the combined SPD and temperature sensor IC 300 is operating in SPD only mode and the oscillator 302c and band gap reference circuit 302b are disabled and powered off.

The exemplary embodiment supports use of a combined SPD and temperature sensor IC within SPD only applications without high power consumption. Further the invention avoids any software changes and is quite flexible and adaptable to different ramp rates allowing its operation to be completely transparent to the user.

Numerous other embodiments may be envisaged without departing from the scope of the invention.

Claims

CLAIMS:

1. A method comprising; providing a circuit with two modes of operation, the circuit comprising a first circuit and second circuit; providing a power supply signal; the power supply signal being other than ground; enabling the first mode of operation when the power supply signal has a first characteristic; and enabling the second mode of operation when the power supply signal has a second characteristic.

2. A method according to claim 1 wherein; enabling the first mode of operation comprises enabling the first circuit; enabling the second mode of operation comprises disabling the first circuit.

3. A method according to claim 1 wherein; the first characteristic is when the power supply is within a first range.

4. A method according to claim 3 wherein; the second characteristic is when the power supply is outside the first range and within a second range.

5. A method according to claim 1 wherein the first circuit comprises a temperature measurement circuit.

6. A method according to claim 1 wherein the second circuit comprises a digital communications circuit according to at least one of an Inter- Integrated Circuit interface, a Universal Serial Bus, a System Management Bus, PMCIA, physcial Ethernet, wireless Ethernet, PCI, SCI, SCSI, IEEE 488, and SPI.

7. A method according to claim 6 wherein the digital communications circuit comprises an Inter-Integrated Circuit interface circuit.

8. A method according to claim 6 wherein the digital communications circuit comprises a circuit for providing serial presence detect to at least a memory circuit.

9. A method according to claim 1 comprising waiting for a predetermined period of time upon detecting a power on reset of the circuit before enabling at least one of the first mode and enabling the second mode of operation

10. A method according to claim 1 further comprising: providing a memory circuit, the memory circuit for storing data at least one of required by and obtained by the circuit, and electrically coupled to the circuit.

11. A method according to claim 10 wherein enabling one of the first mode and the second mode comprises providing read access to the data and write access to the data.

12. An integrated circuit comprising: a first circuit; a second circuit; a package pin, the package pin for receiving a power supply signal other than ground; a decision circuit, the decision circuit electrically coupled to the package pin and responsive to a characteristic of the power supply signal, and for selecting a first mode when the characteristic is within a first range and a second mode when the characteristic is within a second other range; and a mode selection circuit responsive to a signal from the decision circuit for enabling the first circuit when first mode is selected and other than the first circuit when the second mode is selected.

13. An integrated circuit according to claim 12 wherein; the integrated circuit comprises at least one of a packaged hybrid integrated circuit and a monolithic integrated circuit.

14. An integrated circuit according to claim 12 wherein, the integrated circuit comprises a semiconductor circuit manufactured using a semiconductor technology based upon at least one of silicon, silicon-germanium, gallium arsenide, indium phosphide, gallium nitride and polymers.

15. An integrated circuit according to claim 12 wherein; the first circuit provides temperature measurement.

16. An integrated circuit according to claim 12 wherein; the second circuit provides digital communications according to at least one of an Inter- Integrated Circuit interface, a Universal Serial Bus, a System Management Bus, PMCIA, physcial Ethernet, wireless Ethernet, PCI, SCI, SCSI, IEEE 488, and SPI.

17. An integrated circuit according to claim 16 wherein, the second circuit provides serial presence detect to at least a memory circuit.

18. An integrated circuit according to claim 12 wherein; the second circuit provides digital communications according to the Inter- Integrated Circuit interface.

19. An integrated circuit according to claim 18 wherein, the second circuit provides serial presence detect to at least a memory circuit.

20. An integrated circuit to claim 12 wherein, the decision circuit further comprises a delay circuit, the delay circuit for delaying the selection of the one of first mode and second mode.

21. An integrated circuit to claim 20 wherein, the delay provided by the delay circuit is a predetermined period of time from a detection of a power on reset to the circuit.

22. An integrated circuit according to claim 12 further comprising: a memory circuit, the memory circuit electrically coupled to at least one of the first circuit and second circuit, the memory circuit for storing data, the data at least one of required by and obtained by at least one of the first circuit and second circuit.

23. An integrated circuit according to claim 22 wherein, the memory supports read access and write access in the first mode of operation and read access in a second mode of operation.

24. An integrated circuit according to claim 12 wherein, the circuit is shut down after a predetermined period of time in the first mode of operation and is maintained operating in the second mode of operation.

25. A computer readable medium having stored therein data according to a predetermined computing device format, and upon execution of the data by a suitable computing device a design procedure for providing a design of an integrated circuit is provided, comprising: a first circuit; a second circuit; a package pin, the package pin for receiving a power supply signal other than ground; a decision circuit, the decision circuit electrically coupled to the package pin and responsive to a characteristic of the power supply signal, selecting a first mode when the characteristic is within a first range and a second mode when the characteristic is within a second range; and a mode selection circuit responsive to a signal from the decision circuit for enabling the first circuit when first mode selected and other than the first circuit when the second mode selected.

26. A computer readable medium according to claim 25 wherein; the design of the integrated circuit further comprises; a memory circuit, the memory circuit electrically coupled to at least one of the first circuit and second circuit, the memory circuit for storing data, the data at least one of required by and obtained by at least one of the first circuit and second circuit.