DESCRIPTION
SOURCE AND DRAIN FORMATION
The invention relates to a method of source and drain formation, and particularly but not exclusively to a method of source and drain formation on thin body silicon devices, as well as devices thus formed.
Thin body silicon on insulator type devices typically include a thin silicon layer over an insulating layer, often a buried oxide (BOX) layer, which in turn is provided on a substrate typically of silicon. Field effect transistors (FETs) are formed using the thin silicon layer as the channel region.
The advantage of using thin silicon layers is that the depletion region can extend throughout the entire thickness of the silicon film; such transistors can be referred to as fully-depleted Metal Oxide Semiconductor FETs
(MOSFETs). Devices with thin channels can deliver improved performance, including reduced short-channel effects, and high current, especially for
MOSFETs with short gates below 100nm. Such devices are typically used for complementary MOS (CMOS) devices with both n-type and p-type transistors. FETs need sources and drains which are heavily doped. Such sources and drains are typically formed by implanting dopants into the thin silicon layer.
However, such processes normally require thermal annealing to activate the dopants and this can cause problems with short gate devices since the dopants can laterally diffuse under the gate. The formation of suicides on ultra-thin silicon layers can also be rather difficult since there may not be sufficient silicon to convert into a sufficient thickness of suicide for sufficiently low contact resistance.
As a result of these difficulties, some relatively complex approaches to forming FETs on thin silicon layers have been proposed. One approach is to form raised source and drains. US2005/0040465 describes one such approach in which a thick polysilicon layer is deposited after implanting dopants to form n-type and p-type sources and drains after forming a gate stack. A chemical mechanical polishing (CMP) step is used to expose the top of the gate stack, and then dopants are implanted into the top of the gate stack and the top of the thick polysilicon layer. The thick polysilicon layer thus absorbs the dopants and prevents the implantation into the top of the gate stack doping also the sources and drains.
Most of the thick polysilicon layer is then removed, leaving a thinner layer on the source and drain. This thinner layer was protected by the upper part of the thick polysilicon layer and so will not have been doped by the gate stack implantation. This thinner layer is then doped. The structure is then annealed. A silicidation step then takes place.
The approach forms a raised source and drain without forming it from the thin silicon layer.
According to the invention there is provided a method of manufacturing a semiconductor device according to claim 1.
The approach may result in highly activated dopants forming the source and drain regions and a low contact resistance, using a method that is relatively straightforward to carry out.
The approach of the invention differs considerably from that presented in US2005/0040605. In that prior approach, a thick semiconductor layer is deposited over the whole surface and doped by implantation. The implantation is intended to dope the polysilicon gate and the semiconductor layer is a buffer which ensures that the source and drain are not affected by this implantation. For this reason, the implantation does not reach the lower part of the thick semiconductor layer and the doped part of the thick semiconductor layer is removed. Thus, additional doping steps are required in the method according to US 2005/0040605 to dope the source and drain regions n-type or p-type and these additional doping steps are avoided in the present invention. The step of removing all or part of the doped donor layer may be a chemical mechanical polishing step removing the donor layer from the top of the gate structure leaving at least a part of the doped donor layer over the semiconductor epilayer.
The method is particularly useful for forming thin semiconductor devices. In particularly preferred embodiments, the step of providing a semiconductor channel layer includes providing the semiconductor channel layer above an insulating layer on a substrate.
In embodiments, the method may further include depositing a metal precursor layer over the doped donor layer over the doped sources and drains and carrying out an annealing step to react the metal precursor layer with the doped donor layer to form suicide on the sources and drains.
In advantageous embodiments, only one single annealing step is carried out to react the metal precursor layer and to diffuse the dopants from the doped donor layer. In alternative embodiments, the step of removing all or part of the doped donor layer is carried out after annealing the device to diffuse the dopants.
The method may also include implanting source and drain extension implants after forming the gate structure; and forming spacers on the sides of the gate structure over at least part of the extension implants before forming the doped donor layer. In this way the step of annealing the device to diffuse the dopants forms heavily doped regions under the doped donor layer but not under the spacers leaving the extension implants under the spacers defining source and drain extension regions between the heavily doped regions and the gate, the heavily doped regions being more heavily doped than the extension regions. A channel region is formed in the semiconductor channel layer between the extension regions. Thus, heavily and lightly doped source and drain regions are readily formed.
The step of forming a doped donor layer of polysilicon or amorphous silicon over the whole surface including the gate structure and the semiconductor epilayer adjacent to the gate structure may be carried out by depositing polysilicon or amorphous silicon over the whole surface and implanting the polysilicon or amorphous silicon with an implant dose. One approach to forming the gate structure includes depositing gate- forming layers to form a gate structure; depositing a hard mask over the gate- forming layers; and patterning the gate-forming layers using the hard mask.
The invention is applicable to the manufacture of CMOS devices. In one approach for forming both n-type and p-type transistors, the step of forming the doped donor layer includes: depositing a layer of polysilicon or amorphous silicon over the whole surface including the gate structures; carrying out a n-type implantation step to dope the layer of polysilicon or amorphous silicon n-type in n-type regions; and carrying out a p-type implantation step to dope the layer of polysilicon or amorphous silicon p-type in p-type regions to form the doped donor layer having both n-type and p-type regions to form n-type and p-type transistors in the respective n-type and p-type regions. Note that the n-type and p-type implantation steps may be carried out in either order.
Embodiments of the invention will now be described with reference to the accompanying drawings, in which: Figures 1 to 8 represent steps in a method according to a first embodiment of the invention;
Figure 9 illustrates an alternative step used in a method according to a second embodiment of the invention; and
Figure 10 illustrates a step of a third embodiment of the invention. The figures are schematic and not to scale, and like components are given like reference numerals in different figures.
A specific embodiment of the invention will now be described with reference to Figures 1 to 8 which illustrates the formation of a single n-type transistor using a method according to the invention.
Referring to Figure 1 , a silicon substrate 2 has a buried oxide layer 4 and a thin silicon epilayer 6 formed on top of the buried oxide layer. The thin silicon epilayer 6 may have a thickness of 10nm to 1000nm. The epilayer 6 will also be referred to as a channel layer since it forms the channel in the device. In this context, the word "channel" is intended as a label without implying any particular properties of the layer other than that it can be used to form the channel in the finished device.
Referring to Figure 2, a gate structure 10 is then formed on the silicon layer. In the embodiment shown, a gate dielectric 12 is deposited on thin silicon epilayer 6. The gate dielectric 12 may, for example, be of silicon dioxide, silicon nitride, oxynitride, silicates, or other suitable materials including for example high-k dielectric. A gate conductor layer 16, for example of doped polysilicon, is then formed. The gate insulation layers 12 and gate layers 16 are gate-forming layers.
A hard mask layer, for example of tetraethylorthosilicate (TEOS), is then deposited and patterned to form a hard mask 18. The hard mask 18 is then used as a mask to etch the gate structure 10 to arrive at the gate structure 10 as shown in Figure 2.
It will be appreciated by those skilled in the art that there are many different materials and processes that may be used to form gate structures and such alternatives may also be adopted. An extension doping step is then carried out, as illustrated in Figure 3, using n-type dopants at a low doping level to form extension doping regions (previously known as low doped drain or low doped source regions) in the finished device. The doping step forms lightly doped regions 20 adjacent to the gate structure 10, leaving undoped a channel region 21 under the gate structure 10.
Referring to Figure 4, spacers 22 are then formed on the sidewalls of the gate structure 10 using known processes, for example the deposition of a spacer-forming layer over the whole substrate followed by an anisotropic etch. Next, a thick layer of polysilicon 24 is deposited over the whole surface, including both the gate structure 10, the spacers 22 and the lightly doped regions 20. In alternative embodiments, amorphous silicon can be used instead of polysilicon.
The thick layer of polysilicon 24 is then doped heavily n-type using an implantation step illustrated in Figure 5 as dopant implantation 25. For example, the layer may be doped in the range 1019 cm"3 to 1021 cm"3.
A chemical-mechanical polishing (CMP) step is then carried out as illustrated in Figure 6 to remove the excess of the thick layer of polysilicon 24. The step is carried out sufficiently to remove the whole of the hard mask layer 18 as well as the top of the spacers 22 and the upper part of the thick polysilicon layer 24 leaving heavily doped polysilicon regions 26 adjacent to the spacers 22 over part of the lightly doped regions 20.
A metal 28 is then deposited over the heavily doped polysilicon regions 26 as illustrated in Figure 7. The metal is chosen to form a suicide with the heavily doped polysilicon regions 26 in the next step, and may be for example W, Ti, Ta, Co, Ni, Pr, Er, Y or combinations thereof, such as NiPt.
A single annealing step is then carried out as illustrated in Figure 8. This single annealing step reacts the metal 28 with the heavily doped polysilicon regions 26 to form suicide sources and drains 30.
During this process, the dopants in the heavily doped polysilicon regions 26 diffuse into the lightly doped regions 20 formed in the silicon epilayer 6. This creates heavily doped source and drain regions 32. Note that since the dopants preferentially remain in the silicon instead of being incorporated into the suicide, the formation of the suicide 30 drives the dopants into the lightly doped regions 20 to form the heavily doped source and drain regions 32, using what may be described as a "snowplough" effect.
Under the spacer 22, the lightly doped region 20 remains forming lightly doped extension region 34.
The annealing step does not just diffuse the dopants to form the heavily doped source and drain regions 32, but also activates the dopants. This results in the structure shown in Figure 8. The method allows the formation of the heavily doped regions 32 in the thin epilayer 6 very easily without requiring selective epitaxial growth. Further, the resulting structure can have a low contact resistance. The dopants in the heavily doped regions 32 are highly activated.
The single annealing step used in this embodiment reduces the number of annealing steps required. However, in an alternative embodiment, illustrated in Figure 9, a further annealing step is inserted either before or after the CMP step illustrated in Figure 6. Figure 9 illustrates this step taking place after the implantation step illustrated in Figure 5 and before the CMP step of Figure 6.
This additional anneal diffuses the dopants from the heavily doped thick polysilicon layer 24 into the lightly doped regions 20 to form the heavily doped regions 32 and hence define also the more lightly doped extension regions 34 at this earlier stage. This allows one step annealing parameters to be used for this diffusion step and a different set of annealing parameters to be used in the later silicidation step. The above method steps describe the formation of an n-type transistor but it will be appreciated that the invention is equally applicable to the formation of a p-type transistor using p-type implantations instead of n-type.
In an alternative embodiment (not shown) the metal 28 is also deposited on the gate conductor layer 16 in order to fully suicide the gate during the subsequent annealing step.
It will be appreciated by those skilled in the art that the method according to the invention may be used to form complementary metal oxide semiconductor devices with both p-type and n-type transistors. In this case, the step of forming the doped polysilicon layer 24 includes depositing the thick polysilicon layer, in a lightly doped or undoped form, over the whole of the surface. Then, the doped polysilicon layer is heavily doped p-type in p-type regions 40 and n-type in n-type regions 42 in separate implantation steps that may occur in either order. Figure 10 illustrates the doping of the p-type region 40 p-type. In the subsequent annealing step, the n-type and p-type regions of the heavily doped p-type layer form n-type and p-type transistors respectively. It will be appreciated that a similar pair of implantation steps is required to dope the extension regions 20 in the n-type and p-type regions.
Those skilled in the art will realise that many alternatives are possible to the above specific embodiment. For example, the semiconductor epilayer 6 is described above to be of silicon but alternatives are possible, for example a silicon-germanium epilayer 6 may be used instead.
Although the above embodiments describe forming the structure on a semiconductor epilayer 6, the epilayer may be replaced by other layers for example a polysilicon layer or an amorphous silicon layer. Either the polysilicon layer or amorphous silicon layer may be crystallised later in the process. The polysilicon layer or amorphous silicon layer can be formed over the insulating layer 4.
In alternative embodiments, the process is used to form a transistor in a bulk device including a bulk layer.
The insulating layer 4 is described to be a BOX layer but in alternative embodiments alternative silicon on insulator technologies may be used.
The doping levels of the implantation steps may be adjusted to achieve the required doping levels in the finished structure. The embodiments described use polysilicon as the thick layer 24 but amorphous silicon may be used if required.
Alternative materials may be used in the gate structure and elsewhere as required by the particular application or process used.