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WO2007076451A3 - Body effect sensing method for non-volatile memories - Google Patents

Body effect sensing method for non-volatile memories
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Publication number
WO2007076451A3
WO2007076451A3PCT/US2006/062513US2006062513WWO2007076451A3WO 2007076451 A3WO2007076451 A3WO 2007076451A3US 2006062513 WUS2006062513 WUS 2006062513WWO 2007076451 A3WO2007076451 A3WO 2007076451A3
Authority
WO
WIPO (PCT)
Prior art keywords
bit line
cell
voltage
body effect
shut
Prior art date
Application number
PCT/US2006/062513
Other languages
French (fr)
Other versions
WO2007076451A2 (en
Inventor
Nima Mokhlesi
Jeffrey W Lutze
Original Assignee
Sandisk Corp
Nima Mokhlesi
Jeffrey W Lutze
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/321,996external-prioritypatent/US7349264B2/en
Priority claimed from US11/320,917external-prioritypatent/US7616481B2/en
Application filed by Sandisk Corp, Nima Mokhlesi, Jeffrey W LutzefiledCriticalSandisk Corp
Priority to KR1020087015402ApriorityCriticalpatent/KR101357068B1/en
Priority to CN2006800494908Aprioritypatent/CN101351847B/en
Priority to EP06848820Aprioritypatent/EP1966800A2/en
Priority to JP2008548823Aprioritypatent/JP4568365B2/en
Publication of WO2007076451A2publicationCriticalpatent/WO2007076451A2/en
Publication of WO2007076451A3publicationCriticalpatent/WO2007076451A3/en

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Abstract

The present invention presents a scheme for sensing memory cells. Selected memory cells are discharged through their channels to ground and then have a voltage level placed on the traditional source and another voltage level placed on the control gate, and allowing the cell bit line to charge up. The bit line of the memory cell will then charge up until the bit line voltage becomes sufficiently high to shut off any further cell conduction. The rise of the bit line voltage will occur at a rate and to a level dependent upon the data state of the cell, and the cell will then shut off when the bit line reaches a high enough level such that the body effect affected memory cell threshold is reached, at which point the current essentially shuts off. A particular embodiment performs multiple such sensing sub-operations, each with a different control gate voltage, but with multiple states being sensed in each operation by charging the previously discharged cells up through their source.
PCT/US2006/0625132005-12-282006-12-21Body effect sensing method for non-volatile memoriesWO2007076451A2 (en)

Priority Applications (4)

Application NumberPriority DateFiling DateTitle
KR1020087015402AKR101357068B1 (en)2005-12-282006-12-21Body effect sensing method for non-volatile memories
CN2006800494908ACN101351847B (en)2005-12-282006-12-21Alternate sensing techniques for non-volatile memory
EP06848820AEP1966800A2 (en)2005-12-282006-12-21Body effect sensing method for non-volatile memories
JP2008548823AJP4568365B2 (en)2005-12-282006-12-21 Alternative sensing technology for non-volatile memory

Applications Claiming Priority (4)

Application NumberPriority DateFiling DateTitle
US11/320,9172005-12-28
US11/321,9962005-12-28
US11/321,996US7349264B2 (en)2005-12-282005-12-28Alternate sensing techniques for non-volatile memories
US11/320,917US7616481B2 (en)2005-12-282005-12-28Memories with alternate sensing techniques

Publications (2)

Publication NumberPublication Date
WO2007076451A2 WO2007076451A2 (en)2007-07-05
WO2007076451A3true WO2007076451A3 (en)2007-09-20

Family

ID=38197637

Family Applications (1)

Application NumberTitlePriority DateFiling Date
PCT/US2006/062513WO2007076451A2 (en)2005-12-282006-12-21Body effect sensing method for non-volatile memories

Country Status (5)

CountryLink
EP (1)EP1966800A2 (en)
JP (1)JP4568365B2 (en)
KR (1)KR101357068B1 (en)
TW (1)TWI323464B (en)
WO (1)WO2007076451A2 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
US7616481B2 (en)2005-12-282009-11-10Sandisk CorporationMemories with alternate sensing techniques
US7349264B2 (en)2005-12-282008-03-25Sandisk CorporationAlternate sensing techniques for non-volatile memories
KR100923810B1 (en)*2007-02-222009-10-27주식회사 하이닉스반도체Memory device and method of operating the same
US8416624B2 (en)2010-05-212013-04-09SanDisk Technologies, Inc.Erase and programming techniques to reduce the widening of state distributions in non-volatile memories
JP2014199708A (en)*2013-03-142014-10-23株式会社半導体エネルギー研究所Method for driving semiconductor device
US11049557B2 (en)*2019-07-192021-06-29Macronix International Co., Ltd.Leakage current compensation in crossbar array
WO2022155766A1 (en)*2021-01-192022-07-28Yangtze Memory Technologies Co., Ltd.Semiconductor memory device

Citations (6)

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Publication numberPriority datePublication dateAssigneeTitle
EP0673037A1 (en)*1994-03-151995-09-20Kabushiki Kaisha ToshibaNon-volatile semiconductor memory device
US5570315A (en)*1993-09-211996-10-29Kabushiki Kaisha ToshibaMulti-state EEPROM having write-verify control circuit
US5602789A (en)*1991-03-121997-02-11Kabushiki Kaisha ToshibaElectrically erasable and programmable non-volatile and multi-level memory systemn with write-verify controller
US6259627B1 (en)*2000-01-272001-07-10Multi Level Memory TechnologyRead and write operations using constant row line voltage and variable column line load
US20020101778A1 (en)*1995-10-062002-08-01Sakhawat M. KhanIntegrated circuit for storage and retrieval of multiple digital bits per nonvolatile memory cell
US20060291285A1 (en)*2003-02-062006-12-28Nima MokhlesiSystem and method for programming cells in non-volatile integrated memory devices

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
JPH08249893A (en)*1995-03-071996-09-27Toshiba Corp Semiconductor memory device
JP2697665B2 (en)*1995-03-311998-01-14日本電気株式会社 Semiconductor storage device and method of reading data from semiconductor storage device
JP4246831B2 (en)*1999-02-082009-04-02株式会社東芝 Data identification method for semiconductor integrated circuit device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
US5602789A (en)*1991-03-121997-02-11Kabushiki Kaisha ToshibaElectrically erasable and programmable non-volatile and multi-level memory systemn with write-verify controller
US5570315A (en)*1993-09-211996-10-29Kabushiki Kaisha ToshibaMulti-state EEPROM having write-verify control circuit
EP0673037A1 (en)*1994-03-151995-09-20Kabushiki Kaisha ToshibaNon-volatile semiconductor memory device
US20020101778A1 (en)*1995-10-062002-08-01Sakhawat M. KhanIntegrated circuit for storage and retrieval of multiple digital bits per nonvolatile memory cell
US6259627B1 (en)*2000-01-272001-07-10Multi Level Memory TechnologyRead and write operations using constant row line voltage and variable column line load
US20060291285A1 (en)*2003-02-062006-12-28Nima MokhlesiSystem and method for programming cells in non-volatile integrated memory devices

Also Published As

Publication numberPublication date
JP4568365B2 (en)2010-10-27
KR101357068B1 (en)2014-02-03
EP1966800A2 (en)2008-09-10
TW200741718A (en)2007-11-01
KR20080096644A (en)2008-10-31
TWI323464B (en)2010-04-11
WO2007076451A2 (en)2007-07-05
JP2009522706A (en)2009-06-11

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