WO2004008827A2 - Atomic layer deposition of high k dielectric films - Google Patents

Abstract

A method of processing a semiconductor substrate includes reacting in a reactor a first reactant gas, evacuating the first reactant gas from the reactor, reacting a second reactant gas, and evacuating the second reactant gas. The reacting of the first reactant gas reacts the first reactant gas with an exposed surface of the semiconductor substrate in a reactor to convert the exposed surface into a solid mono-layer. The reacting of the second reactant gas reacts the second reactant gas with the solid mono-layer in the reactor to convert the solid mono-layer into a gaseous compound. The evacuating of the second reactant gas also evacuates the gaseous compound from the reactor.

Description

ATOMIC LAYER DEPOSITION OF HIGH K DIELECTRIC FILMS

RELATED APPLICATIONS

This application claims the benefits of and priority to U.S. Provisional Application 60/396,723 filed July 19, 2002, and U.S. Provisional Application 60/396,745 filed July 19, 2002, both of which are hereby incoφorated by reference in their entirety.

This application is related to PCT Patent Application serial no. PCTUS03/19982 filed June 23, 2003 entitled Method and System for Atomic Layer Removal and Atomic Layer Exchange (Attorney Docket No. FP-71606-PC/MSS), which claims the benefit of U.S. Provisional patent application no. 60/391,011 filed June 23, 2002, the disclosure of all of which are hereby incorporated by reference in their entirety; and PCTUS03/19984 filed June 23, 2003 entitled Method For Energy- Assisted Atomic Layer Deposition and Removal (Attorney docket no. FP-71606-1- PC/MSS) which claims the benefit of U.S. Provisional patent application no. 60/391,012 filed June 23, 2002 and U.S. Provisional patent application no. 60/396,743 filed on July 19, 2002, the disclosures of all of which are hereby incorporated by reference in their entirety.

FIELD OF THE INVENTION

The present invention relates generally to the field of semiconductors. More specifically, the present invention relates to a process to form high dielectric constant gate and capacitor insulators using atomic layer deposition and removal processes. BACKGROUND OF THE INVENTION

Semiconductor devices of future generation require thin dielectric films for metal oxide silicon (MOS) transistor gates, and capacitor dielectrics. As oxide films are scaled down, the tunneling leakage current becomes significant and limits the useful range for gate oxides to about 1.8 nm or more.

High dielectric constant ("high-k") metal oxides have been considered as possible alternative materials to silicon oxide (having a dielectric constant k of about 3.9) to provide gate dielectrics with high capacitance but without compromising the leakage current. Metal oxides such as hafnium oxide (HfO₂ ) having a dielectric constant of about 20, zirconium oxide (ZrO₂ ) having a dielectric constant of about 20, and Hf and Zr silicates have been reported. However, prior art fabrication techniques such as chemical vapor deposition (CVD) are increasingly unable to meet the requirements of forming these advanced thin films. While CVD processes can be tailored to provide conformal films with improved step coverage, CVD processes often require high processing temperatures, result in incoφoration of high impurity concentrations, and have poor precursor or reactant utilization efficiency. For instance, one of the obstacles in fabricating high-k gate dielectrics is the formation of an interfacial silicon oxide layer during CVD processing as illustrated in FIG. 1. Interfacial oxide growth problems for gate and capacitor dielectric application have been widely reported in the industry. This problem has become one of the major hurdles for implementing high-k materials in advanced device fabrication. Another obstacle is the limitation of prior art CVD processes in depositing ultra thin (typically lOA or less) films for high-k gate dielectrics on a silicon substrate.

Atomic layer deposition (ALD) is an alternative to traditional CVD processes to deposit very thin films. ALD has several advantages over traditional CVD techniques. ALD can be performed at comparatively lower temperatures which is compatible with the industry's trend toward lower temperatures, has high precursor utilization efficiency, and can produce conformal thin film layers. More advantageously, ALD can control film thickness on an atomic scale, and can be used to "nano-engineer" complex thin films. Accordingly, further developments in ALD are highly desirable.

SUMMARY OF THE INVENTION Accordingly, it is a general object of the present invention to provide a method and system for making transistors of improved performance by forming films on semiconductor devices and wafers by atomic layer deposition and removal.

In general, a method of forming a high-k dielectric film on the surface of a substrate is provided, comprising: reacting a first reactant gas with an exposed surface of the semiconductor substrate in a reactor to convert the exposed surface into a solid mono-layer, evacuating the first reactant gas from the reactor, reacting a second reactant gas with the solid mono-layer in the reactor to convert the solid mono-layer into a gaseous compound, and evacuating the second reactant gas and the gaseous compound from the reactor. The exposed surface of the semiconductor substrate is comprised of a compound that is an oxide of any one of a metal, silicon, germanium, and a bi-element semiconductor formed from group III and group V.

In one aspect of the present invention the method comprises the following pulse cycles: a metal alkyl amide reactant is pulsed into the reaction chamber to form a non layer on the surface of the substrate. The reaction chamber is then purged of unreacted metal alkyl amides and by-products. Next, ozone gas is pulsed into the reaction chamber and reacts with the mono layer on the substrate to form a desired film or layer. Unreacted ozone and by-products are removed from the reaction chamber. The pulse cycle is repeated as many times as necessary to achieve the desired film thickness. In this embodiment the metal alkyl amide reactant is comprised of the formula:

M(NR R²)_n where M is a Group IV metal including but not limited to aluminum, hafnium, zirconium and titanium; n is 4; R¹ and R², independently, are selected from the group of alkyls where the alkyls may be substituted, unsubstituted, linear, branched and/or cyclic, hi one preferred embodiment, R and R are individually, a CI- C6 alkyl, such as methyl and ethyl, hi another preferred embodiment, the ligand (NR¹ R²) are ethylmethyl amides.

In another embodiment a first reactant gas is comprised a compound that is any one of water vapor, methanol, ethanol, propanol, and butanol; and the second reactant gas comprises a compound that is any one of C1F₃, BF₃, BC1₃, NF₃, NC1₃, HF, HC1, fluorine and chlorine. In yet another embodiment the first reactant gas comprises a compound that includes a hydroxyl group, and the second reactant gas comprises of a halogen containing compound. In still another embodiment, the first reactant gas is trimethyl aluminum (A1(CH₃)₃) and the second reactant is ozone (O₃). Additional gas reactants are suitable and include MPA (methylpyrrolidine alane); modified TMA

(methylpyrrolidine TMA, ethylpiperidine TMA); DMAH (dimethyl aluminum hydride, A1((CH₃)₂)H); modified DMAH (methylpyrrolidine dimethyl aluminum hydride, methylpiperidine dimethyl aluminum hydride, ethylpiperidine dimethyl aluminum hydride); TEMAT (Ti[N(CH₃)C₂H₅]₄); PEMAT (Ta[C₂H₅N(CH₃)]₅); TEMAHf (Hf[C₂H₅N(CH₃)]₄); TEMAZr (Zr[C₂H₅N(CH₃)]₄); TDMAHf (HfrN(CH₃)₂]₄); TDMAZr (Zr[N(CH₃)₂]₄); TDEAHf (HfIN(C₂H₅)₂]₄); TDMAZr (Zr[N(C₂H₅)₂]₄); cocktailed BST source (Ba(tetramethylheptanedionate)2,

Sr(tetramethylheptanedionate)2) and cocktailed STO source

(Sr(tetramethylheptanedionate)2, Ti(i-OPr)2(tetramethylheptanedionate)2). In another aspect of the invention, a structure includes a de-oxidized substrate formed by using atomic layer removal of at least one oxide mono-layer and a dielectric film formed by using atomic layer deposition of at least one dielectric mono-layer on the de-oxidized substrate.

In a further aspect of the present invention, a transistor device is provided comprised of a drain and a source formed in a substrate; a de-oxidized channel defined in the substrate between the drain and the source and formed by using atomic layer removal of at least one oxide mono-layer; and a gate dielectric formed by using atomic layer deposition of at least one dielectric mono-layer on the de-oxidized channel. The gate dielectric may include plural dielectric mono-layers, where each dielectric mono- layer comprises a compound that is any one of AI2O3, Tiθ2, H1O2, Ceθ2, Zrθ2, Ta2θ5 and an oxide of one of Li, Be, Na, Mg, K, Ca, Sc, V, Cr, Mn, Fe, Co, Ni, Cu,

Zn, Ga, Ge, Rb, Sr, Y, Nb, Mo, Tc, Pd, Ag, Cd, In, Sn, Sb, Cs, Ba, La, W, Re, Pt, Au, Hg, TI, Pb, Bi, Po, Fr, Ra, Ac, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu and Th. The transistor may further include a barrier metal film formed on the gate dielectric. hi another aspect of the present invention, a capacitor device is provided comprised of a de-oxidized surface of one of a trench formed in a substrate and a stack formed on the substrate, the de-oxidized surface formed by using atomic layer removal of at least one oxide mono-layer; and a capacitor dielectric formed by using atomic layer deposition of at least one dielectric mono-layer on the de-oxidized surface. The capacitor may include a barrier metal layer formed on the capacitor dielectric. The barrier metal film includes plural metal film mono-layers formed by atomic layer deposition; and each metal film mono-layer is comprised a compound that is one of titanium nitride, tantalum nitride, tungsten nitride, titanium aluminum nitride, tantalum aluminum nitride, tungsten aluminum nitride, titanium silicon nitride, tantalum silicon nitride, tungsten silicon nitride and a conductive oxide of one of Ru, Rh, Os and fr.

BRIEF DESCRIPTION OF DRAWINGS The invention will be described in detail in the following description of the invention with reference to the following figures.

FIGS. 1-3 are schematic diagrams illustrating basic steps of the atomic layer removal method according to one embodiment of the present invention.

FIGS. 4-6 are schematic diagrams illustrating the steps of the atomic layer exchange method according to another embodiment of the present invention.

FIGS. 7 and 8 are schematic diagrams illustrating basic steps of atomic layer removal following atomic layer exchange illustrated in FIGS. 4-6 according to another embodiment of the present invention.

FIGS. 9-13 are section views showing stages of forming a trench capacitor according to the present invention.

FIGS. 14-21 are section views showing stages of forming a transistor gate according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a novel method and system for forming dielectric insulators for semiconductor transistors and capacitors using atomic layer deposition and removal. Future increases in the performance of transistors will require increases in the dielectric constant of gate insulators and possibly improved gate electrode materials, hi one embodiment, a gate device is provided wherein the conventional insulators of Siθ2 is replaced with advanced insulators made of a nitride (e.g., Si3N_ι) and oxide stack or a nitride-oxide, and high dielectric constant insulators such as AI2O3, Ceθ2, H1O2 and Zrθ2, or such as silicates of Hf, Y and Zr (Hf, Y and Zr plus SiO_x), or such as aluminates of Hf, Y, La and Zr (Hf, Y, La and Zr plus Aloe_x) and Strip3. Doped poly-crystalline silicon (poly) or poly Si-Ge used for gate electrodes are capped with suicide such as CoSi and NiSi. i another embodiment, poly or SiG poly layers are replaced with single metal gate electrodes such as TiN, TaN, WN and W and with dual metal gate electrodes such as Pt, Ru, Ruθ2, hO, Ni, Ti, Mo, and the like.

As the dimensions of circuit features are reduced, the thickness of gate insulators and capacitor insulators must also be reduced, hi vary thin insulators, undesirable direct tunneling can occur. In addition to tunneling, current can leak through a gate insulator or a capacitor insulator. To avoid this, the equivalent oxide thickness (EAT) of the dielectric materials are conventionally kept greater than 20A where dielectric constants are greater than 3.9-8. A dielectric with low leakage current (less than 1 Ampere per square centimeter) with high voltage breakdown strength is required. The interface between the insulator and other materials should have a low density of traps to trap holes or electrons.

High performance transistors and capacitors require gate insulators with dielectric constants greater than 10 and an equivalent oxide thickness (EOT) less than 15A. Gate leakage current should be kept less than 1 Ampere per square centimeter for a 1 volt potential across the dielectric where the band gap energy Egg is greater than 5 eve. Several dielectric candidates are listed in Table 1.

Table 1 - Dielectric Candidates

Note that BST, SrTiθ3 react with Si at temperatures above 800 degrees C. Also note that Ta2θ_$ is not compatible with Si, and therefore Si3N₄ -barrier -layer is required. -

Preferred dielectric materials include AI2O3, Hfθ2, Hf-silicate, Zrθ2, Zr- silicate, Hf-aluminates and Zr-aluminates.

In alumina AI2O3, traps are formed that hold "holes" and electrons. As deposited, H2O based alumna AI2O3 films (e.g., as formed by water vapor and TMA, A1(CH3)3) exhibit both hole traps and electron traps. However, after annealing for 30 minutes at 800 degree C in nitrogen, electron traps are substantially eliminated. Hole traps persist.

A bare Si surface tends to self oxidize in the air and form a thin film referred to as a native oxide. The silicon oxide surface is referred to as a hydrophilic surface. The native oxide is a poor quality insulator in terms of leakage and other electrical properties, and therefore, the native oxide is ordinarily removed. To remove the oxide, HF is typically processed across the film, and this process leaves the Si surface terminated with hydrogen atoms and forms what is referred to as a hydrophobic surface.

The growth of a water based alumina AI2O3 film on a hydrophobic Si surface as preformed in the prior art is not easily formed. This growth must first go through an incubation or start up phase before alumina begins to be deposited, and approximately 15 cycles of ALD are required before the alumina AI2O3 film begins to grow. The chemistry of the reaction during incubation of the H2O based alumina AI2O3 film is generally given by:

Si + A1(CH₃)₃ + H₂O → Si + Al + O + OH^" + CH₄ (1)

-> Si(OH) + Al(OH) + A1O + ... (2)

ALD deposits of such alumina films of 10 Angstroms or less are impossible since the incubation phase deposits grow to that thickness before actual alumina growth begins. In addition, alumina films thinner than 40 Angstroms are prone to electrical leakage.

Then, once the incubation phase is complete, the chemistry of alumina growth proceeds as:

2A1(CH₃)₃ + 3H₂O → Al₂O₃ + 3CH₄ (3) -

For example, in temperature ranges around 300 degrees C, mono layer growth (e.g., atomic layer deposition, ALD, as discussed below) proceeds with trimethyl aluminum

A1(CH3)3 (also called TMA) and water vapor as precursors. Each ALD cycle adds about 0.85A of dielectric material. However, inherently within an ALD process with TMA (trimethyl aluminum) plus water as precursors, the following reaction also occurs:

A1(CH₃)₃ + 3H₂O → Al(OH)₃ + 3CH₄. (4) leaving a dielectric film containing some Al(OH)3. Al(OH)3 tends to weaken the properties of the dielectric film. With H2O based alumina AI2O3 films, peeling can occur perhaps due to pin hole defects in the surface.

The present invention overcomes these limitations by providing Alumina films grown using TMA and ozone as reactants as opposed to water based alumina films.

As deposited, O3 based alumina AI2O3 films are pure oxide, have no OH^" bonds and suffer no incubation phenomena. Little or no hysteresis is produced in C-V curves, and less carbon is produced in the film. Such films exhibit improved leakage current characteristics without producing oxygen deficient AI2O3 layers. The same alumina AI2O3 film may be produced on different materials and structures. The chemistry of the reaction of the O3 based alumina AI2O3 film is generally given by:

2Al(CH₃)₃ + O₃ → Al₂O3 + 3C₂H₆. (5)

Aluminates (including AI2O3), Hfθ2 and silicates form good insulators. The use of the above described ozone based precursor process suppresses the formation of

OH^" in the gate dielectrics. The layer by layer atomic layer deposition growth process provides excellent coverage over large substrate areas and provides excellent step coverage. The ozone based atomic layer deposition process of the present invention builds the insulator layer by layer using a low theπnal budget (to lessen diffusion in earlier formed structures) and with less impurities being introduced when compared to prior art processes. The low thermal budget minimizes the growth of interfacial oxides as discussed further below. hi general, a method of forming a high-k dielectric film on the surface of a substrate is provided, comprising: reacting a first reactant gas with an exposed surface of the semiconductor substrate in a reactor to convert the exposed surface into a solid mono-layer, evacuating the first reactant gas from the reactor, reacting a second reactant gas with the solid mono-layer in the reactor to convert the solid mono-layer into a gaseous compound, and evacuating the second reactant gas and the gaseous compound from the reactor. The exposed surface of the semiconductor substrate is comprised of a compound that is an oxide of any one of a metal, silicon, germanium, and a bi-element semiconductor formed from group in and group V.

In one aspect of the present invention the method comprises the following pulse cycles: a metal alkyl amide reactant is pulsed into the reaction chamber to form a non layer on the surface of the substrate. The reaction chamber is then purged of unreacted metal alkyl amides and by-products. Next, ozone gas is pulsed into the reaction chamber and reacts with the mono layer on the substrate to form a desired film or layer. Unreacted ozone and by-products are removed from the reaction chamber. The pulse cycle is repeated as many times as necessary to achieve the desired film thickness, h this embodiment the metal alkyl amide reactant is comprised of the formula:

M(NR^! R²)_n where M is a Group IV metal including but not limited to aluminum, hafiiium,

1 0 zircomum and titanium; n is 4; R and R , independently, are selected from the group of alkyls where the alkyls may be substituted, unsubstituted, linear, branched and/or cyclic, hi one preferred embodiment, R¹ and R² are individually, a CI- C6 alkyl, such as methyl and ethyl. In another preferred embodiment, the ligand (NR¹ R²) are ethylmethyl amides. In another embodiment a first reactant gas is comprised a compound that is any one of water vapor, methanol, ethanol, propanol, and butanol; and the second reactant gas comprises a compound that is any one of C1F₃, BF₃, BC1 , NF₃, NC1₃, HF, HC1, fluorine and chlorine.

In yet another embodiment the first reactant gas comprises a compound that includes a hydroxyl group, and the second reactant gas comprises of a halogen containing compound. In still another embodiment, the first reactant gas is trimethyl aluminum (A1(CH₃)₃) and the second reactant is ozone (O₃). Additional gas reactants are suitable and include MPA (methylpyrrolidine alane); modified TMA (methylpyrrolidine TMA, ethylpiperidine TMA); DMAH (dimethyl aluminum hydride, A1((CH₃)₂)H); modified DMAH (methylpyrrolidine dimethyl aluminum hydride, methylpiperidine dimethyl aluminum hydride, ethylpiperidine dimethyl aluminum hydride); TEMAT (Ti[N(CH₃)C₂H₅]₄); PEMAT (Ta[C₂H₅N(CH₃)]₅); TEMAHf (Hf[C₂H₅N(CH₃)]₄); TEMAZr (Zr[C₂H₅N(CH₃)]₄); TDMAHf (HfrN(CH₃)₂]₄); TDMAZr (Zr[N(CH₃)₂]₄); TDEAHf (Hf[N(C₂H₅)₂]₄); TDMAZr (Zr[N(C₂H₅)₂]₄); cocktailed BST source (Ba(tetramethylheptanedionate)2, Sr(tetramethylheptanedionate)2) and cocktailed STO source (Sr(tetramethylheptanedionate)2, Ti(i-OPr)2(tetramethylheptanedionate)2). In another aspect of the invention, a structure includes a de-oxidized substrate formed by using atomic layer removal of at least one oxide mono-layer and a dielectric film formed by using atomic layer deposition of at least one dielectric mono-layer on the de-oxidized substrate. hi a further aspect of the present invention, a transistor device is provided comprised of a drain and a source formed in a substrate; a de-oxidized channel defined in the substrate between the drain and the source and formed by using atomic layer removal of at least one oxide mono-layer; and a gate dielectric formed by using atomic layer deposition of at least one dielectric mono-layer on the de-oxidized channel. The gate dielectric may include plural dielectric mono-layers, where each dielectric mono- layer comprises a compound that is any one of AI2O3, Tiθ2, H1O2, Ceθ2, ZrO₂,

Ta2θ5 and an oxide of one of Li, Be, Na, Mg, K, Ca, Sc, V, Cr, Mn, Fe, Co, Ni, Cu,

Zn, Ga, Ge, Rb, Sr, Y, Nb, Mo, Tc, Pd, Ag, Cd, In, Sn, Sb, Cs, Ba, La, W, Re, Pt, Au, Hg, TI, Pb, Bi, Po, Fr, Ra, Ac, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu and Th. The transistor may further include a barrier metal fihn formed on the gate dielectric.

In another aspect of the present invention, a capacitor device is provided comprised of a de-oxidized surface of one of a trench formed in a substrate and a stack formed on the substrate, the de-oxidized surface formed by using atomic layer removal of at least one oxide mono-layer; and a capacitor dielectric formed by using atomic layer deposition of at least one dielectric mono-layer on the de-oxidized surface. The capacitor may include a barrier metal layer formed on the capacitor dielectric. The barrier metal film includes plural metal film mono-layers formed by atomic layer deposition; and each metal film mono-layer is comprised a compound that is one of titanium nitride, tantalum nitride, tungsten nitride, titanium aluminum nitride, tantalum aluminum nitride, tungsten aluminum nitride, titanium silicon nitride, tantalum silicon nitride, tungsten silicon nitride and a conductive oxide of one of Ru, Rh, Os and Jr. In one embodiment, during pulsing cycles where the reactants are introduced, the wafer is heated to a temperature in the range of approximately 100 °C to 500 °C, and preferably in the range of approximately 200 °C to 400 °C. To minimize temperature variation, this temperature range may be maintained throughout the method.

In one embodiment the method is carried out at a pressure in the reaction chamber of approximately 0.1 to 5 Torr, and preferably in the range of approximately 0.1 to 2 Torr. The pressure may be lower during the purge or evacuation steps.

Precursors or reactants to deposit high-k metal oxides and oxynitrides according to embodiments of the present invention include, but not limited to metal amides, metal alkoxides, metal halides, metal nitrates, metal alkyl, metal hydrides, metal diketonates, metal diiminates. The oxygen source to deposit high-k metal oxides and oxynitrides includes O₂, O₃, atomic oxygen, H O₂, alcohol, NO, and N₂O. Nitrogen sources to deposit metal nitrides and metal oxynitrides include ammonia, alkyl amine, hydrazine, substituted hydrazine, and atomic nitrogen. The film deposited by the method of the present invention may be deposited on a variety of substrates, including silicon, plastic, organic polymers, glass, and inorganic and organic particles.

The exact process conditions used to carry out the present invention will vary depending on the exact application, and may be determined by one of ordinary skill in the art with routine experimentation, hi one illustrative example of the present invention, ALD is carried out to form metal oxides using ozone at the following process conditions: Deposition temperature: 20°C to 700°C, preferably 50° to 500°C. Precursor gas flow : 1 seem to 2000sccm, preferably, lOsccm to lOOOsccm. Precursor pulse time O.Olsec to 30sec, preferably 0.05 sec to lOsec. Ozone gas flow: 10 to 5000sccm, preferably 50 to 2000sccm. Ozone pulse time: 0.1 sec to lOOsec, preferably, 0.5sec to lOsec. Evacuation includes purge and/or pumping steps. hi another illustrative example of the present invention, ALD is carried out to form metal nitride layers with the following process conditions: Deposition temperature: 20°C to 700°C, preferably 50° to 500°C. Precursor gas flow : 1 seem to 2000sccm, preferably, lOsccm to lOOOsccm. Precursor pulse time O.Olsec to 30sec, preferably 0.05 sec to lOsec. NH₃ flow: 10 to 5000sccm, preferably 50 to 2000sccm. NH₃ pulse time: 0.1 sec to lOOsec, preferably, 0.5sec to lOsec. Again, the term evacuation includes purge and/or pumping steps. The various embodiment of the present invention are now described in detail. The reactant gases are introduced into a reaction chamber, preferably through what is referred to as a showerhead for even distribution of gases. A variety of reaction chambers may be used and are known in the art. The showerhead type reactor is preferred for introducing precursors when ozone is used. Two examples of a suitable chambers and systems for carrying out the invention are described in U.S. Patent nos. 6,579,372 and 6,573,184. hi the description of methods and structures described herein, the abbreviation

ALD is often used when referring to the atomic layer deposition aspect of the method. The abbreviation ALR is often used when referring to the atomic layer removal aspect of the method, and the abbreviation ALEx is often used when referring to the atomic layer exchange aspect of the method.

One of the persistent problems in achieving a high performance and very thin dielectric film is the generation of interfacial oxides between the dielectric and the underlying semiconductor surface. Possible sources of this oxide may be from an unremoved native oxide or an interfacial oxide layer formed during the deposition of the dielectric film. Even if the native oxide is removed (e.g., by conventional methods such as HF treatment just prior to deposition of the dielectric film), the process of depositing the dielectric film has its own oxygen sources to form the interfacial oxide. For example, in the ALD process to generate AI2O3 films, the oxygen present in water or ozone (precursor gases), binds to the Si surface to form Siθ2-

Interfacial oxides need to be suppressed in order to achieve low EOT values.

To minimize the interfacial oxide, according to one embodiment of the present invention the native oxide is substantially removed (leaving preferably less than 4 oxide mono-layers, more preferably one mono-layer) or totally removed before depositing the dielectric. Furthermore, the temperature used in the process of depositing the dielectric is minimized.

However, this interfacial silicon dioxide is all but unavoidable, and it tends to grow to an EOT of from 5 to 9 Angstroms or more, and often on the thicker side. This is one reason that the growth of high dielectric constant materials on a surface is difficult.

Native oxide is formed to an uncontrolled thickness that depends loosely on the history and handling of the semiconductor wafer according to the present invention. Of significant advantage, one aspect of the present invention provides for removing and replacing the native oxide with an oxide of controlled thickness. For example, bare silicon reacted with steam or ozone for a predetermined time at a predetermined temperature will produced an oxide with a controlled thickness. But this thickness is often too thick for the application of advanced high performance dielectrics. Therefore, this oxide is made thinner by the repeated application of atomic layer removal (ALR) as described herein until the oxide is substantially removed (leaving less that 4 oxide mono-layers, preferably one mono-layer) or totally removed before depositing the dielectric. Following removal or substantial removal of the native oxide, a metal oxide layer is formed on the substrate. In one embodiment, the ALD process is carried out using ozone and a metal organic as precursors, at a temperature of about 350 degrees C. Examples of metal organic precursors include Hf amide or Hf(O-t-Bu)₄ where O-t-Bu is a tertiary butoxy anion. In this embodiment a H1O2 layer is grown to a thickness of about 80 Angstroms. If 80 Angstroms is too thick for the target application, atomic layer removal (ALR) by the processes described herein is repeatedly applied to the Hfθ2 dielectric film a predetermined number of times until the desired thickness is obtained.

When forming high performance gate insulators or capacitor insulators, high K (meaning a dielectric constant of about 10 or more) dielectric materials with EOT less than about 12 Angstroms (i.e., 1.2 nm) are preferred. Customarily, to form the dielectric, a thin hydrophilic Siθ2 interfacial layer of less than 5 Angstroms (i.e., 0.5 nm) is formed on a hydrophobic Si surface that has be cleaned or conditioned with HF. Then, a dielectric material is grown on the thin Siθ2 interfacial layer using ALD technology.

In contrast, as described herein the present invention provides an atomic layer removal (ALR) method and system. The ALR method is followed by successive ALD steps. A substrate having a film (such as a native oxide or a thickness controlled oxide) on the surface of the substrate is placed in a reactor. A first reactant gas is introduced into the reactor to react with a first layer of the film to convert the first layer into a mono-layer of a solid compound. A second reactant gas is then introduced into the reactor to react with the mono-layer of the solid compound to form a gaseous compound, which is removed from the reactor.

The present invention may advantageously be utilized for the removal of one or more atomic layers from the surface of the wafer. In particular, this process may be used to remove the native oxide or thickness controlled oxide where the native oxide or thickness controlled oxide is an oxide of any of a metal, silicon, germanium and a bi- element semiconductor formed from group III and group V.

Additionally, the atomic layer removal process is a self terminating sequential atomic layer removal process. This process may be used to remove any oxide on the silicon surface or other semiconductor surface prior to a deposition process. Further, the present invention may be used to reduce a deposited conductive or dielectric film thickness to achieve a desired final film thickness. These are just a few of the applications of the present invention.

Many processes used to deposit dielectrics by ALD, use an oxide on which the precursors react. Therefore, removal of all of the oxide before the dielectric deposit is undesirable. It this case, it is preferred that the native oxide be removed and be replaced by a controlled thickness oxide. However, such a controlled thickness oxide may be thicker than desired. Therefore, the controlled thickness oxide is substantially removed (leaving less that 4 oxide mono-layers, preferably one mono-layer) by repeating the steps of atomic layer removal a predetermined number of times. The number of times the ALR is repeated depends on the thickness of the controlled thickness oxide. Then, the dielectric film is deposited by ALD or other means.

When certain dielectrics are desired, such as a dielectric that includes Ta2θ5, it is desirable to inteφose a nitride film between the semiconductor material and the dielectric. In this case, a native oxide or the controlled thickness oxide is totally removed by HF treatment or by repeating the steps of atomic layer removal a sufficient number of times to remove all oxide. Then, the bare semiconductor surface is reacted with ammonia to form a controlled thickness of the nitride film. Here too, the nitride film may be thicker than desired. To thin the nitride film, the controlled thickness of the nitride film is substantially removed (leaving less than 4 nitride mono-layers, preferably one or two mono-layer, sufficient as a barrier) by repeating the steps of atomic layer removal a predetermined number of times. Preferably, the nitride surface is reacted with a halogen containing gas such as fluorine. The reaction may be self- starting or may be optionally initiated by an energy source such as UV radiation. Such a reaction with Si3N₄ (the nitride film) will produce NF3 and SiF₄ as products (both gases which can be removed from the reaction chamber). The reaction time (e.g., UV activation pulse time) and other factors (e.g., temperature, pressure, etc.) are controlled 5 so that each cycle removes only a predetermined thickness (preferably one mono-layer) of nitride. Such variables may be determined by those of ordinary skill in the art with routine experimentation. The number of times the ALR is repeated depends on the thickness of the controlled thickness nitride. Then, the dielectric film (e.g., a film that includes Ta2θ5) is deposited by ALD or other means.

10 When metal-insulator metal (MEVI) capacitors are to be formed, the first metal to be formed is a barrier metal film deposited directly on a semiconductor substrate that may be formed of any of a metal, silicon, germanium, and a bi-element semiconductor formed from group III and group V. This semiconductor substrate also includes doped polycrystalline forms (commonly called poly) of any of a metal, silicon,

15 germanium and a bi-element semiconductor formed from Group III and Group V. In this case, any native oxide or the controlled thickness oxide is totally removed by HF treatment or by repeating the steps of atomic layer removal (ALR) a sufficient number of times to remove all oxide. Then, a barrier metal film is deposited by ALD on the bare semiconductor surface. The barrier metal film preferably includes a compound

20 that is one of titanium nitride, tantalum nitride, tungsten nitride, titanium aluminum nitride, tantalum aluminum nitride, tungsten aluminum nitride, titanium silicon nitride, tantalum silicon nitride, tungsten silicon nitride and a conductive oxide of one of Ru,

- - - - Rh, Os and Ir. Then, the dielectric film is deposited by ALD or other means on the barrier metal film. Since, the barrier metal film provides good electrical contact with

25 the underlying semiconductor, it serves as one electrode of the MIM (or a MIS) capacitor.

Similarly, controlled thickness dielectric films may be deposited on their substrates by any means. Then, the film is thinned by the below described ALR process to a desired thickness.

30 More specifically in one embodiment of the present invention a method of depositing a thin dielectric film on a substrate using atomic layer removal (ALR) is provided. According to the present method, a substrate having a film deposited on the surface of the substrate is placed in a reactor. The film is typically comprised of multiple atomic layers. A first reactant gas is introduced into the reactor to react with a first layer of the film to convert the first layer into a mono-layer of a solid compound. The excessive first reactant gas is evacuated from the reactor with an inert purge gas. Thereafter, a second reactant gas is introduced into the reactor to react with the mono-layer of the solid compound to form a gaseous compound. The gaseous compound and excessive second reactant gas are then removed from the reactor. The chemistries are chosen such that the second reactant gas does not react with the original film. In this way, only one atomic layer is removed. A second, third, and more layers of the film can be removed by repeating the above steps until a desired number of layers remain on the substrate. Generally, the reactant gases are introduced into the reactor for a period of time sufficient to react with one mono-layer (i.e., atomic layer) of the film.

The present ALR method is now described in more detail with reference to FIGS. 1-3. A further description of the ALR method is described in PCT Patent application no. PCTUS03/19982 filed June 23, 2003 (Attorney docket no. FP-71606- PC/MSS) which claims the benefit of U.S. Provisional patent application no. 60/391,011 filed on June 23, 2002, the disclosures of both of which are hereby incoφorated by reference in their entirety. FIG. 1 schematically shows a substrate having film A deposited on the surface of the substrate. While three layers of film A are shown in FIG. 1 for illustrative puφose, the number of layers pre-deposited on the surface of the substrate may vary widely depending on the specific application. The film A to be removed can be of any type of film used in semiconductor processing such as any gate dielectric or capacitor dielectric or ceramic, including metal oxides^ aluminates, silicates, nitrides, pure metals, or oxides of any one of silicon, germanium or a bi-element semiconductor formed from Group III and Group V. hi FIG. 2, a first reactant gas B is reacted with the top layer of the film A to convert the top layer to a mono-layer of a solid compound D. The first reactant gas B is a chemical agent that converts an atomic layer of film A to a mono-layer of a solid compound D, which can be further reacted with a second reactant gas C as described below. The selection of the first reactant gas B depends on the molecular composition of film A. Preferably the first reactant gas B is selected such that the mono-layer of the solid compound D formed needs less energy to further react with the second reactant gas C (as described below) than that required by the next layer of film A underneath the mono-layer of the solid compound D. The reaction of the second reactant gas C with the solid mono-layer D preferably requires less activation energy than the activation energy required for the reaction of the second reactant gas C with the surface A underlying the solid mono-layer D. Examples of first reactant gas B precursors that may be used include, but are not limited to, ozone and ammonia.

In FIG. 3, the mono-layer of the solid compound D is then reacted with a second reactant gas C to form a gaseous compound E. This formed gaseous compound E is removed from the reactor by any suitable means such as pumping out with the aid of a purge gas. In one example, the second reactant gas C that reacts with the converted mono-layer of solid compound D may be a halogen containing compound. Examples of halogen containing compounds include, but are not limited to CIF3, BF3,

BCI3, NF3, NCI3, HF, HC1, fluorine and chlorine.

The above steps of this embodiment of the present ALR method can be summarized in the following equations:

A (solid) + B (gas) → D (Solid) (6)

D (solid) + C (gas) - E (Gas) t (7)

The steps (6) and (7) can be repeated until any desired number of, or all, layers of films A are removed from the substrate.

Another embodiment of the present invention is illustrated in FIGS. 4-6. In FIG. 4 of this embodiment, the film or wafer surface is comprised of a compound of two elements, AB. For example, the wafer surface may contain a film, or it may contain only silicon with either hydrogen termination (i.e., hydrophilic surface) or a native oxide (i.e., hydrophobic surface) formed thereon, hi this example, atomic layer exchange takes place. h FIG. 5, the wafer is exposed to a gaseous precursor CD. A surface reaction and exchange of species occurs with the top layer on the wafer. In this example, the surface reaction converts the top layer to a mono-layer of solid compound AD (see FIG. 6), and a gaseous compound of CB is formed which is removed or purged from the chamber.

In this embodiment, the steps maybe summarized by the following equation: AB (solid) + CD (gas) → AD (solid) + CB(gas) t (8)

Many types of gaseous precursors or reactants may be employed with the method of the present invention, and will be selected based in part on the chemical composition of the film. Additional examples of gaseous precursors include, but are not limited to: MPA (methylpyrrolidine alane); modified TMA (methylpyrrolidine TMA, ethylpiperidine TMA); DMAH (dimethyl aluminum hydride, A1((CH₃)₂)H); modified DMAH (methylpyrrolidine dimethyl aluminum hydride, methylpiperidine dimethyl aluminum hydride, ethylpiperidine dimethyl aluminum hydride); TEMAT (Ti[N(CH₃)C₂H₅]₄); PEMAT (Ta[C₂H₅N(CH₃)]₅); TEMAHf (HfIC₂H₅N(CH₃)]₄); TEMAZr (Zr[C₂H₅N(CH₃)]₄); TDMAHf (Hf[N(CH₃)₂]₄); TDMAZr (Zr[N(CH₃)₂]₄); TDEAHf (Hf[N(C2H₅)₂]₄); TDMAZr (Zr[N(C₂H₅)₂]₄); cocktailed BST source

(Ba(tetramethylheptanedionate)2, Sr(tetramethylheptanedionate)2) and cocktailed STO source (Sr(tetramethylheptanedionate)₂, Ti(i-OPr)2(tetramethylheptanedionate)2).

Given the teaching of the present invention, the specific reactants may be selected by those of ordinary skill in the art with routine experimentation.

As described above, atomic layer exchange takes place between free radicals or molecules in the gas phase and molecules on the wafer surface. Diffusion of these gaseous precursors through the wafer surface may be controlled by a number of parameters. These parameters include temperature (e.g., which advantageously varies between 200 - 400 degrees for alumina), pulse time (that refers to the time interval for reaction defined by an activation source such as UV radiation and may advantageously vary between 1 to 10 seconds), chamber pressure (that may advantageously be less than 10 Torr), the size of the molecule of the reactant gas, the reactivity of the molecules in the reaction, all to avoid multi-layer atomic exchange.

In another embodiment of the method of the present invention, atomic layer removal (ALR) follows the atomic layer exchange (ALEx) discussed above with respect to FIGS. 4-6. Atomic layer exchange is first carried out as discussed above with respect to

FIGS. 4-6 to modify the chemistry of the film surface according to the following equation: AB (solid) + CD (gas) → AD (solid) + CB(gas) t (9)

The gaseous precursor CD is first conveyed to the chamber. Then, once the gaseous precursor is in the reaction chamber, the precursor is activated. As discussed above, activation may take place by a variety a means, such as by temperature, energy pulse, and the like. Once activated, atomic layer exchange with the top layer of the film takes place as shown in FIG. 6, and the chamber is purged so that the formed gaseous byproduct CB is removed from the chamber. The top layer of the film has now been converted to the compound AD as shown in FIG. 6.

Next, atomic layer removal is carried out to remove the mono-layer AD that is disposed on the film as shown in FIGS. 7 and 8. In FIG. 7 of this example, a gaseous precursor XY is selected, and the mono-layer AD reacts with XY and the film AB (the layer of the film underlying AD) does not react with XY. When the gaseous precursor XY enters the reaction chamber, the precursor is activated. As discussed above, the precursor may be activated by such means as by an energy pulse or other means. A further description of an energy assisted method is described in PCT patent application PCTUS03/19984 filed June 23, 2003 (Attorney docket no. FP-71606-l-PC/MSS) which claims the benefit of U.S. Provisional patent application no. 60/391,012 filed June 23, 2002 and U.S. Provisional patent application no. 60/396,743 filed on July 19, 2002, the disclosures of all of which are hereby incoφorated by reference in their entirety. In this example, reaction products in the gas phase are:

AD (solid) + XY (gas) → DX (gas) + AY(gas) (10)

The reaction occurs and the gaseous products DX and AY are formed and purged from the chamber as shown in FIG. 8. Thus, one atomic layer of the film has been removed. These steps may be repeated as many times as desired for additional atomic layer removal. In an illustrative example, a layer of titanium nitride (TiN) is provided, and the removal to a desired thickness is achieved by the method and system of the present invention. Titanium nitride (TiN) is a preferable material for gate electrode barrier. To deposit a thin TiN film on a substrate, a relatively thick TiN film can be pre-deposited on the surface of a gate dielectric.

According to this embodiment of the present invention, ozone gas is introduced to convert the top atomic layer of TiN film to a mono-layer of titanium dioxide (TiO₂). The solid TiO₂ layer is then further reacted with hydrogen fluoride (HF) vapor to form gaseous titanium fluoride (TiF) and water vapor, which are evacuated from the reactor. Each cycle of the method can remove one atomic layer of TiN from the substrate. By repeating the process, an ultra thin TiN film of a desired thickness can be achieved or "deposited" on a silicon substrate. There is no limitation on the number of TiN layers that can be removed by the atomic layer removal method of the present invention.

In another example where a silicon diode film is pre-deposited or otherwise formed as a native oxide, ethanol can be used as a first reactant gas to react with silicon dioxide (SiO ) film pre-deposited on a substrate. A mono-layer of silicon hydroxide (SiOH) is formed on the top surface of the substrate. Hydrogen fluoride (HF) can be used as a second reactant gas to react with the solid silicon hydroxide to form gaseous silicon fluoride (SiF₄) and water vapor, which are evacuated from the reactor chamber.

The method of the present invention can be used to particular advantage as a process to deposit an ultra thin film on a substrate. For instance, prior art deposition technology has limitations in depositing a dielectric film having an ultra-thin thickness, such as a thickness of 3 A. With the method of the present invention, a dielectric film having a greater thickness (e.g. 10A) can be first deposited on the surface of a substrate. Then, layers of the dielectric films can be removed from the substrate using the atomic layer removal method as described above. There is no limitation on the number of layers that can be removed. Thus, if a dielectric film with a thickness of 3A is desired, then layers of a thickness of 7A of the dielectric film can be removed by repeating the steps as described above, leaving a film with a thickness of 3 A remaining on the surface of the substrate.

The atomic layer deposition and removal method of the present invention has broad applications. For example, the present invention can be used to etch metals and dielectrics, generate photolithographic masks, and improve resolution of liquid crystal displays, among other applications. Additionally, atomic layer removal of the present invention may be used for reducing a final film thickness and/or removing undesired surface roughed prior to forming gate electrodes. The silicon - high K dielectric interface may be controlled by atomic layer exchange of the present invention along with low temperature ALD high K dielectric processes.

There are additional applications for and benefits of high - K dielectrics. For example, for gate insulators and capacitor insulators, nano-laminates with multiple films and inter-film surfaces create opportunities for more undesired interface traps.

Therefore, bulk application of films followed by atomic layer removal may advantageously be used to form ultra-thin films.

Another embodiment of this invention provides for ultra-thin layers of oxide. For example, a layer of silicon dioxide may be formed to a thickness of 9 Angstroms. This is a considerable portion of the total thickness that can be allocated to advanced insulator dielectrics. If the final thickness for the dielectric is to be only 12 Angstroms, then a 9 Angstrom this film of silicon dioxide would be 75% of the allowable thickness, leaving only 25% of the allowable thickness for a high dielectric constant dielectric. However, in this embodiment, atomic layer removal is used to reduce the thickness of the silicon dioxide to only 1.2 Angstroms or about 10% of the allowable thickness. This ultra-thin silicon dioxide film serves to control mobility at the interface. Upon this ultra-thin film of silicon dioxide, a very high dielectric constant insulator is deposited by atomic layer deposition. Thus, the total dielectric fits within the 12 Angstrom allowable thickness and is composed of 10% silicon dioxide and 90% AI2O3, Tiθ2, H1O2, Ceθ2, Zrθ2, Ta₂O5 or whatever high k dielectric is used.

The trend in the performance of integrated circuit capacitors, for example as used in dynamic random access memories (DRAMs), follow the growth from planar cells with silicon dioxide insulators to both trench capacitors (etched deeply into the semiconductor surface) and stack capacitors (built up on the semiconductor surface). Future increases in the performance of such capacitors will depend on the ability to reduce the size of such capacitors and the migration to capacitor technologies such as MLM (metal-insulator-metal) and MIS (metal-insulator-silicon), hi both stack and trench capacitors, the physical size of SIS (silicon-insulator-silicon) capacitors and MIS capacitors can be reduced significantly by migrating to a MEVI technology, and yet produce the same capacitance. However, as size gets smaller, the insulator dielectric must become thinner. For example, for a relatively large but advanced capacitor (e.g., stack height > 1 micrometer or trench depth greater than 0.1 micrometer) of about 25 femto Farads, the equivalent oxide thickness (EOT) would need to be 30 to 35 Angstroms for SIS or MIS capacitors. However, advanced MIS or MLM capacitors with advanced dielectrics would need EOTs in the range of 5 to 10 Angstroms. Such dielectric insulators can be obtained with nano-laminate processing of advanced dielectrics such as Si3N₄, AI2O3, Ta2θ5, Hfθ2, Zrθ2, Tiθ2, La and Y aluminate, other nano-laminates such as ATO/AHO, STO, and Perovskites such as BST/PZT. Capacitor performance can be enhanced by use of advanced electrode technologies such as HSG (hemispherical grained) poly silicon, TiN/TaN with or without poly silicon, ternary compounds such as TiATN or TaSiN, nobel metals such as Ru or Ruθ2, or Perovskites such as SRO/LSCO.

Example - Capacitor Device

In one example of a method to form a trench type capacitor 100 with a trench depth of less than 100 nm, the trench 102 is formed conventionally (e.g., by reactive ion etching), followed by formation of a conventional collar 104 at the top of the trench. See FIG. 9.

The trench, below the collar, is coated with a doped silicon deposition at a temperature that produces a doped poly with graining between amoφhous silicon and poly-crystalline silicon (often by CVD) in a process called "seeding." Then, the trench is annealed in an ultra high vacuum. The "seed and anneal" process is typically based on UHV CVD. The isothermal exposure of the amoφhous silicon surface to a silicon source gas at low pressure, followed by an anneal, tends to roughen the lower electrode to as to increase the surface area and increased the capacitance relative to a smooth surface in a trench capacitor. Such increased surface area can be as much as 2:1. The anneal process leaves the lower electrode with microscopic "bumps" 106 or folds in the surface, the folds having a dimension of about 20 nm. Such a process is called HSG (hemispherical grained) silicon. See FIG. 10.

With this increased surface area, an advanced dielectric 108, such as AI2O3, is deposited on the roughened surface by the atomic layer deposition (ALD) process using a layer by layer build up to an EOT of less than 3.6 nm. The steps of this process might include removing any native oxide and replacing it with a controlled thickness oxide followed by the removal of the oxide by ALR until a very thin oxide is achieved (e.g., less than 4 mono-layers, preferably one mono-layer). Then, the advanced dielectric is deposited by ALD. Finally, a poly layer 110 is deposited over the advanced dielectric to serve as the upper capacitor electrode and complete a SIS capacitor. See FIG. 11.

Such a capacitor can achieve a capacitance of 25 femto Farads and have a leakage current of less than 1 femto Amperes per capacitor cell. The AI2O3 insulator formation in a SIS capacitor exposes the semiconductor device to temperatures no more than 350 degrees C. for no more than 4 minutes. During this exposure, some minimal interfacial silicon oxide is formed between the HSG silicon and the advanced dielectric since some of the oxygen in the AI2O3 migrates to bond to the underlying silicon. However, since the temperature budget is kept low, the interfacial oxide is kept extremely thin.

In FIG. 12, a barrier metal film 112 is deposited over the advanced dielectric before the poly is deposited. The barrier metal film 112 conforms to the roughened surface of the trench. Then, a metal film 114 is formed over the barrier metal film by plating metal onto the barrier metal film. See FIG. 12.

Finally, any void remaining in the trench is filled with a doped poly-crystalline silicon 116 before the wafer is subjected to chemical mechanical polishing to remove excess plated material. See FIG. 13. In this way, one electrode of the capacitor is metal to form a SIM capacitor. Alternatively, a stacked capacitor of 25 femto Farads of height of less than 130 nm is formed with an HSG silicon surface using an AI2O3 advanced dielectric to a thickness (EOT) of less than 3.6 nm, followed by a poly deposition to form a SIS capacitor. Or a stacked capacitor of 25 femto Farads of height of less than 130 nm is formed with an HSG silicon surface using a Ta₂O5 advanced dielectric to a thickness (EOT) of less than 3.7 nm, followed by a metal deposition to form a MIS capacitor. The AI2O3 insulator formation in the SIS capacitor exposes the semiconductor device to temperatures no more than 350 degree C for only 4 minutes, and the Ta₂O5 insulator formation in the MIS capacitor exposes the semiconductor device to temperatures no more than 750 degrees C. for no more than 30 minutes. In a variant of the above described stacked capacitor of 25 femto Farads of height of less than 130 nm that is formed with an HSG silicon surface using an AI2O3 advanced dielectric, the dielectric is formed by the herein described atomic layer deposition (ALD) process using a layer by layer build up to an EOT of less than 2.8 nm (instead of less than 3.6 nm), and this process is followed by a TiN deposition to form an electrode of a MIS capacitor. Such a capacitor can achieve a capacitance of 25 femto Farads and have a leakage current of less than 1 femto Ampere per capacitor cell with operating voltages up to 1.5 volts. As discussed above, during this exposure, an interfacial silicon oxide is formed between the HSG silicon and the advanced dielectric; however, since the temperature budget is kept low, the interfacial oxide is kept thin (about 8 to 9 Angstroms).

The TiN is formed using a pseudo ALD process. Conventional CVD processes to deposit TiN using TiCl₄ as a precursor tend to have poor step coverage (about 25%).

This is particularly a problem when the capacitor dielectric is conformally formed over an HSG silicon surface. By using an ALD process (instead of CVD), the step coverage is excellent; however, the growth rate is slow. The pseudo ALD process, blends a mixture of both processes to achieve better than 90% step coverage with a bonus of low chlorine content (an atom from the precursor). Furthermore, the ALD and pseudo ALD processes produce capacitors with improved capacitance and leakage characteristics.

Ternary barrier metals may be used to achieve high crystallization temperatures, smooth moφhology due to amoφhous character of the film, good diffusion barrier and good oxidation resistance. Finally, the advanced dielectric that is built up layer by layer in the ALD process may be replaced with alternating nano-laminates of dielectrics. For example, a dielectric might be formed by a 15 Angstrom film of Tiθ2 (e.g., 15-20 ALD cycles), followed by a 20 Angstrom film of Al₂O3 (e.g., 20-25 ALD cycles), followed by a 15

Angstrom film of TiO₂ (e.g., 15-20 ALD cycles). These alternating nano-laminates can be custom designed to meet EOT requirements, dielectric constant requirements, leakage requirements. Two types of nano-laminates may alternate in a stack, or a mix of more than two types of nano-laminates may be formed in a stack of any desired thickness. The stacked capacitor structure may be formed using the above described insulator formation process for trench capacitors and vice versa.

Example - Gate Device h FIG. 14, the formation process to form gate 200 begins. Gate 200 is formed in substrate 202 with drain and source regions 204 defining a channel between the drain and source. The insulator material 206 is deposited on the substrate, patterned and a recess over the channel is etched into which an insulator 208 is formed and into which a poly gate electrode 210 is formed.

FIG. 15 is a section view of gate 200 after an oxide film 220 is grown on the wafer, typically by a convention CVD process. FIG. 16 is a section of the wafer after having been subjected to polishing (e.g., chemical mechanical polishing). FIG. 17 shows the gate 200 after the dummy gate electrode 210 and insulator 208 have been removed, for example, by etching. FIG. 18 is a section view of gate 200 after an advanced dielectric 222 (as discussed above) has been grown on the gate. FIG. 19 is a section view of gate 200 after a barrier metal 224 (e.g., WN or N) as been formed on the advanced dielectric 222. FIG. 20 is a section view of gate 200 after a metal 226 has been plated on the barrier metal 224. FIG. 21 is a section view of the metal gate 200 after having been subjected to polishing (e.g., chemical mechanical polishing).

Example - Low temperature deposition of Al₂O₃ by ALD

At a wafer temperature of 100°C and a chamber pressure of 1 Torr, trimethylaluminum (TMA) was delivered into a process chamber with an Ar flow of 445 seem for 0.2sec, followed by 1 sec of purge and 2 sec pulse of O₃ (180 g/m3, 390 seem), and 2 sec purge. This deposition cycle provided Al₂O₃ films on a 200mm diameter Si substrate with a deposition rate of 1.2A/cycle.

Example - Low temperature deposition of HfO? by ALD

At a wafer temperature of 120°C and a chamber pressure of 1 Torr, tetrakis(ethyhnethylamino)hafiιium (TEMAHf) was delivered into a process chamber with an Ar flow of 200 seem for 3.5 sec, followed by 1 sec of purge and 2 sec pulse of O3 (180 g/m3, 200 seem), and 3 sec purge. This deposition cycle provided HfO₂ films on a 200mm diameter Si substrate with a deposition rate of 1.5 A/cycle. Having described preferred embodiments and examples of a novel method and system for forming dielectric insulators of semiconductor transistors and capacitor using atomic layer deposition and removal (which are intended to be illustrative and not limiting), it is noted that modifications and variations can be made by persons skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments of the invention disclosed which are within the scope of the invention as defined by the appended claims. For example, a hafnium dioxide mono-layer may be grown using ozone and either hafnium (t-butoxide)₄ or hafnium dialkylamide as precursors. Having thus described the invention with the details and particularity required by the patent laws, what is claimed and desired protected by Letters Patent is set forth in the appended claims.

Claims

What is claimed is:

1. A method of processing a semiconductor substrate comprising: reacting a first reactant gas with an exposed surface of the semiconductor substrate in a reactor to convert the exposed surface into a solid mono- layer; evacuating the first reactant gas from the reactor; reacting a second reactant gas with the solid mono-layer in the reactor to convert the solid mono-layer into a gaseous compound; and evacuating the second reactant gas and the gaseous compound from the reactor.

2. The method of claim 1, further comprising repeating a predetermined number of times the reacting of the first reactant gas, the evacuating of the first reactant gas, the reacting of the second reactant gas, and the evacuating of the second reactant gas and the gaseous compound.

3. The method of claim 1, wherein the reaction of the second reactant gas with the solid mono-layer requires less activation energy than the activation energy required for the reaction of the second reactant gas with the surface underlying the solid mono-layer.

4. The method of claim 1, wherein a depth of diffusion of at least one of the first reactant gas and the second reactant gas into the exposed surface is controlled to avoid multi-layer atomic exchange by at least one process factor selected from a group that includes temperature, irradiation pulse time, chamber pressure, size of the molecule of the first and second reactant gases, and heat of formation of the molecule in the reaction.

5. The method of claim 1, wherein the exposed surface comprises of a compound that is an oxide of one of a metal, silicon, germanium and a bi-element semiconductor formed from group III and group V.

6. The method of claim 1, wherein the first reactant gas comprises a compound that includes a hydroxyl group.

7. The method of claim 1, wherein the first reactant gas comprises a compound that is one of water vapor, methanol, ethanol, propanol, and butanol.

8. The method of claim 1, wherein the second reactant gas comprises of a halogen containing compound.

9. The method of claim 1, wherein the second reactant gas comprises a compound that is one of C1F3, BF3, BCI3, NF3, NCI3, HF, HC1, fluorine and chlorine.

10. The method of claim 8, wherein the first reactant gas comprises a compound that includes a hydroxyl group.

11. The method of claim 1, wherein the exposed surface comprises of a compound that is an oxide of one of a metal, silicon, germanium and a bi-element semiconductor formed from group III and group V, the method further comprising: repeating the reacting of the first reactant gas, the evacuating of the first reactant gas, the reacting of the second reactant gas, and the evacuating of the second reactant gas and the gaseous compound until all oxides on the exposed surface are removed and a base is exposed, the base including one of a metal, silicon, germanium and a bi-element semiconductor formed from group III and group V; and forming a nitride film on the base by reacting ammonia with the base.

12. The method of claim 11 , further comprising: reacting a third reactant gas with an exposed surface of the nitride film in the reactor to convert the exposed surface into a gaseous compound; and evacuating the third reactant gas and the gaseous compound from the reactor.

13. The method of claim 12, further comprising repeating a predetermined number of times the reacting of the third reactant gas and the evacuating of the third reactant gas and the gaseous compound.

14. The method of claim 13, wherein a depth of diffusion of the third reactant gas into the exposed surface is controlled to avoid multi-layer atomic exchange by at least one process factor selected from a group that includes temperature, irradiation pulse time, chamber pressure, size of the molecule of the first and second reactant gases, and heat of formation of the molecule in the reaction.

15. The method of claim 13, wherein the third reactant gas comprises of a halogen containing compound.

16. The method of claim 1, wherein the exposed surface comprises of a compound that is an oxide of one of a metal, silicon, germanium and a bi-element semiconductor formed from group III and group V, the method further comprising: repeating the reacting of the first reactant gas, the evacuating of the first reactant gas, the reacting of the second reactant gas, and the evacuating of the second reactant gas and the gaseous compound until all oxides on the exposed surface are removed and a base is exposed, the base including one of a metal, silicon, germanium and a bi-element semiconductor formed from group III and group V; and forming a barrier metal film on the base by atomic layer deposition.

17. The method of claim 16, wherein the barrier metal film comprises a compound that is one of titanium nitride, tantalum nitride, tungsten nitride, titanium aluminum nitride, tantalum aluminum nitride, tungsten aluminum nitride, titanium silicon nitride, tantalum silicon nitride, tungsten silicon nitride and a conductive oxide of one of Ru, Rh, Os and Ir.

18. The method of claim 16, further comprising forming a dielectric mono- layer by atomic layer deposition, wherein the dielectric mono-layer comprises a compound that is one of Al₂O3, TiO₂, HfO₂, CeO₂, ZrO₂, Ta₂O5 and an oxide of one of Li, Be, Na, Mg, K, Ca, Sc, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Rb, Sr, Y, Nb, Mo, Tc, Pd, Ag, Cd, hi, Sn, Sb, Cs, Ba, La, W, Re, Pt, Au, Hg, TI, Pb, Bi, Po, Fr, Ra, Ac, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu and Th.

19. A structure comprising: a de-oxidized substrate formed by using atomic layer removal of at least one oxide mono-layer; and a dielectric film formed by using atomic layer deposition of at least one dielectric mono-layer on the de-oxidized substrate.

20. The structure of claim 19, wherein the de-oxidized substrate comprises: a base that includes one of a metal, silicon, germanium and a bi-element semiconductor formed from group III and group V; and less than four oxide mono-layers disposed on the base.

21. The structure of claim 19, wherein: the dielectric film includes plural dielectric mono-layers; and each dielectric mono-layer comprises a compound that is one of AI2O3,

Tiθ2, HfO₂, Ceθ2, Zrθ2, Ta₂O5 and an oxide of one of Li, Be, Na, Mg, K, Ca, Sc, V,

Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Rb, Sr, Y, Nb, Mo, Tc, Pd, Ag, Cd, In, Sn, Sb, Cs, Ba, La, W, Re, Pt, Au, Hg, TI, Pb, Bi, Po, Fr, Ra, Ac, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu and Th.

22. The structure of claim 19, further comprising a barrier metal film formed on the dielectric film.

23. The structure of claim 22, wherein: the barrier metal film includes plural metal film mono-layers formed by atomic layer deposition; and each metal film mono-layer comprises a compound that is one of titanium nitride, tantalum nitride, tungsten nitride, titanium aluminum mtride, tantalum aluminum mtride, tungsten aluminum mtride, titanium silicon nitride, tantalum silicon nitride, tungsten silicon nitride and a conductive oxide of one of Ru, Rh, Os and Ir.

24. The structure of claim 22, further comprising a metal film formed by plating a metal on the barrier metal fihn.

25. The structure of claim 19, wherein the de-oxidized substrate comprises: a base that includes one of a metal, silicon, germanium and a bi-element semiconductor formed from group III and group V; and a silicon nitride film formed on the base after all oxide mono-layers are removed by reaction of the base and ammonia and thinned to less than four nitride mono-layers by atomic layer removal of at least one silicon nitride mono-layer.

26. The structure of claim 25, wherein: the dielectric film includes plural dielectric mono-layers; and each dielectric mono-layer comprises Ta₂O5.

27. A structure comprising: a de-oxidized substrate formed by repeatedly using atomic layer removal of oxide mono-layers until no oxide mono-layer remains; a first barrier metal film formed by using atomic layer deposition of at least one metal film mono-layer on the de-oxidized substrate; and a dielectric film formed by using atomic layer deposition of at least one dielectric mono-layer on the first barrier metal film.

28. The structure of claim 27, wherein the de-oxidized substrate comprises a base that includes one of a metal, silicon, germanium and a bi-element semiconductor formed from group III and group V.

29. The structure of claim 27, wherein: the barrier metal film includes plural metal film mono-layers formed by atomic layer deposition; and each metal fihn mono-layer comprises a compound that is one of titanium nitride, tantalum mtride, tungsten nitride, titanium aluminum nitride, tantalum aluminum nitride, tungsten aluminum mtride, titanium silicon nitride, tantalum silicon nitride, tungsten silicon nitride and a conductive oxide of one of Ru, Rh, Os and Ir.

30. The structure of claim 27, wherein: the dielectric film includes plural dielectric mono-layers; and each dielectric mono-layer comprises a compound that is one of Al O3,

TiO₂, HfO₂, CeO , ZrO₂, Ta₂Os and an oxide of one of Li, Be, Na, Mg, K, Ca, Sc, V,

Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Rb, Sr, Y, Nb, Mo, Tc, Pd, Ag, Cd, In, Sn, Sb, Cs, Ba, La, W, Re, Pt, Au, Hg, TI, Pb, Bi, Po, Fr, Ra, Ac, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu and Th.

31. The structure of claim 19, further comprising a second barrier metal film formed on the dielectric film.

32. The structure of claim 31 , wherein: the second barrier metal film includes plural metal film mono-layers formed by atomic layer deposition; and each metal film mono-layer comprises a compound that is one of titanium nitride, tantalum nitride, tungsten nitride, titanium aluminum nitride, tantalum aluminum mtride, tungsten aluminum nitride, titamum silicon nitride, tantalum silicon nitride, tungsten silicon nitride and a conductive oxide of one of Ru, Rh, Os and Ir.

33. The structure of claim 31, further comprising a metal film formed by plating a metal on the barrier metal film.

34. A transistor comprising: a drain and a source formed in a substrate; a de-oxidized channel defined in the substrate between the drain and the source and formed by using atomic layer removal of at least one oxide mono-layer; and a gate dielectric formed by using atomic layer deposition of at least one dielectric mono-layer on the de-oxidized channel.

35. The transistor of claim 34, further comprising a barrier metal film formed on the gate dielectric.

36. The transistor of claim 35, wherein: the barrier metal film includes plural metal film mono-layers formed by atomic layer deposition; and each metal film mono-layer comprises a compound that is one of titanium nitride, tantalum nitride, tungsten nitride, titanium aluminum nitride, tantalum aluminum nitride, tungsten aluminum nitride, titanium silicon nitride, tantalum silicon nitride, tungsten silicon nitride and a conductive oxide of one of Ru, Rh, Os and Ir.

37. The transistor of claim 35, further comprising a metal gate formed by plating a metal on the barrier metal film.

38. The transistor of claim 34, wherein: the gate dielectric includes plural dielectric mono-layers; and each dielectric mono-layer comprises a compound that is one of AI2O3,

TiO , HfO₂, CeO₂, ZrO₂, Ta₂O5 and an oxide of one of Li, Be, Na, Mg, K, Ca, Sc, V,

Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Rb, Sr, Y, Nb, Mo, Tc, Pd, Ag, Cd, In, Sn, Sb, Cs, Ba, La, W, Re, Pt, Au, Hg, TI, Pb, Bi, Po, Fr, Ra, Ac, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu and Th.

39. The transistor of claim 38, further comprising a barrier metal film formed on the gate dielectric, wherein: the barrier metal film includes plural metal film mono-layers formed by atomic layer deposition; and each metal film mono-layer comprises a compound that is one of titanium nitride, tantalum nitride, tungsten nitride, titanium aluminum nitride, tantalum aluminum nitride, tungsten aluminum nitride, titanium silicon nitride, tantalum silicon nitride, tungsten silicon nitride and a conductive oxide of one of Ru, Rh, Os and Ir.

40. A capacitor comprising: a de-oxidized surface of one of a trench formed in a substrate and a stack formed on the substrate, the de-oxidized surface formed by using atomic layer removal of at least one oxide mono-layer; and a capacitor dielectric formed by using atomic layer deposition of at least one dielectric mono-layer on the de-oxidized surface.

41. The capacitor of claim 40, further comprising a barrier metal film formed on the capacitor dielectric.

42. The capacitor of claim 41 , wherein: the barrier metal film includes plural metal film mono-layers formed by atomic layer deposition; and each metal film mono-layer comprises a compound that is one of titanium nitride, tantalum nitride, tungsten nitride, titanium aluminum nitride, tantalum aluminum nitride, tungsten aluminum nitride, titanium silicon nitride, tantalum silicon nitride, tungsten silicon nitride and a conductive oxide of one of Ru, Rh, Os and Ir.

43. The capacitor of claim 41, further comprising a metal gate formed by plating a metal on the barrier metal film.

44. The capacitor of claim 40, wherein: the capacitor dielectric includes plural dielectric mono-layers; and each dielectric mono-layer comprises a compound that is one of Al₂O3,

TiO₂, HfO₂, Ceθ2, ZrO₂, Ta₂O₅ and an oxide of one of Li, Be, Na, Mg, K, Ca, Sc, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Rb, Sr, Y, Nb, Mo, Tc, Pd, Ag, Cd, In, Sn, Sb, Cs, Ba, La, W, Re, Pt, Au, Hg, TI, Pb, Bi, Po, Fr, Ra, Ac, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu and Th.

45. The capacitor of claim 44, further comprising a barrier metal film formed on the capacitor dielectric, wherein: the barrier metal film includes plural metal film mono-layers formed by atomic layer deposition; and each metal film mono-layer comprises a compound that is one of titanium nitride, tantalum nitride, tungsten nitride, titanium aluminum nitride, tantalum aluminum nitride, tungsten aluminum nitride, titanium silicon nitride, tantalum silicon nitride, tungsten silicon nitride and a conductive oxide of one of Ru, Rh, Os and Ir.

46. A method of forming a metal oxide mono layer on a substrate, comprising: introducing separate pulses of metal alkyl amide and ozone reactants into a reaction chamber containing a substrate where said metal alkyl amide is comprised of:

lr»2

M(NR¹R^z)n

where M is a Group IV metal; n is 4; and R¹ and R², independently, are comprised of alkyls, where said alkyls may be any one of or combination of: substituted, unsubstituted, linear, branched and cyclic.

47. The method ofclaim 46 where R¹ and R² are individually comprised of a CI - C6 alkyl.