DRAM CAPACITOR WITH ULTRA-THIN NITRIDE LAYER FIELD OF THE INVENTION
The present invention relates generally to fabrication of semiconductor devices, and specifically to high-density DRAM devices.
BACKGROUND OF THE INVENTION
The density of dynamic random-access memory (DRAM) continues to increase, thanks to advances in memory cell structure and production technology. Gigabit DRAM d vices are expected to enter the market within the next few years, based on feature sizes of 0.15 μm and below.
One of the key challenges associated with increasing DRAM cell density is to maximize the charge storage capacity of the cells, while minimizing leakage current. A typical DRAM cell contains a capacitor made up of a storage node, acting as a lower conductive plate, and a conductive upper plate. The plates are separated by a dielectric layer. In order to increase the capacitance, it is necessary to maximize the effective areas of the plates, while minimizing the thickness of the dielectric layer. A variety of cell designs have been developed to meet these criteria. The most common designs are categorized generally as trench capacitor (TRC) and stack capacitor (STC) types. These designs are surveyed in an article by Nitayama, et al., entitled "Future Directions for DRAM Memory Cell Technology," in IEDM Technical Digest (IEEE, 1998), pp. 355-
358, which is incorporated herein by reference.
State-of-the-art STC devices use hemispherical grain silicon (HSG) storage nodes, covered by a relatively thick (>50A) dielectric layer of nitride or tantalum oxide (TA2O5). A scheme of this sort with 0.15 μm feat ire size is described, for example, by Chum, et al., in an article entitled "A New DR-. -M Cell Technology Using Merged Process with Storag . Node and Memory Cell Contact for 4Gb DRAM and Beyond," in IEDM Technical Dige st (IEEE, 1998), pp. 351-54, which is incorporated herein by reference. Looking ahead to future generations, with feature sizes of 0.13 μm and below, the dielectric material used in stack capacitors must meet the requirements of high dielectric constant and low leakage current (<108 A/cm2), with good step coverage over the HSG and other elements of the capacitor structure. The thickness of the dielectric layer should be less than 5θA. Nitride dielectric cannot be made to meet these requirements using current furnace technology. New materials, such as TA2O5 and BST, may offer an alternative, but will require substantial further development before they can be used in production.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an improved method for production of thin dielectric layers.
It is a further object of some aspects of the present invention to provide an improved process for producing stack and trench capacitors used in DRAM devices.
In preferred embodiments of the present invention, a DRAM device comprises a capacitor, preferably a stack capacitor (STC) structure, most preferably comprising
HSG, which is covered by an ultra-thin nitride layer. Alternatively, the capacitor may comprise a trench capacitor structure. The nitride layer is formed by chemical vapor deposition (CVD), using a novel process implemented in a single-wafer CVD chamber.
The process enables the layer to be formed with a thickness below 5θA, while maintaining good step coverage and low leakage current. It thus meets the needs of gigabit DRAM devices with feature sizes of 0.15 μm and below. The present invention will be more fully understood from the following detailed
description of the preferred embodiment thereof, taken together with the drawings in which: BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic, sectional illustration of a DRAM cell, in accordance with a preferred embodiment of the present invention; and
FIG. 2 is a flow chart that schematically illustrates a process for producing a thin dielectric layer in a DRAM device, in accordance with a preferred embodiment of the present invention. DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT
FIG. 1 is a schematic, sectional illustration of a DRAM cell 20, in accordance with a preferred embodiment of the present invention. The cell comprises a silicon substrate 22, on which a storage node 24 is formed. Preferably, the storage node comprises hemispherical grain silicon (HSG), as described, for instance, in the above- mentioned article by Chun, et al. The shape of storage node 24 in the FIG. 1 is shown only by way of example, and substantially any suitable shape known in the art may be used. The storage node is covered by an ultra-thin nitride layer 30, preferably less than 5θA thick, which is formed using a process described hereinbelow. A conductive plate 28 is formed over layer 30. Plate 28 and storage node 24 thus constitute the plates of a stack capacitor (STC), which are separated by the dielectric nitride layer 30. The capacitor is charged and discharged via a word line 26, as is known in the art.
FIG. 2 is a flow chart that schematically illustrates a process for producing ultra- thin nitride layers, such as layer 30, in accordance with a preferred embodiment of the present invention. At an initial step 40, STC storage nodes, such as node 24, are formed on a silicon wafer using processes known in the art. The nodes preferably comprise HSG, as noted above. The wafer is then transferred to a CND chamber in a single-wafer cluster tool, such as IΝTEGRAPRO, produced by STEAG CND Systems, in order to produce the nitride layer. The same cluster tool can also be used to form the storage nodes at step 40. In this case, the wafer can be transferred directly within the cluster tool from the node formation stage to the nitride layer formation stage, either under vacuum or in an atmospheric environment.
At a cleaning step 42, the wafer is optionally cleaned in situ. Any suitable method known in the art can be used for this purpose, including either dry or wet cleaning, or a combination of the two.
A seed layer is formed on the surface of node 24, at a seed formation step 44. This step is carried out using one or more of the following techniques:
• High- vacuum reactive gas seed flow. • Reactive gas flow, using chlorine gas, for example, under ultraviolet
(UV) illumination. This technique can be carried out either in the CND chamber or in a separate, dedicated surface conditioning chamber.
• Growth of a very thin layer of silicon nitride, with high step coverage, using dichlorosilane (DCS) and/or disilane chemistry and ΝH3, using CVD or, in particular, rapid thermal CVD (RTCVD).
• Plasma-enhanced growth of a thin nitride layer of N2 and/or atomic N*", using a remote or local plasma.
The seed layer is used as a base for CVD growth of a thin nitride layer, to serve as the bulk nitride layer 30, at a nitride layer growth step 46. The layer is preferably grown using silane, disilane or DCS chemistry, in a RTCVD and or CVD process with susceptor heating.
Optionally, at an annealing step 48, thin nitride layer 30 is annealed at high temperature under NH3 or N2, preferably using a rapid thermal processing (RTP) technique, in order to harden the layer. At a further optional post-treatment step 50, the wafer is treated under high temperature using NO and/or N2O gas. The DRAM production process then continues with the formation of upper plate 28 and other steps, as are known in the art.
It will be appreciated that the preferred embodiments described above are cited by way of example, and that the present invention is not limited to what has been particularly shown and described hereinabove. Rather, the scope of the present invention includes both combinations and subcombinations of the various features described hereinabove, as well as variations and modifications thereof which would occur to persons skilled in the art upon reading the foregoing description and which are not disclosed in the prior art.