INTEGRATED CIRCUIT ATTACHMENT PROCESS AND APPARATUS
CROSS-REFERENCE TO RELATED APPLICATION This application claims the benefit under 35 U.S.C. § 119(e) of U.S. Provisional Application Number 60/093,088, filed on July 16, 1998, which application is specifically incorporated by reference herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to radio frequency identification (RFID) systems, and more specifically to RFID systems having an improved form factor.
2. Description of Related Art
In the automatic data identification industry, the use of RFID transponders (also known as RFID tags) has grown in prominence as a way to track data regarding an object to which an RFID transponder is affixed. An RFID transponder generally includes a semiconductor memory in which information may be stored. An RFID interrogator containing a transmitter- receiver unit is used to query an RFID transponder that may be at a distance from the interrogator. The RFID transponder detects the interrogating signal and transmits a response signal containing encoded data back to the interrogator. RFID systems are used in applications such as inventory management, security access, personnel identification, factory automation, automotive toll debiting, and vehicle identification, to name just a few.
Such RFID systems provide certain advantages over conventional optical indicia recognition systems (e.g., bar code symbols). For example, the RFID transponders may have a memory capacity of several kilobytes or more, which is substantially greater than the maximum amount of data that may be contained in a bar code symbol. The RFID transponder memory may be re-written with new or additional data, which would not be possible with a printed bar code symbol. Moreover, RFID transponders may be readable at a distance without requiring a direct line-of-sight view by the interrogator, unlike bar code symbols that must be within a direct line-of-sight and which may be entirely unreadable if the symbol is obscured or damaged. An additional advantage of RFID systems is that several RFID transponders may be read by the interrogator at one time.
As generally known in the art, an RFID tag or transponder may comprise a semiconductor chip and an antenna mounted to a substrate. This substrate may be enclosed (e.g., encapsulated, laminated, etc.) so that it is protected from the environment. It is known in the art to provide an RFID tag having a thin form factor, such as disclosed in U.S. Patent No. 5,528,222 issued to Moskowitz et al. For example, as shown in FIG. 1 , a prior art RFID tag 100 may include an RF circuit chip 102 which is mounted in a flexible substrate 104. The chip 102 has electrical contacts 112 that are bonded at bond points 114 to an antenna 106 contained on the substrate 104. A window 108 is formed in the substrate 104 allowing the insertion of the chip 102 therein so that the thickness of the substrate 104 is not added to the thickness of the chip 102. The window 108 allows coating of the chip 102 with an encapsulant 110. The encapsulant 110 protects the chip 102 and the associated bonding structure 112, 114 from environmental exposure. The RFID tag 100 is sealed by thin flexible laminations 116 comprising an inner coating of hot melt adhesive 118 (such as ethyl-vinyl- acetate (EVA), phenolic butyral, or silicone adhesive) and an outer coating of tough polymeric material 120 (such as polyester, polyimide, or polyethylene). The antenna 106 (such as a resonant dipole, loop or folded dipole) is integrally formed on the substrate 104.
More particularly, the antenna 106 may comprise thin (e.g., 25 to 35 microns) copper lines which are etched onto a copper/organic laminate substrate or plated onto an organic substrate with a thickness (s). Typical materials used are polyester or polyimide for the organic substrate 104 and electroplated or rolled annealed copper for the antenna 106. The copper may further include gold and nickel plating to facilitate bonding. The chip 102 has a thickness (w), which may range from approximately 174 to 400 microns. In general, semiconductors are manufactured on thick wafers, e.g., up to 1 mm thick. The semiconductor may be made thinner by polishing or back grinding the wafer after manufacture. In the exemplary prior art RFID tag 100 of FIG. 1 , the substrate 104 has a thickness (v) of approximately 225 microns or less, the bonding structure 112, 114 has a thickness (m) of approximately 50 microns, the laminating materials 116 have a thickness (u, q) of approximately 50 to 125 microns per side, and the encapsulate 110 above the antenna 106 and the substrate 104 has a thickness (r) of approximately 50 microns. Thus, the total thickness (t) of the prior art RFID tag 100 ranges from approximately 500 to 750 microns.
It is desirable to embed thin, flexible RFID tags in labels in both laminated and printed forms. Applications for such labels may include luggage or shipping tags used by airlines or other shippers to track the transportation of luggage and other packages or objects, wrist-band identification bracelets for tracking the movement of patients in a hospital, or animal collars for tracking the movement of animals such as household pets, farm animals, and the like. It is further desirable to use such labels in existing printers wherein the label embedded with the RFID tag is printed with indicia such as a barcode, alphanumeric characters or the like. While the prior art RFID tags described above already provide a thin form factor, the market continues to present packaging challenges to satisfy the demand for faster, smaller, and less expensive products. Accordingly, it is highly desirable to further reduce the form factor of an RFID tag.
SUMMARY OF THE INVENTION Accordingly, the present invention is directed to packaging processes that provide RFID tags having reduced form factors and improved electrical performance. Moreover, the present invention provides RFID tags having both electrostatic discharge protection (ESD) and environmental protection in a thin form factor. In a first embodiment of the invention, a radio frequency transponder comprises a substrate layer having an electrically conductive material disposed thereon, and a superstrate layer disposed above the substrate layer and having an integrated circuit retention aperture. The superstrate layer is laminated to the substrate layer and substantially covers the electrically conductive material on the substrate layer. An integrated circuit is substantially retained within the integrated circuit retention aperture and is operatively connected to the electrically conductive material. The substrate and superstrate layers may each be comprised of an organic material. The electrically conductive material comprises a metal patterned to provide an antenna. An encapsulant material is disposed within the integrated circuit retention aperture to substantially enclose the integrated circuit therein.
In a second embodiment of the invention, a radio frequency transponder comprises a substrate layer having an electrically conductive material disposed thereon and an integrated circuit retention aperture, a first superstrate layer disposed above the substrate layer and also having a integrated circuit retention aperture, and a second superstrate layer disposed below the substrate layer. The integrated circuit retention aperture of the substrate layer is disposed in substantial registration with the integrated circuit retention aperture of the first superstrate layer. The first and second superstrate layers are laminated together to provide a seal around the substrate layer. An integrated circuit is substantially retained within the integrated circuit retention apertures and is operatively connected to the electrically conductive material. An encapsulant is disposed within the integrated circuit apertures substantially enclosing the integrated circuit therein. The substrate layer may be comprised of a glass fabric impregnated with resin, and the superstrate layers may each be comprised of an organic material.
In a third embodiment of the invention, a radio frequency transponder comprises a substrate layer having an electrically conductive material disposed thereon and an integrated circuit retention aperture, and a superstrate layer disposed below the substrate layer. The substrate and superstrate layers are laminated together. An integrated circuit is substantially retained within the integrated circuit retention aperture and is operatively connected to the electrically conductive material. An encapsulant is disposed within the integrated circuit aperture substantially enclosing the integrated circuit therein. The conductive material disposed on the substrate layer may be coated with an insulating material, such as a solder mask. The substrate layer may be comprised of a glass fabric impregnated with resin, and the superstrate layer may be comprised of an organic material.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention claimed. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate an embodiment of the invention and together with the general description, serve to explain the principles of the invention.
BRIEF DESCRIPTION OF THE DRAWINGS The numerous objects and advantages of the present invention may be better understood by those skilled in the art by reference to the accompanying figures in which:
FIG. 1 is a cross-sectional side elevational view showing a typical prior art thin RFID tag;
FIG. 2 is an isometric exploded view of an RFID tag including a perforated substrate according to a first embodiment of the present invention;
FIG. 3 is a cross-sectional side elevation view of the RFID tag of FIG. 2;
FIG. 4 is an isometric exploded view of an RFID tag including a chip- in-cavity structure according to a second embodiment of the present invention; FIG. 5 is a cross-sectional side elevational view of the RFID tag of FIG. 4;
FIG. 6 is an isometric exploded view of an RFID tag including a chip- in-cavity structure according to a third embodiment of the present invention; FIG. 7 is a cross-sectional side elevational view of the RFID tag of
FIG. 6; and
FIG. 8 is a highly diagrammatic, isometric view of an exemplary process of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
The present invention satisfies the critical need for an RFID tag having a reduced form factor. In the detailed description that follows, it should be appreciated that like element numerals are used to describe like elements illustrated in one or more of the aforementioned figures. Referring first to FIGS. 2 and 3, an RFID tag 10 having a chip-in- cavity (CIC) package constructed in accordance with a first embodiment of the invention is illustrated. The RFID tag 10 includes a substrate 12 and an upper superstrate 18 each comprised of an organic material such as polyimide or polyester. The substrate 12 includes an antenna 14 laminated thereon using a material having sufficiently high electrical conductivity, such as a metallic material comprising copper (Cu) or aluminum (Al). As known in the art, the antenna 14 may be patterned on the substrate 12 utilizing a photolithographic, ion etching, chemical etching, or vapor deposition process. The upper superstrate 18 includes an aperture 20 having a size and shape adapted to accommodate an integrated circuit 16 (described below). The upper superstrate 18 is then laminated on top of the substrate 12. Prior to this lamination step, any exposed metallic material may be selectively plated with, for example, electroless nickel (Ni) or gold (Au) in order to provide metallurgy, where needed, to facilitate electrical coupling between the antenna 14 and the integrated circuit 16 using known techniques, such as wire-bonding, tape automated bonding (TAB), or solder reflow. Alternatively, where for example, the antenna 14 is comprised of copper (Cu), the copper traces may also be plated before the upper superstrate 18 is applied to the substrate 12. While the antenna 14 illustrated in FIG. 2 may be recognized as being a dipole antenna, it should be appreciated that other known types of antenna may be patterned on the substrate 12, such as a loop or folded dipole.
Once the substrate 12 and upper superstrate 18 have been laminated together, the integrated circuit 16 is operatively attached to the antenna 14, such as using bonds 22 (see, for example United States Patent No. 5,528,222, incorporated by reference herein). An encapsulating material 24, such as an epoxy, is then utilized to seal the integrated circuit 16 and protect the operative wire bonds 22. Preferably the aperture 20 in the upper superstrate 18 is slightly larger than the integrated circuit 16 so as to provide an annular space for the encapsulating material 24 to flow around the perimeter of the integrated circuit 16 (as shown in FIG. 3). The upper superstrate 18 serves as a mask for the substrate 12 in the process of selective plating onto the substrate 12 and/or shaping the encapsulating material 24. Moreover, the upper superstrate 18 serves to enhance protection of the RFID tag 10 from electrostatic discharge (ESD), moisture and other environmental hazards, and assists in controlling the shape of the encapsulating material 24.
FIGS. 4 and 5 illustrate an RFID tag 10' having chip-in-cavity (CIC) packaging constructed in accordance with a second embodiment of the present invention. The RFID tag 10' includes a substrate 32 comprised of either a flexible material such as described above, or a less flexible material such as a glass fabric impregnated with a resin (usually epoxy) generally used in the fabrication of printed circuit boards (e.g., FR-4) or ceramic. The substrate 32 includes an antenna 14 laminated thereon in the same manner as described above. An upper superstrate 18 and a lower superstrate 28 are each comprised of organic materials, such as described above. The upper superstrate 18 includes an aperture 20 having a size and shape adapted to accommodate an integrated circuit 16, as also described above. The substrate 32 further includes an aperture 26 similar in shape and orientation as the aperture 20 of the upper superstrate 18, but slightly larger in dimensions. The aperture 26 of the substrate 32 is disposed in substantial alignment with the aperture 20 of the upper superstrate 18. The RFID tag 10' further includes a lower superstrate 28 disposed below the substrate 32. The upper superstrate 18 and lower superstrate 28 are laminated together to hermetically seal the substrate 32 therein. An edge seal 30 is defined around the periphery of the upper and lower superstrates 18, 28 where the superstrate layers come into contact with each other (see FIG. 5). As described above, any exposed metallic material may be selectively plated with, for example, electroless nickel (Ni) or gold (Au) in order to provide metallurgy to permit coupling of the antenna 14 with the integrated circuit 16, such as using wire-bonding, tape automated bonding (TAB), or solder reflow techniques. Alternatively, where for example, the antenna 14 is comprised of copper (Cu), the copper traces may also be plated before the upper and lower superstrates 18, 28 are applied to the substrate 32. As noted above, FIG. 4 illustrates the antenna 14 as being a dipole antenna, but it should be appreciated that any known type of antenna may be advantageously utilized. Once the upper and lower superstrates 18, 28 are laminated together to enclose the substrate 32, the integrated circuit 16 is placed on the lower superstrate 28 and is operatively attached to the antenna 14, such as using bonds 22. An encapsulating material 24, such as an epoxy, is then utilized to seal the integrated circuit 16 and protect the operative wire bonds 22. Preferably the apertures 20, 26 are slightly larger than the integrated circuit 16 so as to provide an annular space for the encapsulating material 24 to flow around the perimeter of the integrated circuit 16 (as shown in FIG. 5). As described above, the upper superstrate 18 serves as a mask for the substrate 32 in selectively plating onto the substrate and/or shaping the encapsulating material 24. Moreover, the upper and lower superstrates 18, 28 serve to enhance protection of the RFID tag 10' from electrostatic discharge (ESD), moisture and other environmental hazards, and assists in controlling the shape of the encapsulating material 24.
FIGS. 6 and 7 illustrate an RFID tag 10" having chip-in-cavity (CIC) packaging constructed in accordance with a third embodiment of the present invention. The RFID tag 10" includes a substrate 32 comprised of either a flexible material such as described above, or a less flexible material such as a glass fabric impregnated with a resin (usually epoxy) generally used in the fabrication of printed circuit boards (e.g., FR-4) or ceramic. The substrate 32 includes an antenna 14 laminated thereon in the same manner as described above. A lower superstrate 28 is comprised of organic materials, such as described above. The substrate 32 includes an aperture 26 having a size and shape adapted to accommodate an integrated circuit 16, as also described above.
Unlike the preceding embodiment, an upper superstrate is not included in this embodiment. Instead, the antenna 14 is coated with an insulating material, such as a solder mask comprised of polymer materials. The substrate 32 and the lower superstrate 28 are then laminated together. Any unmasked metallic material may be selectively plated with electroless nickel (Ni) or gold (Au) in order to provide metallurgy to permit coupling of the antenna 14 with the integrated circuit 16, such as using wire-bonding, tape automated bonding (TAB), or solder reflow techniques. Alternatively, where for example, the antenna 14 is comprised of copper (Cu), the copper traces may also be plated. As noted above, FIG. 6 illustrates the antenna 14 as being a dipole antenna, but it should be appreciated that any known type of antenna may be advantageously utilized.
Thereafter, the integrated circuit 16 is placed on the lower superstrate 28 and is operatively attached to the antenna 14, such as using bonds 22. An encapsulating material 24, such as an epoxy, is then utilized to seal the integrated circuit 16 and protect the operative wire bonds 22. Preferably the aperture 26 is slightly larger than the integrated circuit 16 so as to provide an annular space for the encapsulating material 24 to flow around the perimeter of the integrated circuit 16 (as shown in FIG. 7). As described above, the lower superstrate 28 serves to enhance protection of the RFID tag 10" from electrostatic discharge (ESD), moisture and other environmental hazards, and assists in controlling the shape of the encapsulating material 24. FIG. 8 illustrates a process for fabricating RFID tags 10' in accordance with the embodiment of the present invention described above with respect to FIGS. 4 and 5. The exemplary process is used to fabricate a reel 40 of finished RFID tags 10', which may be indexed with indexing sprocket holes. For specific applications, such as insertion into labels, such a process is advantageous in a high speed automated processing system. Even though the following process is described in connection with RFID tags 10' as illustrated in FIGS. 4 and 5, it should be appreciated that a similar process may be used to fabricate RFID tags 10 as illustrated in FIGS. 2 and 3, and RFID tags 10" as illustrated in FIGS. 6 and 7. In addition, it should also be appreciated that a similar process can be used to fabricate RFID tags 10, 10', 10" in finished formats other than reels, such as sheets, panels, etc.
In the automated process of FIG. 8, the upper and lower superstrates 18, 28 and substrate 32 are laminated together to provide a continuous web (such as a 35 mm film strip format or the like), with sprocket holes defined along outer edges of the web. As described above, the substrate 32 includes an antenna 14 formed from electrically conductive materials and an aperture 26, and the upper superstrate 18 includes an aperture 20 disposed in substantial alignment with the aperture 26. More particularly, the lower superstrate 28 may be provided first as a base layer, with the substrate 32 deposited onto the lower superstrate. The antenna 14 may then be patterned onto the exposed substrate 32. Next, the upper superstrate 18 is deposited onto the substrate 32, and the three successive layers are laminated together to form a single web of material. An integrated circuit 16 may then be placed (via suitable automation apparatus 34) within the apertures 20, 26 and electrically connected to the antenna 14. An encapsulant 24 may then be applied (via suitable automation apparatus 36), which flows around the integrated circuit 16. Upon curing of the encapsulant 24, the continuous reel 40 may be segmented into individual RFID tag products. It is believed that the integrated circuit attachment process and apparatus of the present invention and many of its attendant advantages will be understood by the foregoing description, and it will be apparent that various changes may be made in the form, construction and arrangement of the components thereof without departing from the scope and spirit of the invention or without sacrificing all of its material advantages. The form herein before described being merely an explanatory embodiment thereof, it is the intention of the following claims to encompass and include any such changes.