METHOD AND APPARATUS FOR REDUCING INTERMODU ATION DISTORTION
Technical Field
This invention relates generally to the field of radio communication, and more particularly to a radio receiver having improved intermoduiation and sensitivity.
Background Art
In a radio receiver, a received signal is often preamplified in a preamplifier stage. Saturation of the preamplifier stage under strong signal conditions typically increases noniinearities in the preampllfication thereby increasing intermoduiation (IM). Also, strong signals at the preamplifier stage of a receiver can cause the preamplifier to oscillate, even though the preamplifier has been designed to satisfy a stability criteria under low level signal conditions. In attempting to eliminate the strong signal instability issues, optimization of small signal noise figure, gain, and input and output match are usually sacrificed, which degrades the receiver's sensitivity.
In order to minimize the problems associated with strong signal conditions, an automatic gain control (AGC) circuit may be used in conjunction with the preamplifier stage. Some AGC circuits provide a constant amplitude at the output of the preamplifier stage, by feeding back a control signal proportional to the preamplifier's signal output. However, the use of a preamplifier stage having this type of AGC circuit does not compensate for variations occurring in the subsequent stages of the receiver, such as mixers, and IF amplifiers. Accordingly, a need exists for a receiver capable of preamplification without degrading IM performance.
Summary of the Invention
Accordingly, it is an object of the present invention to provide a receiver having improved intermoduiation, and sensitivity.
It is another object of the present invention to provide a receiver having reduced current drain.
Briefly, according to the invention, a radio receiver is provided comprising a RF amplifier stage that varies the gain of the amplifier in response to a control signal. The control signal is preferably proportional to the received signal strength. The preamplifier stage also includes means for bypassing the amplifier when the gain of the amplifier is reduced to zero. When the amplifier stage is by passed, it may be inactivated or shut down so as to save reduce current drain in the radio receiver.
Brief Description of the Drawings
Figure 1 is block diagram of a radio receiver according to the present invention. FIG 2a is block diagram of the 2nd IF amplifier stage of the receiver of FIG. 1.
FIG 2b is block diagram of the limiter stage of the receiver of FIG. 1.
Figure 3 is schematic diagram of the RF preamplifier stage of the receiver of Figure 1. Detailed Description of the Preferred Embodiment
Referring to Figure 1 , a block diagram of a double conversion FM receiver 100 is shown. The receiver 100 is preferably used in a portable two-way radio (not shown), and although a double conversion FM receiver is well known in the art, the stages and operation of the receiver 100 will be briefly described. In the preferred embodiment, the receiver 100 may be tuned to operate over the 935-941 MHZ band. Operationally, a signal received at the antenna 10 is coupled to a 2-pole filter 15. The 2-pole filter 15 provides the initial receiver selectivity, and produces a RF IN signal 17 proportional to the received signal. The RF IN signal 17 is applied to a preamplifier stage 20. As will be described latter, the preamplifier stage 20 may provide gain or may attenuate the received signal. An RF OUT signal 19, proportional to received signal, is provided by the preamplifier stage.20, and is applied to a 3-pole filter 25 to provide additional receiver selectivity. The 2-pole filter 15 and 3-pole filter 25 may be of any suitable type, such as, well known high Q dielectric resonator filters. The output of the 3-pole filter 25 and a 1 st LO signal 31 are applied to a 1st mixer 30, and provides a 1st IF signal 41 at 39.15 MHZ. A 1st local oscillator source 35 provides the 1st LO signal, and may comprise a channel element (resonator) or may be a part of a phase locked loop frequency synthesizer. The 1st LO source is tuned to a proper frequency, so as to provide the proper 1st IF signal 41 when mixed with the RF OUT signal 19. The 1st mixer 30 may be of any suitable type having a non-liner characteristic. The output of the 1st mixer 30 is coupled to a first IF stage 40, which includes a 1st IF filter 42 and a 1 st IF amplifier 44. The 1 st IF filter 42 of the preferred embodiment comprises two 2-pole crystal band pass filters, each centered at the 1st intermediate frequency, and provide selectivity for the first IF stage 40. The output of the 1 st IF filter is amplified by the 1st IF amplifier 44, and is coupled to a 2nd mixer 45. A 2nd LO signal is applied to the 2nd mixer 45 by a 2nd LO source 50, and provides a 2nd IF signal 51 at 450 KHZ. The 2nd IF signal 51 is applied to a 2nd If filter 55, which preferably is a bandpass ceramic filter of suitable type centered at the 2nd intermediate frequency. The output of the 2nd IF filter 55 is amplified by a 2nd IF amplifier 60, and subsequently is limited by a limiter 65. The output of the limiter 65 is coupled to a FM detector 70, which recovers the modulating signal. The modulating signal, after amplification by an audio power amplifier 75, is coupled to a speaker 85. The detector 70, and the audio PA 75 may be of any suitable type, such as those used in the receiver section of a STX portable radio manufactured by Motorola, inc.
Referring to FIG. 2a, the block diagram of the 2nd IF amplifier 60 is shown. The 2nd IF amplifier 60 includes two stages of cascaded amplifiers 61. The output of each amplifier is coupled to an.RF detector 62, and each detector provides a DC signal representing the amplitude or strength of each stage. The detectors 61 may be any suitable RF detectors such as well known full wave or half wave rectifiers. In the preferred embodiment, the detectors 61 comprise temperature compensated full wave rectifiers. The output of the rectifiers 61 are summed by a summer 63, and the output 64 of the summer is a DC signal proportional to the signal strength the 2nd IF signal. Referring to FIG. 2b, a block diagram of the limiter 65 is shown. The limiter 65 includes three cascaded limiting stages 66. The output of the limiting stages 66 are coupled to RF detectors 67, which are similar to RF detectors 62 of FIG. 2a. The DC outputs of the detectors 67 are summed by a summer 68, which provides a DC output 69 proportional to the strength of the 2nd IF signal 51.
Referring again to FIG. 1 , the DC outputs 64 and 69 are coupled to a summer 80, which provides a DC received signal strength indicator (RSSI) output signal 81. Persons of ordinary skill in the art will appreciate that the 2nd If signal strength is proportional to the received signal strength; therefore the RSSI signal 81 is proportional to the received signal strength Accordingly, as the strength of the received signal increases, the RSSI signal 81 will increase. Conversely, as the received signal strength decreases, the RSSI signal 81 will decrease. When each amplification or limiting stage is saturated, a maximum DC voltage will be provided by the RF detector corresponding to that stage, and each subsequent stage will provide additional DC voltage. Each stage will add a DC voltage proportional to its input signal thereby providing a relatively wide dynamic range for the RSSI signal 81. Persons of ordinary skill in the art will appreciate that the summer 80 of FIG. 1 , summer 63 of FIG. 2a, and summer 69 of FIG. 2b may be replaced by a single summer to provide the RSSI signal 81. The RSSI signal 81 is applied to control the gain of the preamplifier stage 20. Accordingly, a negative feed back is provided, such that as the received signal strength is increased, the gain of the preamplifier stage 20 is decreased (even to zero where the preamplifier stage 20 is inactivated and bypassed, as will be described later).
Referring to FIG. 3 the schematic diagram of the preamplifier stage 20 of FIG. 1 is shown. A RF IN signal 17 proportional to the received signal of the receiver 100 of FIG. 1 is applied to an input matching network 211. The input matching network 211 provides the impedance matching to the previous stage to maximize power transfer into the preamplifier 20 (2-pole filter 15 of FIG. 1). The output of the matching network 211 is coupled to the base of an amplifier transistor 230. The output of the transistor amplifier 230 is provided at its collector, which is coupled to an output matching network 240. The output matching network 240 provides for the impedance matching to maximize power transfer to the subsequent stage (3-pole filter 25 of FIG. 1 ). The biasing circuitry for the transistor amplifier 230 includes a resistor 225, coupled between the collector of the transistor amplifier 230 and a supply voltage Vs. The emitter of the transistor amplifier 230 is coupled to ground. Furthermore, a resistor 231 is coupled between the resistor 225 and the emitter of a PNP transistor 220. The collector of the transistor 220 is coupled to the base of the transistor amplifier 230 and a resistor 205 having its second terminal grounded. The base of the transistor 220 is coupled to the RSSI signal 81 through a resistor 215 and an inductor 221 , and a resistor 217 and a capacitor 219 are coupled between the junction 216 and ground. The RSSI signal 81 provides for the controlling the bias of the transistor amplifier 230. As the RSSI signal 81 increases, the emitter voltage of the transistor 220 is increased, which reduces the current through the resistors, 205, 230, and 225. The reduction in current through resistor 205 drops the base voltage of the transistor amplifier 230 causing it to conduct less current, thereby reducing the gain of the transistor amplifier 230. The RSSI signal 81 may reach a level which causes the gain of the preamplifier stage 20 to become zero. At this point, the preamplifier stage 20 is shut down or inactivated, and the transistor amplifier 230 will present a very high impedance to the RF IN signal 17. Accordingly, the RF IN signal 17 bypasses the amplifier 230, and is routed via a inductor 235, and a capacitor 245 to the output matching network 240. The inductor 235, and the capacitor 245 comprise a passive bypass network 250. The transistor amplifier 230 is an active device, which significantly contributes to the generation of IM signals under strong signal condition. Therefore, passively bypassing the transistor amplifier 230 under strong received signal conditions greatly improves the IM performance of the receiver. Additionally, the passive network 250 may include attenuating means, such as a resistor divider to attenuate the received signal, thereby reducing the IM contribution of the subsequent active stages. One of ordinary skill in the art may appreciate that the current drain of the preamplifier stage 20 reduces as the gain of the amplifier transistor 230 is decreased and reaches a minimum level when the preamplifier stage 20 is inactivated. Accordingly, under strong received signal conditions, wherein the preamplifier stage 20 is inactivated, the overall current drain of the receiver 100 is minimized prolonging its battery life.
Since the RSSI signal 81 is provided at the 2nd IF and is fully temperature compensated, the variations of the entire receiver front end are accounted for. Additionally, the stability considerations under strong signal conditions cause sacrificing the gain at low signal levels. Since the gain of the transistor amplifier 230 is reduced under strong signal conditions, the preamplifier stage 20 may be optimized to provide additional gain for low level received signals, thereby improving the receiver sensitivity.
What is claimed is: