A PLANAR TRANSISTOR WITH AN INTEGRATED OVERVOLTAGE GUARD
TECHNICAL FIELD
The present invention relates to a planar transistor with overvoltage protection where the transistor and the overvoltage guard is integrated in the same semiconductor wafer.
BACKGROUND ART
Some transistor circuits, e g Darlington circuits are often used to drive relays and other inductive circuits. The overvoltage which occurs when the current through an inductance is interrupted can then become so high that a collector- emitter is created which damages the transistor. Such circuits must therefore be provided with some sort of protective circuit, which effects leading away the magnetic energy stored in the inductance without dangerous overvoltages occurring.
One known method of providing a transistor with overvoltage protection is to use a Zener diode between the collector and base of the transistor. For a voltage which is lower than the collector-emitter breakdown voltage BV -.-. the diode releases current to the transistor base so that the collector-emitter circuit becomes conductive as long as the overvoltage is present, and looks after the stored energy.
In monolithic integrated circuits it is known to make Zener diodes in the same semi-conductor wafer as the transistor by using base and emitter diffusion techniques. When the breakdown voltage for the barrier layer between these diffusion regions is relatively low (under 10 V) a large number of Zener diodes must be coupled in series for the cases where the collector-emitter distance is constructed for high breakdown voltage. Such an implemention is described in the . Swedish patent 355 105, for example. Already at working voltages of about 100 V, the space requirement for these series-connected Zener diodes becomes embarassing. For transistors of the p-n-p type there is furthermore added the
OMPI need of protective diffusions to prevent channel formation, which further increases the space requirements of the semi-conductor wafer.
The German published patent application No 2 712 218 teaches that the break¬ down voltage of a p-n junction is dependent on the radius of curvature of the junction, so that breakdown takes place at the point where the radius of curvature is least. In this publication it is stated that it is not possible, with the diffusion techniques used, to adjust the breakdown voltages at the p-n junction with sufficient accuracy for it to be practicably usable as a protective diode for the input in an MOS circuit. According to the publication, this problem has been solved by a V-shaped etching and a subsequent epitaxial deposition of a doped layer enabling a defined radius of curvature of the p-n junction. The method used can be applied for the low voltages in the order of magnitude 10 V, which is the case in MOS circuits. The method is troublesome to handle and causes several extra steps in the process, with associated high costs.
It is also known, in semi-conductor circuits intended for high voltages, that there are problems with the contact connection to the base electrodes of the transistors, due to the degree of doping being low at the surface of the*base. For example, aluminium (which is an acceptor) gives rise to a Schottky diode in combination with an n-doped base layer in a p-n-p transistor. When using other contact metals, it may be difficult to provide ohmic contact for n- as well as p-doped layers with a low degree of doping. These problems begin to make themselves felt with transistors which must withstand a voltage of greater than 80 V. It is well known to solve this problem by diffusing in an extra, highly doped region of the same conductivity type under the contact metal as for the semi-conductor region which is to be contacted.
DISCLOSURE OF INVENTION
The problem is to provide overvoltage protection in a planar transistor intended for high voltages, and especially in the final transistor for a Darlington circuit, where the overvoltage guard takes up small space and can be produced without any extra processual steps being required, apart from those used in the normal production of planar transistors for high voltages. Furthermore, it must be easy to control the breakdown voltage. This is achieved in accordance with the invention in the mode apparent from the appended patent claims.
BRIEF DESCRIPTION OF DRAWINGS
The invention will now be described in detail while referring to the appended drawings, where Figure 1 schematically illustrates a plan view of, and Figure 2 a section A-A through a monolithic integrated Darlington circuit of the n-p-n type, while Figure 3 illustrates a principle diagram of this circuit.
Figure 4 schematically illustrates a plan view of, and Figure 5 a section A-A through a monolithic integrated Darlington circuit of the p-n-p type, while Figure 6 is a principal diagram of the same circuit.
MODES FOR CARRYING OUT THE INVENTION
The numeral 15 in Figure 1 denotes a semi-conductor wafer, in this case made from n silicon 16 with an epitaxial n layer 17 having lower doping, which constitutes the common collector with connection 14 for the transistors Tl and T2. In the n layer 17 there are diffused p-doped base layers 18 and 19 for the transistors Tl and T2. The n -emitter layers 20 and 21 are in turn diffused into this base layer. All these layers are made conventionally. In a last step, highly doped p -layers 22 and 23 are diffused into the weakly-doped base diffusions 18 and 19 so that it will be possible to obtain ohmic contact between these layers and the metallic contact connections 24 and 25.
The doping 23 is executed such that the doped region lies partially . within the collector region 17 and partially within the base region 19. Between the collector diffusion and the extra base diffusion there is thus obtained a barrier layer 26, forming the Zener diode Z according to Figure 3, with the biassing direction from base to collector. The diode Z has a breakdown voltage which is set to a desired value by selecting the diffusion conductions conventionally so that a desired radius of curvature is obtained for the barrier layer 26. Since the p diffusion is otherwise hardly critical, there are large opportunities of varying this diffusion to obtain the desired breakdown voltage. The highly doped region 23 may, as illustrated in Figure 23, extend along a limited portion of the interface 27 between base and collector, but the extension can be made large or smaller depending on how good contact is desired with the base and the power resistance of the Zener diode.
As will be seen from Figure 3, the input 11 of the Darlington circuit is connected to the base in the transistor Tl, while the output 14 is connected to the common collector region over the π -diffusion 16. Between the p -region 23, including the transistor T2 base connection and the Zener diode Z anode, and the emitter in the transistor Tl there is a connection 12 formed in the conductive layer of the circuit. The point 13, common to the input and output of the circuit, is connected to the emitter in the transistor T2.
In Figures 4-6 there is illustrated a corresponding Darlington circuit 30 of the p-n-p type. It is built up on a highly-doped substrate 31 of the p type to obtain low collector resistance. On this there is deposited an epitaxial low-doped p layer 32 for the collector. In this case a base layer 33, common to both transistors, and of the n-type (weakly doped) is diffused into the epitaxial collector region 32. The emitters in the .transistors Til and T12 are then diffused into the base layer 33 in the form of annular highly-doped p regions, where the diffusion is made to sUfch a depth that it almost reaches the epitaxial p layer 32. Thus, a portion of the base diffusions 36, 37 will lie inside the annular emitter region, while another portion 38 is outside. Accordingly, so-called pinch resistors Rl and R2 are formed between the inner and outer base regions, and these stabilize the circuit as well as increasing its breakdown voltage. The pinch resistor Rl is between the base 36 of the transistor Til and the base 38 of the transistor T12, the base 38 surrounding the emitter 34 of the transistor Til. The pinch resistor R2 is between the base region 38 and the transistor T12 and the base diffusion 37 situated inside the emitter 35, said diffusion 37 being connected to the emitter 35 in T12 via a contact diffusion 39.
The contact diffusions 40, 41 in the base regions', as well as one contact 39 to the pinch resistor R2 are made simultaneously in an n diffusion. The base contact diffusion 41 is provided over the collector-base barrier layer 42 as in previous cases, but in this case for the whole of its length, so as to form the Zener diode Z1 between the collector and base of the transistor T21. The n diffusion may be also easily selected so that the radius of curvature of the barrier layer will be such as to obtain the desired breakdown voltage.
OMPI A plurality of Darlington circuits according to Figures 4-6 have been manufac¬ tured. The epitaxial layer 17 had a resistivity of 11-13 ohm-cm. The depth of the base diffusion was 5 -um and the extra base diffusion 3 .urn with a superficial resistivity of 2,5 ohm/square. The breakdown voltage between collector and base with floating emitter BV_R_ was 200 V and between collector and emitter with floating base it was 180 V. The Zener guard diode Z' had a breakdown voltage of 160 V. These values are mean values for all Darlington circuits manufactured. There was a variation in the breakdown voltages of about 10% between the different specimens. The variation was entirely parallel for the three above- mentioned breakdown voltages, the safety margin to the breakdown voltages of the Zener diodes thus being maintained. To a great extent, this variation would appear to depend on other factors, e g varying degree of doping in the collector region, than on the difficulty of setting a suitable radius of curvature during the extra base diffusion.
A Darlington circuit in accordance with the invention has a space requirement which is only about 40% of that required for a similar circuit manufactured according to previously known technology with a guard circuit comprising a plurality of series-connected p-n junctions between base and emitter diffusions. This applies to an ordinary circuit where the final transistor Tl, T12 is dimensioned for a collector current of 200 mA. For a smaller final transistor, the reduction in area is even greater, whereby a greater number of circuits can be obtained per silicon wafer and with better yeild.