Peak Tracking Correlator
The present invention relates to data processing apparatus and more particularly to apparatus for tracking the peak of a correlation function between two signals. In many applications, it is necessary to monitor a correlation function between two signals and to determine when the coar-relation function reaches a maximum value. One such application arises in connection with a met,hod of measuring flow in which the flow velocity is determined by identifying the time delay between two related signals, one signal being derived downstream of the flow with respect to the other signal. If the distance between the points of derivation of the two signals is constant, the flow velocity will then be inversely proportional to the identified time delay.
The present invention provides apparatus for tracking the peak of a correlation function between two signals, said apparatus comprising in comlination first correlator means responsive to said signals for providing a coarse measure of the position of said peak, and second correlator means responsive to said signals for tracking said position when said coarse measure corresponds to the tracking range of said second correlator means, said first correlator means being connected to said second correlator means for causing said tracking range to correspond to said coarse measure.
In order that the present invention may be more readily understood, an embodiment thereof will now be described by way of example, with reference to the accompanying drawings, in which:-
Figure la is a schematic diagram showing the relationship between two internal variables of a transport process and their external measureable signals;
Figure lb is a block diagram showing one form of correlation function peak tracking apparatus; Figure 2 is a graphical representation of a coirelation function and its differential with respect to delay time;
Figure 3 is a block diagram showing one embodiment of correlation function peak tracking apparatus incorporating coarse-fine resolution;
Figure 4 is a block diagram showing a modification to the peak tracking apparatus of Figure
3;
Figure 5 is a. schematic diagram showing one example of a word-controlled shift register which may be used in the apparatus oi Figure 3 or 4; and
Figure 6 is a diagram of a flow control system incorporating the apparatus of Figure 3 or 4. Referring to Figure la, there is shown in schematic form the relationship between internal variables, x' and y' of a transport process T(S), and external, measurable signals x and y, Laplace transforms L1(S) and L2(S) act as transfer functions between x' and x, and y' and y respectively. One example of such a transport process occurs in the above-mentioned method of measuring flow. In this case a pipe or conduit 10 contains a flowing medium represented by the arrow 11. Transducers and associated circuits 12 and 13 having transfer functions represented by the Laplace transforms L1(S) and L2(S) produce respective signals x and y derived from flow signals x' and y'.
It can be shown that if the suto-correlation function of x is Rxx(S) and the cross-correlation function between x and y is Ryx(S) ,' then:-
Rxx(S) = L1 (S). L1(-S). Rx,x, (S) and
Ryy(S) = L2(S). T(S). L2(-S).T(-S).Rx,x,(S)
Eliminating Rx,x, (S) gives :-
Thus the effective transfer function relating y to x is
 and therefore
 When both transfer functions L
1 and L
1 are unity,
R
yx(S) = T(S).R
xx(S) ...(2)W h en L
1 = 1 and L
2 =
 (wher
 is the delay time )
R ( S ) =
 . . . ( 3) yx In the time delay domain, this is equivalent to the differentiation of equation (2) with respect to time delay.
Where it is desired to carry out these functions with electronic circuits, an ideal differen- tiator of the sort L
1 = 1 and L
2 =
 need not be  used since L, = 1/ ( 1 + ) and L
0 =
 / U +
 ) are easily implemented using resistance-capicitancc circuits and still give the ratio
 to conform with equation (3) above. The essential features of one form of delay-lock-loop, correlation function peak tracking apparatus are shown in Figure lb. One input signal x(t) is fed through a polarity detector 14 to a shift register (SR) 15 which introduces a delay to the signal. This delayed signal is then fed to one input of a multiplier. A second input signal y(t) is fed through a differentiating circuit 17 to the second input of the multiplier 16. The output of the multiplier 16 is fed through a smoothing circuit l8 which may comprise an RC circuit having a suitable time constant, to an integrator 19 whose output is fed to a voltage controlled oscillator (VCO) 20. The voltage controlled oscillator 20 provides the clock frequency setting the shift register delay

 . If the feedback loop comprising the integrator 19 and VCO 20 is broken and the shift register delay externally controlled by varying its clock frequency, then it can be shown that the differentiation of the signal y(t) results in a voltage variation appearing at the output of the smoothing cxrcuit 18 Which is representative υf the differentiated cross-correlation function R
yx, as the shift register delay is slowly swept through the delay range of the function. The cross-correlation function R
yx and its differential with respect to the delay time are shown graphically in Figure 2.
The differentiated function, illustrated by a broken line, is bipolar and hence the stable operating point of the closed loop negative feedback system will be obtained when the differentiated function equals zero. This point corresponds to the peak of the correlation function Ryx . When the feedback loop is connected as shown in Figure lb, a signal representative of the differentiated function is received at the input of the integrator 19. If this input is at zero, i.e. representative of the peak of the function, the integrator output will be constant; therefore the clock frequency derived from the VCO 20 will also be constant and the negative feedback system will be at its stable operating point. However, a positive or negative input to the integrator 19 will be integrated in time, thus leading to a progressively increasing or decreasing clock frequency to the shift register 15. This in turn will lead to a decreasing magnitude of signal output from the multiplier 16 until the input to the integrator 19 is at zero and the stable operating point of the system has been reached. The clock frequency of the shift register 15 will be inversely proportional to the delay time of the register and hence to the delay time corresponding to the peak of the correlation function. Slow changes of this peak position will therefore be tracked by this apparatus.
Previously proposed differentiation methods have used the difference between two correlation functions, one delayed with respect to the other. The difference signal is proportional to the differentiated coritjLation function. However, since the zero-crossing point of the differentiated function is obtained from the subtraction of parts of the correlation functions substantially less than peak values, the accuracy of the result obtained will be reduced due to noise arising from increased variance as the function magnitude decreases.
Where more rapid changes of peak position are to be tracked, it is an advantage to initially obtain a coarse indication of the peak position. This obviates the need to use the apparatus of
Figure lb in a search mode of operation, which would cause a long time-delay in the response of the syste to large changes of peak position. The use of a coarse peak indicator also removes the possibility that spurious, smaller magnitude peaks will be locke on to before the main peak has been found.
The preferred embodiment of the present invention therefore provides a coarse-fine system approach. A digital correlator with a relatively smalJ number of delay increments will provide a coarse indication of the peak position. This may be used to constrain the peak tracking range of a delay-locked loop to the immediate vicinity of the most significant peak thereby removing the need for a search mode of operation. By using this technique it will be possible to construct correlation functio peak tracking apparatus, e.g. for use in a correlation flowmeter, having a virtually continuous output resolution. Figure 3 shows a block diagram of a complete constxained peak tracking apparatus. Parts of the circuit common to those shown in Figure lb are denoted by like reference numerals. The circuit of Figure 3 includes that of Figure lb with the exception that the shift register 15 is replaced by a word controlled shift register 25 whose delay time is set both by the frequency of tho clock pulses from the VCO 20 as with the shift register 15, and also by having a variable length, or number of stages which is controlled by a signal such as a digital word N fed to a control input of the shift register  A coarse peak detector 26, such as a digital correlator having a relatively small number of delay increments, is arranged to receive the signals x(t) and y(t) and to provide a signal indicative of a coarsely detected peak position. The signal is shown in Figure 3 as taking the form of the digital word N , and this signal is fed to the control input of the shift register 25. The length and hence the delay time of the register is controlled in accordance with this signal, and the preferred arrangement is that the signal controls the length of the shift register to be proportional to the detected coarse peak position. Any one of a variety of conventional correlators which produce a coarse measure of the function peak may be used as the coarse peak detector 26.
The clock frequency F of the shift register 25 is set by the VCO 20 forming part of the delay-lock loop in a similar fashion to that of Figure lb. The integrator 19 provides a signal V
2 representative of the integral of the smoothed signal V
1 , and this integral signal V
2 contols the VCO 20 and hence the clock frequency F
c. The integrator output signal V
2 effectively adjusts the clock frequency F until the signal V
1 is nulled as described above, and then the time delay position of the peak of the function will be given by Time delay =
 For correlation flowmeter applications, an output inversely proportional to time delay is required i.e.
This function may he implemented as shown in Figure 3 by using suitable processing means such as a variable modulus counter circuit 27 having its modulus controlled by the coarse peak indication
Np with the clock frequency Fc as an input. The output frequency is then proportional to flow and this is fed to a frequency to voltage converter (FVC) 28 which produces a voltage V0 proportional to flow. The voltage V0 can be arranged to activate conventional indicating means such as a panel meter, pen recorder or digital read out. Alternatively, if a digital output is required, this may be derived directlyfrom the output of the counter 27.
A further output circuit may be formed as follows. The output from the voltage controlled oscillator 20 is given by
 and K
1 , K
2 and K
3 are constants set by the parameters of the apparatus However the equation for F
c can be rewritten to give
Hence it is possible to form a voltage V
c given by
 gure 4 shows apparatus using a modified output circuit in accordance with the above-described method. The apparatus is similar to that of Figure
3, but the variable modulus counter 27 and the frequency to voltage converter 28 are replaced by a digital to analogue converter (DAC) circuit 29.
The DAC circuit 29 receives the output V2 of the integrator and effectively divides the varying part Vc by the coarse peak indication Np. Since the flow rate is proportional to Fc divided by Np , and Vc is proportional to Fc as shown above, the output V0 of circuit 29 will bo proportional to the flow rate.
Figure 5 shows one example of a word controlled shift register 25 which may be used in the apparatus of Figure 3 or 4. The binary word Np, applied in this case in parallel form, controls logic switches 42, 44, 46 connecting stages 4l, 43, 4-5 respectively of the shift register. When a binary bit of the word Np is one, a shift register stage proportional in length to the binary weighting of the bit is connected into the chain of shift register stages whereas when the bit is zero the stage is by-passed by a short circuit. Therefore, the control input of the logic switch 42 controls the shift register stage (SRS) 4l having unit length, while the switches 44 and 46 respectively control stages 43 and 45 having respectively double and quadruple the lengths of the stage 4l.
The logic switch 42 is shown in greater detail as including AND-gates 47,48, an OR-gate 49 and an inverter 50. Switches 44 and 46 may be constructed in a similar fashion. Upon receipt of a logic one at the control input, AND-gate 47 allows serial data from the stage 41 to pass therethrough and via OR-gate 49 to the subsequent stage 43- The inverter 50 inhibits the AND-gate 48 from providing a by-pass path around the stage 4l. When a logic zero is received at the control input, the states of the AND-gates 47 and 48 are reversed, and the serial data by-passes the stage 4l, thereby shortening the total length of the shift register 25. The total length of the register upon receipt of a control binary word Np is then equal to the product of the  maximum obtainable length of the register and the decimal number corresponding to the binary Np.
Whilst only three stages 4l , 43 and 45 are shown in Figure 5, any desired number may be provided corresponding to the number of bits in the control word Np prodnco.d by the coarse detector 26.
When used for flow measurement applications, the tracking apparatus may be arranged to provide an indication or read-out of flow rate or other derived flow parameter. Alternatively, it may be used in a feedback system as shown in Figure 6 to control the flow. The pipe or conduit 10 contains a flowing medium such as a liquid represented by the arrow 11, and is provided with transducers 12 and 13. The peak tracking apparatus 60, such as shown in Figures 3 or 4, receives flow related signals from the transducers 12, 13 and provides an indication of flow to a control circuit 61. The control circuit
61 is arranged to be responsive to the flow indication from apparatus 60 to activate a flow control mechanism
62 disposed in the path of the flow. Thus, for example, the flow can be maintained constant, or alternatively may be given a maximum limit which may not be exceeded. The flow control mechanism 62 may comprise a valve and/or a pump, and the control circuit 6l may comprise any conventional arrangement such as a comparator which compares the flow indicatio signal with a reference signal and activates the contr mechanism 62 accordingly.