USRE49166E1 - Displays with silicon and semiconducting-oxide top-gate thin-film transistors - Google Patents

Abstract

An electronic device may include a display having an array of display pixels on a substrate. The display pixels may be organic light-emitting diode display pixels, that include hybrid thin-film transistor structures formed using semiconducting-oxide thin-film transistors, silicon thin-film transistors, and capacitor structures. A drive transistor in the display pixel may be a top-gate semiconducting-oxide thin-film transistor and a switching transistor in the display pixel may be a top-gate silicon thin-film transistor. A storage capacitor in the display may include a conductive semiconducting-oxide electrode.

Description

This application claims the benefit of provisional patent application No. 62/476,551, filed on Mar. 24, 2017, and is a reissue of patent application Ser. No. 15/729,330, now U.S. Pat. No. 10,249,695, which is are hereby incorporated by reference herein in its entirety their entireties.

BACKGROUND

This relates generally to electronic devices and, more particularly, to electronic devices with displays that have thin-film transistors.

Electronic devices often include displays. For example, cellular telephones and portable computers include displays for presenting information to users.

Displays such as liquid crystal displays are formed from multiple layers. A liquid crystal display may, for example, have upper and lower polarizer layers, a color filter layer that contains an array of color filter elements, a thin-film transistor layer that includes thin-film transistors and display pixel electrodes, and a layer of liquid crystal material interposed between the color filter layer and the thin-film transistor layer. Each display pixel typically includes a thin-film transistor for controlling application of a signal to display pixel electrode structures in the display pixel.

Displays such as organic light-emitting diode displays have an array of display pixels based on light-emitting diodes. In this type of display, each display pixel includes a light-emitting diode and thin-film transistors for controlling application of a signal to the light-emitting diode.

Thin-film display driver circuitry is often included in displays. For example, gate driver circuitry and demultiplexer circuitry on a display may be formed from thin-film transistors.

If care is not taken, thin-film transistor circuitry in the display pixels and display driver circuitry of a display may exhibit non-uniformity, excessive leakage currents, insufficient drive strengths, poor area efficiency, hysteresis, and other issues.

It is within this context that the embodiments herein arise.

SUMMARY

An electronic device may be provided with a display. The display may have an array of display pixels on a substrate. The display pixels may be organic light-emitting diode display pixels or display pixels in a liquid crystal display.

The display may include a display pixel with at least an organic light-emitting diode (OLED) a semiconducting-oxide thin-film transistor (e.g., a drive transistor), a silicon thin-film transistor (e.g., a switching transistor), and a storage capacitor coupled to the drive transistor. The switching transistor, the drive transistor, and a light-emitting diode may be coupled in series between a positive voltage power supply line and a ground voltage power supply line. In particular, the drive transistor may be a top-gate semiconducting-oxide transistor. The switching transistor may be a top-gate silicon transistor. The storage capacitor may include a conductive semiconducting-oxide as a first electrode.

The silicon switching transistor may be formed on a substrate, and the semiconducting-oxide drive transistor may be formed above the silicon switching transistor. A conductive routing path may couple the silicon switching transistor to the semiconducting-oxide drive transistor. The conductive routing path may be covered by an organic layer formed on the drive transistor. An additional organic layer may be formed on the organic layer. An anode layer of the light-emitting diode may be formed on the additional organic layer.

In an embodiment, an etch-stop liner may be interposed between a source-drain terminal of the semiconducting-oxide drive transistor and a contact of the conductive routing path coupled to the semiconducting-oxide drive transistor.

In an embodiment, a dielectric layer may be formed below the semiconducting transistor, and the conductive semiconducting-oxide of the storage capacitor and semiconducting-oxide material in the drive transistor may be formed on the dielectric layer.

In an embodiment, the silicon switching transistor comprises a gate structure formed in the same layer as a capacitor plate of the storage capacitor.

In an embodiment, a passivation layer is interposed between the conductive path coupling and the organic layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram of an illustrative display such as an organic light-emitting diode display having an array of organic light-emitting diode display pixels or a liquid crystal display having an array of display pixels in accordance with an embodiment.

FIG. 2 is a diagram of an illustrative organic light-emitting diode display pixel of the type that may include an organic light-emitting diode with semiconducting-oxide top-gate thin-film transistors and silicon top gate thin-film transistors in accordance with an embodiment.

FIGS. 3A-3C are diagrams of illustrative top-gate indium gallium zinc oxide (IGZO) transistor structures in accordance with an embodiment.

FIG. 4 is a cross-sectional side view of illustrative pixel circuitry that includes a top-gate IGZO drive transistor of the type shown inFIG. 3A in accordance with an embodiment.

FIG. 5 is a cross-sectional side view of illustrative pixel circuitry that includes a top-gate IGZO drive transistor of the type shown inFIG. 3B in accordance with an embodiment.

FIGS. 6A and 6B are cross-sectional side views of illustrative pixel circuitry that includes a top-gate IGZO drive transistor of the type shown inFIG. 3A and a metal layer that reduces a number of contact holes in a planarization layer in accordance with an embodiment.

FIG. 7 is a cross-sectional side view of illustrative pixel circuitry that includes a top-gate IGZO drive transistor of the type shown inFIG. 3B and a metal layer that reduces a number of contact holes in a planarization layer in accordance with an embodiment.

FIG. 8 is a cross-sectional side view of illustrative pixel circuitry that includes source-drain metal layer formed above a top-gate IGZO drive transistor in accordance with an embodiment.

FIG. 9 is a cross-sectional side view of illustrative pixel circuitry what includes a contact via formed in the same layer as a gate structure of a top-gate IGZO drive transistor in accordance with an embodiment.

FIG. 10 is a cross-sectional side view of illustrative pixel circuitry that includes a protective metal film for contacting source-drain regions of a top-gate IGZO drive transistor in accordance with an embodiment.

FIG. 11 is a cross-sectional side view of illustrative pixel circuitry of the type inFIG. 8 that further includes a passivation layer in accordance with an embodiment.

FIG. 12 is a cross-sectional side view of illustrative pixel circuitry of the type inFIG. 9 that further includes a passivation layer in accordance with an embodiment.

FIG. 13 is a cross-sectional side view of illustrative pixel circuitry of the type inFIG. 10 that further includes a passivation layer in accordance with an embodiment.

DETAILED DESCRIPTION

A display in an electronic device may be provided with driver circuitry for displaying images on an array of display pixels. An illustrative display is shown inFIG. 1. As shown inFIG. 1,display14 may have one or more layers such assubstrate24. Layers such assubstrate24 may be formed from planar rectangular layers of material such as planar glass layers.Display14 may have an array ofdisplay pixels22 for displaying images for a user. The array ofdisplay pixels22 may be formed from rows and columns of display pixel structures onsubstrate24. There may be any suitable number of rows and columns in the array of display pixels22 (e.g., ten or more, one hundred or more, or one thousand or more).

Display driver circuitry such as display driver integratedcircuit16 may be coupled to conductive paths such as metal traces onsubstrate24 using solder or conductive adhesive. Display driver integrated circuit16 (sometimes referred to as a timing controller chip) may contain communications circuitry for communicating with system control circuitry overpath25.Path25 may be formed from traces on a flexible printed circuit or other cable. The control circuitry may be located on a main logic board in an electronic device such as a cellular telephone, computer, set-top box, media player, portable electronic device, or other electronic equipment in which display14 is being used. During operation, the control circuitry may supply display driver integratedcircuit16 with information on images to be displayed ondisplay14. To display the images ondisplay pixels22, display driver integratedcircuit16 may supply corresponding image data to data lines D while issuing clock signals and other control signals to supporting thin-film transistor display driver circuitry such asgate driver circuitry18 anddemultiplexing circuitry20.

Gate driver circuitry18 may be formed on substrate24 (e.g., on the left and right edges ofdisplay14, on only a single edge ofdisplay14, or elsewhere in display14).Demultiplexer circuitry20 may be used to demultiplex data signals from display driver integratedcircuit16 onto a plurality of corresponding data lines D. With this illustrative arrangement ofFIG. 1, data lines D run vertically throughdisplay14. Each data line D is associated with a respective column ofdisplay pixels22. Gate lines G run horizontally throughdisplay14. Each gate line G is associated with a respective row ofdisplay pixels22.Gate driver circuitry18 may be located on the left side ofdisplay14, on the right side ofdisplay14, or on both the right and left sides ofdisplay14, as shown inFIG. 1.

Gate driver circuitry18 may assert gate signals (sometimes referred to as scan signals) on the gatelines Gin display14. For example,gate driver circuitry18 may receive clock signals and other control signals from display driver integratedcircuit16 and may, in response to the received signals, assert a gate signal on gate lines G in sequence, starting with the gate line signal G in the first row ofdisplay pixels22. As each gate line is asserted, the corresponding display pixels in the row in which the gate line is asserted will display the display data appearing on the data lines D.

Display driver circuitry such asdemultiplexer circuitry20 and gateline driver circuitry18 may be formed from thin-film transistors onsubstrate24. Thin-film transistors may also be used in forming circuitry indisplay pixels22. To enhance display performance, thin-film transistor structures indisplay14 may be used that satisfy desired criteria such as leakage current, switching speed, drive strength, uniformity, etc. The thin-film transistors indisplay14 may, in general, be formed using any suitable type of thin-film transistor technology (e.g., silicon-based, semiconducting-oxide-based, etc.).

With one suitable arrangement, which is sometimes described herein as an example, the channel region (active region) in some thin-film transistors ondisplay14 is formed from silicon (e.g., silicon such as polysilicon deposited using a low temperature process, sometimes referred to as LTPS or low-temperature polysilicon) and the channel region in other thin-film transistors ondisplay14 is formed from a semiconducting-oxide material (e.g., amorphous indium gallium zinc oxide, sometimes referred to as IGZO). If desired, other types of semiconductors may be used in forming the thin-film transistors such as amorphous silicon, semiconducting-oxides other than IGZO, etc. In a hybrid display configuration of this type, silicon transistors (e.g., LTPS transistors) may be used where attributes such as switching speed and good drive current are desired (e.g., for gate drivers in liquid crystal diode displays or in portions of an organic light-emitting diode display pixel where switching speed is a consideration), whereas oxide transistors (e.g., IGZO transistors) may be used where low leakage current is desired (e.g., in liquid crystal diode display pixels and display driver circuitry) or where high pixel-to-pixel uniformity is desired (e.g., in an array of organic light-emitting diode display pixels). Other considerations may also be taken into account (e.g., considerations related to power consumption, real estate consumption, hysteresis, etc.).

Oxide transistors such as IGZO thin-film transistors are generally n-channel devices (i.e., NMOS transistors). Silicon transistors can be fabricated using p-channel or n-channel designs (i.e., LTPS devices may be either PMOS or NMOS). Combinations of these thin-film transistor structures can provide optimum performance.

Embodiments below may be described with organic light-emitting diode technology as an example. However, if desired these embodiments may also be applied to liquid crystal display technology

In an organic light-emitting diode display, each display pixel contains a respective organic light-emitting diode. A schematic diagram of an illustrative organic light-emittingdiode display pixel22 is shown inFIG. 2. As shown inFIG. 2,display pixel22 may include light-emittingdiode26. A positive power supply voltage Vdd may be supplied to positivepower supply terminal34 and a ground power supply voltage Vss may be supplied to groundpower supply terminal36. The state ofdrive transistor28 controls the amount of current flowing throughdiode26 and therefore the amount of emitted light40 fromdisplay pixel22.

To ensure thattransistor28 is held in a desired state between successive frames of data,display pixel22 may include a storage capacitor such as storage capacitor Cst. The voltage on storage capacitor Cst is applied across the gate and source terminals oftransistor28 to controldrive transistor28, thereby controlling the amount of current flowing through light-emittingdiode26.

Pixel22 may also include switching transistor30 (sometimes referred to herein as enable transistor30).Transistor30 may be coupled between positivepower supply terminal34 and drivetransistor28. An enable signal may be coupled to the gate terminal oftransistor30 to further control the current flow frompositive supply terminal34 to light-emittingdiode26.

Pixel22 may further include additional circuitry as indicated byellipses200. In particular,pixel22 may include an additional switching transistor (distinct from switching transistor30) that loads data into storage capacitor Cst. As an example, the additional switching transistor may be controlled by gate line G (as shown inFIG. 1) and may convey information from data line D (shown inFIG. 1) to storage capacitor Cst. When the switching transistor is off, data line D is isolated from storage capacitor Cst and the gate voltage oftransistor28 is equal to the data value stored in storage capacitor Cst (i.e., the data value from the previous frame of display data being displayed on display14). When gate line G (sometimes referred to as a scan line) in the row associated withdisplay pixel22 is asserted, the switching transistor will be turned on and a new data signal on data line D will be loaded into storage capacitor Cst. The new signal on capacitor Cst is applied to the gate terminal oftransistor28, thereby adjusting the state oftransistor28 and adjusting the corresponding amount of light40 that is emitted by light-emittingdiode26.

Display pixels such as organic light-emittingdiode pixel22 ofFIG. 2 may include transistors that use top-gate thin-film transistor structures of the type shown inFIGS. 3A-3C. In particular,FIG. 3A shows topgate transistor structure300 formed by hydrogenation using silicon nitride or ion implantation.Transistor structure300 includessubstrate layer302 andbuffer layer304 formed on top ofsubstrate layer302. Additionally, an indium gallium zinc oxide layer (i.e., IGZO layer) may be formed on top ofbuffer layer304. In particular, the IGZO layer may include three portions,active region306 and two source-drain regions306′. Source-drain regions306′ may be heavily n-doped (e.g., heavily doped by electron donor impurities).

Gate insulator layer308 may be formed on top of the IGZO layer, andgate structure310 may be formed over thegate insulator layer308 on top of a region directly aboveactive region306 of the IGZO layer.Insulation layer312 may be formed over corresponding portions ofgate insulation layer308 andgate structure310. Contact holes314-1 and314-2 for source-drain regions306′ of the IGZO layer (i.e., source-drain of transistor structure300) may be formed by etching throughgate insulator layer308 andinsulation layer312.Passivation layer316 may be formed over contact holes314-1 and314-2 for respective source-drain regions306′.

In an embodiment, source-drain regions oftransistor structure300 ofFIG. 3A may be formed by a hydrogenation process using silicon nitride. It may be preferable to use silicon nitride asinsulation layer312 to diffuse dopants (e.g., hydrogen) into source-drain regions306′ in the hydrogenation process. Additionally, dopants may also diffuse into active region306 (sometimes referred to herein as channel region306), thereby shortening the effective channel region oftransistor structure300. These characteristics of the hydrogenation step may lead to less source-drain region dopant concentration control.

In an embodiment, source-drain regions oftransistor structure300 ofFIG. 3A may be formed by an ion implantation process. The ion implantation process may necessitate a thickness limit on insulation layer312 (e.g., a thickness less than 200 nm). For example,insulation layer312 may act as a mask when doping source-drain regions306′ using an ion implantation process. In such a way, the ion implantation process may provide better doping concentration control (as compared to the previously described hydrogenation process).

In an embodiment, as shown inFIG. 3B,transistor structure300′ may be formed using plasma treatment. Similar structure previously described in connection withFIG. 3A will not be further described inFIG. 3B in order to not unnecessarily obscure the present embodiment.

Whiletransistor structure300 ofFIG. 3A may have agate insulator layer308 that is patterned by contact holes314,transistor structure300 ofFIG. 3B may includegate insulator layer308′, which is patterned usinggate structure310. For example,gate structure310 andgate insulator308′ may be simultaneously etched (e.g., etched in the same processing step) to form the pattern as shown inFIG. 3B using a dry etch process (e.g., plasma treatment). Because source-drain regions306′ may also be exposure during the plasma treatment, source-drain regions306′ may increase in conductivity. If desired, additional plasma treatment (e.g., using Argon, Hydrogen, Helium) to further activate (e.g., increase the conductivity of) source-drain regions306′.

In an embodiment, as shown inFIG. 3C,transistor structure300′ may also includebarrier layer320 formed oversource drain regions306′. Portions ofbarrier layer320 may be etched away to form contacts to source-drain regions306′ (e.g., to form contacts314-1 and314-2).Barrier layer320 may be formed from alumina to act as a hydrogen barrier layer, as an example. Other suitable barrier materials may also be used. In the scenario in which source-drain regions306′ directly contact insulation layer312 (as shown inFIG. 3B), diffusion may occur across interface between source-drain region306′ andinsulation layer312. The diffusion may increase the resistance of source-drain regions306, especially in high temperature settings, thereby leading to lower thermal stability of source-drain regions306′. By forming barrier layer320 (as shown inFIG. 3C) diffusion out of source-drain regions (into insulation layer312) may be minimized

Top-gate IGZO transistor structures (i.e., transistor structures in which the gating element is formed above the gate insulator and channel region) as shown inFIGS. 3A-3C may be implemented within various transistor circuitry ofpixel22. In particular, as shown inFIG. 4drive transistor28 may be formed usingtransistor structure300 as described inFIG. 3A.Circuitry400 ofFIG. 4 may also include switchingtransistor30 formed as a top-gate LTPS transistor and storage capacitor Cst having a conductive IGZO electrode.

A cross-sectional view ofpixel circuitry400 is shown inFIG. 4.Pixel circuitry400 may includetransistors28 and30 formed over substrate and buffer layers402.Portion402 as shown inFIG. 4 may include one or more semiconducting layers, one or more insulation layers, a combination of semiconducting layers and insulation layers, as an example. A buffer layer may be formed as the topmost layer ofportion402. A polysilicon layer (e.g., an LTPS layer) may be formed on the buffer layer, thereafter, patterned and etched to formLTPS region406. The two opposing ends ofLTPS region406 may be doped (e.g., p-doped) to form source-drain regions of switchingtransistor30. As an example, the two opposing ends ofLTPS region406 may be doped after forming the gate structure oftransistor30. If desired, switchingtransistor30 may be formed with n-doped source drain regions.

Gate insulator layer408 may be formed onportion402 andLTPS region406. A first metal layer (e.g., a first gate metal layer) may be formed over thegate insulator layer408. The first metal layer may be patterned and etched to form gate structure Gate1 oftransistor30.Dielectric layers412 and414 may be formed over gate structure Gate1 andtransistor circuitry30.Dielectric layers412 may be formed from silicon nitride, whiledielectric layer414 may be formed form silicon nitride, as an example. If desired, any suitable dielectric materials may formlayers412 and414. Portions oflayers408,412, and414 above a first source-drain region of transistor30 (e.g., the left source-drain region oftransistor30 as shown inFIG. 4) may be etched to form contact holes. A metal contact (e.g., via418-1 or contact418-1) may be formed from metal contact layer CNT1 (sometimes referred to herein as contact CNT1) in the etched region to contact the left source-drain region oftransistor30. Portions oflayers408,412, and414 above a second source-drain region of transistor30 (e.g., the right source-drain region oftransistor30 as shown inFIG. 4) may also be etched to form additional contact holes. An additional metal contact (e.g., contact418-2) may be formed in the etched region to contact the right source-drain region oftransistor30. Contact418-2 may also be formed in metal contact layer CNT1.

Metal portions SD1 may be all formed simultaneously. In other words, a metal layer (e.g., interconnection metal layer SD1, sometimes referred to herein as source-drain metal layer SD1) may be provided, and thereafter, patterned to formmetal segments416 and420 and metal segments on top of metal contact layer CNT1 (e.g., capping contacts418-1 and418-2). Metal segment416 (sometimes referred to herein as metal structure416) may form a portion ofdrive transistor28 to improve transistor performance (e.g., to provide better current-voltage characteristics such as a flatter saturation current profile).Metal segment420 may form a portion of storage capacitor Cst as a capacitor electrode (sometimes referred to herein as a capacitor place or capacitor terminal). Dielectric layer422 (sometimes referred to herein as a passivation layer) may be formed overmetal segments416 and420 and contacts418-1 and418-2.Dielectric layer422 may also form a portion of storage capacitor Cst. In particular, a portion ofdielectric layer422 may be a capacitor dielectric layer.

An IGZO layer may be formed overdielectric layer422. The IGZO layer may be patterned and etched to formIGZO segments424 and426. As previously described inFIG. 3A, an insulation layer (e.g., gate insulator layer428) may be formed onIGZO segments424 and426 and portions ofdielectric layer422. A second gate metal layer may be formed ongate insulator layer428. The second gate metal layer may be patterned and etched to form a gating element of transistor28 (e.g., gate structure Gate2). Source-drain regions ofIGZO segment424 andIGZO segment426 may be doped as similarly described inFIG. 3A (e.g., via hydrogenation, via ion implantation).Passivation layer430 may similarly be formed over gate structure Gate2.

IGZO segment426 may form a first electrode of storage capacitor Cst.IGZO regions424 and426 may be formed in the same semiconducting-oxide layer (e.g., a patterned IGZO layer using the same mask).Metal segment420 may form a second electrode of storage capacitor Cst. Portions ofdielectric layer422 betweensegments426 and420 may form the dielectric material between the first and second electrodes of storage capacitor Cst.

Contact holes for metal contacts to both source-drain terminals oftransistor28, metal contacts to contact418-1, and both electrodes (e.g.,electrodes420 and426) of storage capacitor Cst may be formed by etching through one or more layers oflayers430,428, and422. An additional metal contact layer (e.g., metal contact layer CNT2, sometimes referred to herein as contact CNT2) may be formed to fill the etched contact holes thereby forming respective contacts totransistors28 and30, and capacitor Cst.

A planarization layer (e.g., planarization layer432) may be formed onpassivation layer430, and consequently, on the transistor and capacitor structures. Interconnections between the different metal contacts of transistors and capacitors structures (e.g., interconnection metal layer SD2 sometimes referred to herein as source-drain metal layer SD2) may be formed onplanarization layer432. In particular, contact418-2 may be coupled to a positive voltage power supply (e.g.,voltage power supply34 inFIG. 2). Contact418-1 may be coupled to the right source-drain terminal oftransistor28 via metal contact layer CNT2 and metal layer SD2 overplanarization layer432.

In other words, a conductive routing path may coupletransistor28 totransistor30. The conductive routing path may include three vias, two of which are formed in metal contact layer CNT2 and one of which is formed in metal contact layer CNT1. Source-drain metal layer SD2 may couple the two vias in metal contact layer CNT2 to each other. The conductive routing path may include a first terminal contact coupled totransistor28 and a second terminal contact coupled totransistor30. The first terminal contact may include only one via, whereas the second terminal contact may include two vias.

An additional planarization layer (e.g., planarization layer434) may be formed onplanarization layer432 and over the metal interconnections on planarization layer432 (e.g., over the conductive routing path).Planarization layer432 and434 may be formed from organic dielectric materials such as a polymer. In contrast withlayers430,428,422,414,412, and480, which may be formed from inorganic dielectric material such as silicon nitride, silicon oxide, etc.

Anode436 may be formed overplanarization layer434 and may be coupled to the left source-drain terminal oftransistor28 via the corresponding metal interconnection onplanarization layer432. Pixel defining layer438 (PDL438) may be formed overanode436 and portions ofplanarization layer434.Pixel defining layer438 may define active luminous regions of display pixels.

Additional structures may be formed overPDL438 andanode436. For example, light-emitting diode emissive material, cathode, and other structures may also be included inpixel22. However, these additional structures are omitted for the sake of brevity.

Pixel circuitry400 may also includeencapsulation interface region450 and bendingregion452. As shown inFIG. 4 portions ofPDL438 andplanarization layers434 and432 may be removed to elimination any organic materials ininterface region450, thereby minimizing the amount of moisture and contaminants that reach pixel circuitry from outside of an encapsulated pixel region.Bending region452 may be formed to include different signal lines and power lines that are provided to the display pixels.

As shown inFIG. 4,drive transistor circuitry28 may be formed as an IGZO transistor that incorporates a top-gate design. In particular, the IGZO transistor may be of the type as shown inFIG. 3A.Switching transistor circuitry28 may be formed as an LTPS transistor that also incorporates a top-gate design. Furthermore, storage capacitor Cst may be formed a capacitor that includes conductive IGZO as a terminal of the capacitor.

Similar features previously described in connection withFIG. 4 are subsequently omitted from description inFIGS. 5-13 in order to avoid unnecessarily obscuring the following embodiments. Similar features (e.g., features with similar structures, features with similarly labelled reference numbers, etc.) as shown inFIGS. 5-13 may be assumed to serve similar functions as described inFIG. 4.

In an embodiment,drive transistor circuitry28 may include an IGZO transistor of the type as shown inFIG. 3B. In particular, the pixel circuitry as shown inFIG. 5 havingdrive transistor28, which includesgate insulator429. Gate structure Gate2,gate insulator429, and channel region of segment424 (i.e.,IGZO layer424 excluding doped source-drain regions) may be self-aligned. In other words, gate structure Gate2 andgate insulator429 may be etched using a same mask, as described inFIG. 3B. The source-drain regions of the IGZO segment may also be formed using gate structure Gate2 andgate insulator429 as a mask during plasma treatment (e.g., during dry etching of gate structure Gate2 and gate insulator429), as an example.

Referring back toFIG. 4,pixel circuitry400 may include multiple metal interconnections (e.g., source-drain metal layer SD2 with multiple segments coupling different transistor and capacitor structure) aboveplanarization layer432. As such, multiple contact holes (e.g., multiple vias CNT2) are required to access different terminals oftransistors28 and30 and capacitor Cst to one another using the respective metal interconnections in source-drain metal layer SD2 aboveplanarization layer432. As an example,pixel circuitry400 inFIG. 4 may require six total contact holes to couple positivevoltage supply source34 toanode436. In particular, the six total contact holes include two inorganic contact holes filed by contacts CNT1 (i.e., contact holes formed in inorganic layers), two organic contact holes filled by contacts CNT2 (i.e., contact holes formed in organic layers) tocouple transistor28 totransistor30, and two additional organic contact holes filled by contacts CNT2 that couple thetransistor28 toanode436.

Because of the number and size of contact holes required (e.g., three of the four organic contact holes are form in planarization layer432), layout design rules that specify spacing requirements may be violated in compact designs. Additionally, topology forplanarization layer434 may be distorted because of excess contact holes inplanarization layer432.

In an embodiment, metal layer SD2 formed aboveplanarization layer432 that requires contact holes withinplanarization layer432 may be reduced. As shown inFIG. 6A, an additional metal layer (e.g.,metal layer600, sometimes referred to herein as gate metal layer Gate3) may be formed onpassivation layer430. Metal contact layer CNT2 may be similarly formed onpassivation layer430 without forming contact holes throughplanarization layer432.

Metal contact layer CNT2 may have two respective segments each coupled to a source-drain terminal oftransistor28, a third segment coupled to gate structure Gate2 as a metal contact and a fourth segment coupled to the conductive IGZO plate of capacitor Cst. Metal layer CNT may also have a fifth segment coupled to contact418-2 or metal contact layer CNT1.Metal layer600 may coupletransistor28 totransistor30 via metal layer CNT2. As compared topixel circuitry400 as shown inFIG. 4, the pixel circuitry inFIG. 6A only includes two organic contact holes, one of which is inplanarization layer432 and the other one of which is inplanarization layer434. As previously described, an organic contact hole is defined as a contact hole formed in an organic layer (e.g., planarization layer432), whereas an inorganic contact hole is defined as a contact hole formed in an inorganic layer (e.g., passivation layer430).

As shown inFIG. 6A, bendingregion452 may includeplanarization layer610 formed on a substrate (e.g., a substrate inportion402 as described inFIG. 4). As an example,planarization layer610 may be formed from organic polymers, such as polyimide or polyacryl. Source-drain metal layer SD1 may also include a segment (e.g., metal segment612) formed in bendingregion452.Segment612 may be formed onplanarization layer610, which may level (e.g., flatten) the topology in the bending region (with respectful to the pixel circuitry region) before depositing metal layer SD1.Planarization layer432 may be formed over metal layer SD1.Planarization layer432 may also serve to flatten the topology before depositing an additional metal layer on top. Source-drain metal layer SD2 may also be formed in bendingregion452. In particular, metal layer SD2 may be formed onplanarization layer432.Planarization layer434 andPDL438 layer may be subsequently formed over metal layer SD2.

If desired, a portion of third gate metal layer Gate3 (e.g., segment650) may be formed in bendingregion452, as shown inFIG. 6B. In particular,planarization layer620 may be formed on a substrate (e.g., a substrate inportion402 as described inFIG. 4) and serve a similar function asplanarization layer610 inFIG. 6A. As an example,planarization layer620 may be thicker (e.g., have a larger height) thanplanarization layer610 inFIG. 6A because gate metal layer Gate3 may be in higher level than metal layer SD1 in a process stack-up.Planarization layer432 may be formed on gatemetal layer segment650, and metal layer SD2 may be formed onplanarization layer432. If desired, any number of additional metal layers (with corresponding planarization layers) may also be formed in bendingregion452 to provide a suitable number interconnections in bendingregion452.Planarization layer434 andPDL438 may be formed on metal layer SD2.

Similar toFIG. 4,drive transistor circuitry28 ofFIGS. 6A and 6B may both be top-gate IGZO transistors of the type as shown inFIG. 3A. Alternatively, drivetransistor28 may be formed as a top-gate IGZO transistor of the type as shown inFIG. 3B. In particular, as shown inFIG. 7,gate insulator700 similar togate insulator429 as shown inFIG. 5. In other words,transistor28 inFIG. 7 may includegate insulator700 that is vertically aligned with gate structure Gate2.

AlthoughFIGS. 5 and 7 describeddrive transistor30 as a type of top-gate IGZO transistor as shown and described inFIG. 3B, if desired, the IGZO transistor structure ofFIG. 3C may also be used.

As shown inFIGS. 4-7, interconnection metal layer SD1 may be formed between gate metal layer Gate1 andIGZO layer424. If desired, interconnection metal layer SD1 may be formed over gate metal layer Gate2, as shown inFIG. 8. Forming metal layer SD1 in such a configuration may reduce a number of masks used in the fabrication process as well as a number of inorganic contact holes (as compared to the pixel circuitry described inFIGS. 6 and 7).

InFIG. 8,transistor30 may be formed on a topmost layer (e.g., a buffer layer) inportion402.Gate insulator layer408 may similarly be formed over a LTPS layer (similar toLTPS region406 inFIG. 4). Because interconnection metal layer SD1 is formed abovepassivation layer430, the first gate metal layer (in which gate structure Gate1 inFIG. 4 is formed) may form both a gate structure fortransistor30 and as an electrode for capacitor Cst (e.g., capacitor plate812). Therefore, inter-layerdielectric layer412 may cover both gate structure Gate1 andcapacitor plate812. Inter-layerdielectric layer412 may also be used as the capacitor dielectric for storage capacitor Cst.

Similar toFIG. 4,IGZO portion424 may be formed as a portion oftransistor28, whileIGZO portion810 may be formed a portion of capacitor Cst (e.g., capacitor electrode810).IGZO portions424 and810 may be formed in the same IGZO layer during processing (e.g., by using the same IGZO layer patterned by a single mask).Insulation layer800 may be formed over bothIGZO portions424 and810.Insulation layer800 may also form the gate insulator oftransistor28. Gate structure Gate2 may form the gating element oftransistor28.Passivation layer430 may be formed over gate metal layer Gate2.

Additionally, if desired, metal contact layers CNT1 and CNT2 may be formed in the same step (e.g., using a single mask) using etch holes formed through one ormore layers430,800,412, and408. Alternatively, metal contact layers CNT1 and CNT2 may be separately formed. Interconnection metal layer SD1 may be formed overpassivation layer430 and may couple transistor structures and capacitor structures to one another. For example, metal layer SD1 may couple a source-drain region oftransistor28 to a source-drain region oftransistor30. As another example, metal layer SD1 may couple a terminal of storage capacitor Cst (e.g., capacitor terminal812) to a source-drain terminal oftransistor30. Metal layer SD2 may also be connected to the portion of metal layer SD1 coupled to both the terminal of storage capacitor Cst and the source-drain terminal oftransistor30. A positive power supply voltage may be provided to the portion of metal layer SD1, if desired.

Still referring toFIG. 8, a conductive routing path may also coupletransistor28 totransistor30. In contrast with the routing path referred to inFIG. 4, the conductive routing path ofFIG. 8 only includes one via in contact CNT2, one via in contact CNT1, and a source-drain metal layer that couples the one via in contact CNT2 and one via in contact CNT1. In other words, a first terminal contact of the conductive routing path coupled totransistor28 includes only one via. A second terminal contact of the conductive routing path coupled totransistor30 also includes only one via.

Because the two contact holes (contacts CNT1 and CNT2) formed to coupletransistor28 totransistor30 have different depth, contact issues may arise when forming metal contacts to fill the two contact holes. For example, an etch process may etch through the right source-drain region oftransistor28 while trying to achieve the correct depth of contact CNT1 to access the left source-drain region oftransistor30. Therefore, after forming the contact hole for the left source-drain region oftransistor30, it may be desirable to fill the contact hole as soon as possible. As shown inFIG. 9, gate structure Gate2 may be formed in a gate metal layer. In order to fill the contact hole of contacts CNT1 separately from contacts CNT2, the gate metal layer in which gate structure Gate2 is formed, may also formmetal vias900,902, and904. In other words, gate structure Gate2 may be simultaneously formed with contacts CNT1 to fill the formed contact holes immediately. Accordingly,passivation layer430 may be formed to cover gate structure Gate2 andmetal vias900,902, and904. Thereafter, metal contact layer CNT2 and interconnection metal layer SD1 may be formed as previously described inFIG. 8.

As shown inFIG. 10, an additional metal layer (e.g., metal layer1000) may be formed before forming metal contact layer CNT1, but following patterning based on the metal layer CNT1 mask.Metal layer1000 may be a protective metal film that prevents over-etching problems previously described in connection withFIG. 8.Metal layer1000 may therefore sometimes be referred to as etch-stop liner1000.

Metal layer1000 may be interposed between source-drain metal layer SD1 andpassivation layer430. Additionally, metal layer100 may also be interposed between contacts CNT1 and both source-drain regions oftransistor28. As an example,Metal layer1000 may be formed from Molybdenum, Tungsten, or any other suitable materials.Metal layer1000 may protectIGZO layer424 from over-etching as well as ensure good electrical contact to the source-drain regions oftransistor28.

As shown inFIG. 11, the pixel circuitry ofFIG. 8 may includepassivation layer1100 formed over interconnection metal layer SD1 and portion ofpassivation layer430. As an example, passivation layers430 and1100 may be formed from silicon nitride. If desired, any other suitable material may be used as the passivation layers. The addition ofpassivation layer1100 may prevent moisture and other contaminants from entering metal layer SD1.

In an embodiment, the pixel circuitry ofFIG. 9 may includepassivation layer1200 formed over interconnection metal layer SD1. A configuration of this type is shown inFIG. 12.

In an embodiment, the pixel circuitry ofFIG. 10 may includepassivation layer1300 formed over interconnection metal layer SD1. A configuration of this type is shown inFIG. 13.

The foregoing is merely illustrative and various modifications can be made by those skilled in the art without departing from the scope and spirit of the described embodiments. The foregoing embodiments may be implemented individually or in any combination.

Claims (23)

What is claimed is:

1. A display comprising:

a semiconducting-oxide drive transistor, wherein the semiconducting-oxide drive transistor is a top-gate transistor;

a storage capacitor coupled to the drive transistor, wherein the storage capacitor comprises conductive oxide, and wherein the storage capacitor is formed in the same layer in the display as the semiconducting-oxide drive transistor;

a silicon switching transistor coupled to the semiconducting-oxide drive transistor, wherein the silicon switching transistor is formed on a substrate, and wherein the semiconducting-oxide drive transistor is formed above the silicon switching transistor;

an organic layer formed on the semiconducting-oxide drive transistor;

a metal layer laterally coupling a source-drain terminal of the semiconducting-oxide drive transistor to a source-drain terminal of the silicon switching transistor, wherein the metal layer is not formed through the organic layer; and

a conductive structure electrically coupled to a gate conductor of the top-gate transistor, wherein the conductive structure is not formed through the organic layer.

2. The display ofclaim 1, further comprising:

a light-emitting diode coupled in series with the drive transistor.

3. The display ofclaim 2, wherein the silicon switching transistor is configured to selectively pass current through the drive transistor to the light-emitting diode.

4. The display ofclaim 2, further comprising:

a first power supply line; and

a second power supply line, wherein the semiconducting-oxide drive transistor, the silicon switching transistor, and the light-emitting diode are coupled in series between the first and second power supply lines.

5. The display ofclaim 1, further comprising:

a light-emitting diode coupled in series with the drive transistor; and

an additional organic layer formed on the organic layer, wherein the light-emitting diode has an anode layer that is formed on the additional organic layer.

6. The display ofclaim 1, further comprising:

a conductive segment formed in a bending region of the display, the conductive segment and the metal layer are at least partially formed in the same gate metal layer.

7. The display ofclaim 1, further comprising:

a conductive structure formed directly below the semiconducting-oxide drive transistor in a given metal layer; and

a storage capacitor coupled to the drive transistor, the storage capacitor comprises a capacitor plate in the given metal layer.

8. The display ofclaim 1, wherein the silicon switching transistor comprises a gate structure formed in a given metal layer, the display further comprising:

a storage capacitor coupled to the drive transistor, the storage capacitor comprises a capacitor plate in the given metal layer.

9. The display ofclaim 1, wherein the semiconducting-oxide drive transistor does not include a bottom gate.

10. A display comprising:

a drive transistor having a gate terminal and a source terminal;

a metal segment formed directly below the drive transistor;

a capacitor coupled to the drive transistor, wherein the capacitor comprises a first terminal formed from conductive oxide and a second terminal formed from an additional metal segment separate from the metal segment, wherein the additional metal segment is formed in the same layer as the metal segment, and wherein the capacitor is configured to store a voltage across the gate and source terminals of the drive transistor.

11. The display ofclaim 10, further comprising:

a light-emitting diode coupled in series between the drive transistor.

12. The display ofclaim 10, further comprising:

a dielectric layer formed below the drive transistor, wherein the drive transistor comprises semiconducting-oxide material, and wherein the conductive oxide of the capacitor and the semiconducting-oxide material of the drive transistor are formed on the dielectric layer.

13. The display ofclaim 10, further comprising:

a switching transistor coupled to the drive transistor, wherein the switching transistor has a gate formed below the metal segment.

14. The display ofclaim 10, further comprising:

a capacitor; and

an additional routing path coupling the capacitor to the switching transistor, wherein the routing path and the additional routing path include lateral routing portions that are formed in the same layer.

15. A display comprising:

a drive transistor having a source-drain terminal;

a switching transistor coupled to the drive transistor;

a conductive routing path having a first terminal contact that is coupled to the drive transistor and a second terminal contact that is coupled to the switching transistor; and

a conductive etch-stop liner interposed between the source-drain terminal of the drive transistor and the first terminal contact.

16. The display ofclaim 15, wherein the drive transistor comprises semiconducting-oxide and the switching transistor is a silicon transistor.

17. The display ofclaim 16, wherein the drive transistor is a top-gate transistor.

18. The display ofclaim 15, wherein the second terminal contact of the conductive routing path comprises only one via.

19. A display comprising:

a semiconducting-oxide transistor having a semiconducting-oxide layer;

a conductor formed directly below the semiconducting-oxide layer of the semiconducting-oxide transistor; and

a capacitor coupled to the semiconducting-oxide transistor, wherein the capacitor comprises a first terminal and a second terminal that is formed from an additional conductor separate from the conductor, and wherein the additional conductor is formed in the same layer as the conductor.

20. The display of claim 19, further comprising:

a light-emitting diode coupled to the semiconducting-oxide transistor.

21. The display of claim 19, further comprising:

a switching transistor coupled to the semiconducting-oxide transistor, wherein the switching transistor has a gate formed in a layer below the conductor.

22. The display of claim 20, wherein the semiconducting-oxide transistor comprises a metal layer that includes molybdenum.

23. The display of claim 21, further comprising:

a first planarization layer formed over the semiconducting-oxide transistor; and

a second planarization layer formed on the first planarization layer.

Images