USRE46035E1 - Liquid crystal display having a reduced number of data driving circuit chips - Google Patents

Abstract

A liquid crystal display includes a substrate, a plurality of gate lines formed on the substrate, a plurality of data lines intersecting the plurality of gate lines, a plurality of thin film transistors connected to the plurality of gate lines and the plurality of data lines, and a plurality of pixel electrodes connected to the plurality of thin film transistors and arranged in a matrix, wherein each of the pixel electrodes includes a first side parallel to each gate line and a second side being shorter than the first side, the second side being formed next to the first side, wherein the plurality of pixel electrodes that are adjacent to each other in a column direction are connected to different data lines from each other.

Description

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to Korean Patent Application No. 10-2005-0086257 filed on Sep. 15, 2005, the contents of which are incorporated herein by reference in their entirety.Notice: More than one reissue application has been filed for the reissue of U.S. Pat. No. 7,733,433. The reissue applications are application Ser. No. 14/490,731 (the present application, which is a continuation reissue application of application Ser. No. 13/837,889), Ser. No. 13/837,889 (a continuation reissue application of application Ser. No. 13/198,411), and Ser. No. 13/198,411 (now U.S. Pat. No. Re. 44,181).

This is a continuation reissue application of a pending continuation reissue application of U.S. Reissue application Ser. No. 13/837,889 filed on Mar. 15, 2013 which is a reissue application of U.S. Reissue application Ser. No. 13/198,411 filed on Aug. 4, 2011, issued as U.S. Pat. No. Re. 44,181 on Apr. 10, 2013, from U.S. application Ser. No. 11/517,521 filed on Sep. 7, 2006, issued as U.S. Pat. No. 7,733,433, issued on Jun. 8, 2010, which claims priority to Korean patent Application No. 10-2005-0086257 filed on Sep. 15, 2005, the disclosures of which are incorporated by reference herein in their entirety.

BACKGROUND OF THE INVENTION

(a) Technical Field

The present disclosure relates to a liquid crystal display, and more particularly to a liquid crystal display having a reduced number of data driving circuit chips.

(b) Discussion of the Related Art

Liquid crystal displays (LCDs) are widely used flat panel displays. An LCD may include two panels provided with field-generating electrodes such as, for example, pixel electrodes and a common electrode, and a liquid crystal layer interposed therebetween. The LCD displays images by applying voltages to the field-generating electrodes to generate an electric field in the liquid crystal layer, thereby determining the orientations of the liquid crystal molecules in the liquid crystal layer and adjusting polarization of incident light.

The LCD includes switching elements connected to respective pixel electrodes, and a plurality of signal lines such as gate lines and data lines for controlling the switching elements to apply voltages to the pixel electrodes. The gate lines transmit gate signals generated by a gate driving circuit and the data lines transmit data voltages generated by a data driving circuit. The switching elements transmit the data voltages to the pixel electrodes in response to the gate signals.

The gate driving circuit and the data driving circuit may be implemented as a plurality of integrated circuit (IC) chips directly mounted on the panel or mounted on a flexible circuit film, which is attached to the panel. Since the manufacturing cost of data driving circuit chips for use in an LCD are expensive and the data driving circuit is difficult to integrate into the panel, there is a need to reduce a number of the data driving circuit chips.

SUMMARY OF THE INVENTION

An exemplary embodiment of the present invention provides a liquid crystal display including a substrate, a plurality of gate lines formed on the substrate, a plurality of data lines intersecting the gate lines, a plurality of thin film transistors connected to the gate lines and the data lines, and a plurality of pixel electrodes connected to the thin film transistors and arranged in a matrix. Each of the pixel electrodes may include a first side parallel to each gate line and a second side that is shorter than the first side and is next to the first side, wherein pixel electrodes that are adjacent to each other in a column direction can be connected to different data lines from each other.

The liquid crystal display may further include storage electrode lines of which at least a portion of each overlaps a pixel electrode.

The storage electrode lines may extend perpendicular to the gate lines.

The storage electrode lines may be located in a same layer as the data lines.

The storage electrode lines may include a first part located in the same layer as the gate lines and disposed between two adjacent gate lines, and a second part located in a different layer from the gate lines, the second part intersecting the gate lines and connecting the first parts with each other.

The second part may be located in a same layer as the pixel electrodes.

The storage electrode lines may include at least one branch that is adjacent to the gate lines and extends substantially parallel to the gate lines.

A boundary of each pixel electrode may be located on the at least one branch of a storage electrode line.

The storage electrode lines may be substantially parallel to the gate lines and arranged alternately with the gate lines, the storage electrode lines being located in a same layer as the gate lines.

The thin film transistors may include each a drain electrode overlapping a storage electrode line.

A boundary of each pixel electrode may be located on a storage electrode line.

Each pixel electrode may cover a gate line.

The data lines and the pixel electrodes may overlap each other.

The liquid crystal display may further include an organic layer formed between the pixel electrodes and the data lines and between the pixel electrodes and the gate lines.

The thin film transistor may include a gate electrode connected to a gate line, a source electrode connected to a data line, and a drain electrode connected to a pixel electrode, wherein the source electrode and the drain electrode have a substantially bilateral symmetry.

A length of the first side may be three times the length of the second side.

The liquid crystal display may further include a gate driver connected to the gate lines, wherein the gate driver includes a first gate driving circuit connected to first gate lines, and a second gate driving circuit connected to second gate lines, wherein the first and second gate driving circuits are located in a same layer as the gate lines, the data lines, and the thin film transistors.

The first gate driving circuit and the second gate driving circuit may be disposed opposite each other with respect to the substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

Exemplary embodiments of the present invention can be understood in detail from the following description taken in conjunction with the accompanying drawings of which:

FIG. 1 is a block diagram of an LCD according to an exemplary embodiment of the present invention;

FIG. 2 is a circuit diagram of a pixel of an LCD according to an exemplary embodiment of the present invention;

FIG. 3 is a layout view of an LCD according to an exemplary embodiment of the present invention;

FIG. 4 andFIG. 5 are cross-sectional views of an LCD taken along the line IV-IV and the line V-V inFIG. 3, respectively;

FIG. 6 is a layout view of an LCD according to an exemplary embodiment of the present invention;

FIG. 7 is a cross-sectional view of an LCD taken along the line VII-VII inFIG. 6;

FIG. 8 is a layout view of an LCD according to an exemplary embodiment of the present invention; and

FIG. 9 is a cross-sectional view of an LCD taken along the line IX-IX inFIG. 8.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

Exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

An LCD according to an exemplary embodiment of the present invention is described with reference toFIG. 1 andFIG. 2.

FIG. 1 is a block diagram of an LCD according to an exemplary embodiment of the present invention.FIG. 2 is a circuit diagram of a pixel of an LCD according to an exemplary embodiment of the present invention.

Referring toFIG. 1 andFIG. 2, an LCD according to an exemplary embodiment of the present invention includes a liquidcrystal panel assembly300, a pair ofgate drivers400a and400b and adata driver500 that are connected to the liquidcrystal panel assembly300, agray voltage generator800 connected to thedata driver500, and asignal controller600 for controlling the above components.

The liquidcrystal panel assembly300 includes, for example, a plurality of display signal lines and a plurality of pixels PX1, PX2, and PX3 connected to the display signal lines and arranged substantially in a matrix. The liquidcrystal panel assembly300 includes, for example, lower andupper panels100 and200 that face each other with aliquid crystal layer3 interposed therebetween.

The signal lines G1-Gn and D1-Dm include a plurality of gate lines G1-Gn for transmitting gate signals (also referred to as “scanning signals”) and a plurality of data lines D1-Dm for transmitting data signals. The gate lines G1-Gn extend substantially in a row direction and substantially parallel to each other. The data lines D1-Dm extend substantially in a column direction and substantially parallel to each other.

Each pixel PX1, PX2, and PX3 has a substantially rectangular shape elongated in the row direction. Each pixel PX1, PX2, and PX3, includes a switching element Q connected to the signal lines GL and DL, a liquid crystal capacitor Clc, and a storage capacitor Cst that are connected to the switching element Q.

In an embodiment of the present invention, the storage capacitor Cst may be omitted.

The switching element Q including a thin film transistor can be a three-terminal component provided on thelower panel100, wherein the control terminal is connected to the gate line GL, the input terminal is connected to the data line DL, and the output terminal is connected to the liquid crystal capacitor Clc and the storage capacitor Cst. Referring toFIG. 1, each column of pixels is adjacent to two data lines, and the pixels PX1, PX2, and PX3 in the column of pixels are connected to the two data lines alternately. In other words, in each column of pixels, the switching elements Q of adjacent pixels PX1, PX2, and PX3 are connected to different data lines D1-Dm from each other.

The liquid crystal capacitor Clc includes apixel electrode191 provided on thelower panel100 and thecommon electrode270 provided on theupper panel200 as two terminals of the liquid crystal capacitor Clc. Theliquid crystal layer3 disposed between the twoelectrodes191 and270 functions as a dielectric material of the liquid crystal capacitor Clc. Thepixel electrode191 is connected to the switching element Q, and thecommon electrode270 is formed on the surface of theupper panel200 and is supplied with a common voltage Vcom. In an embodiment of the present invention, thecommon electrode270 may be provided on thelower panel100, and at least one of the twoelectrodes191 and270 may have a stripe or a bar shape.

The storage capacitor Cst, functioning as an auxiliary capacitor for the liquid crystal capacitor Clc, is formed by overlapping a signal line (not shown) provided on thelower panel100 with thepixel electrode191 via an insulator disposed therebetween. The signal line is supplied with a predetermined voltage such as a common voltage Vcom. Alternatively, the storage capacitor Cst may be formed by overlapping thepixel electrode191 with a gate line above thepixel electrode191 via an insulator.

Each pixel PX1-PX3 can display one of the primary colors (spatial division). Each pixel PX1-PX3 can sequentially display the primary colors in turn (temporal division). A spatial or temporal sum of the primary colors can be recognized as a desired color. An example set of the primary colors can be three primary colors including red, green, and blue.FIG. 2 shows an example of the spatial division in which each pixel PX1-PX3 includes acolor filter230 representing one of the primary colors in an area of theupper panel200 facing thepixel electrode191. In an embodiment of the present invention, thecolor filter230 may be provided on or under thepixel electrode191 on thelower panel100.Color filters230 of the pixels PX1-PX3 that are adjacent to each other in a row direction are connected to each other to extend along the row direction. The color filters230 representing different colors from each other are arranged alternately in the column direction.

In an embodiment, eachcolor filter230 may represent one of red, green, and blue colors. A pixel including ared color filter230 is referred to as a red pixel, a pixel including agreen color filter230 is referred to as a green pixel, and a pixel including ablue color filter230 is referred to as a blue pixel. Red pixels, blue pixels, and green pixels are disposed sequentially and alternately in the column direction according to an embodiment of the present invention.

Pixels PX1-PX3 representing the three primary colors form a dot DT that is a unit for displaying images.

Referring toFIG. 1, thegate drivers400a and400b are integrated into the liquidcrystal panel assembly300 along with the signal lines G1-Gn and D1-Dm and the thin film transistor switching elements Q. Thegate drivers400a and400b are located on the left side and the right side of the liquidcrystal panel assembly300, respectively. Thegate drivers400a and400b are alternately connected to the odd-numbered gate lines and the even-numbered gate lines, and apply gate signals comprising a gate-on voltage Von and a gate-off voltage Voff to the gate lines G₁-G_n. In an embodiment of the present invention, thegate driver400a and400b may be provided on only one side of theassembly300. In an embodiment of the present invention, thegate drivers400a and400b may be directly mounted on theassembly300 in the form of IC chips. In an embodiment of the present invention, thegate drivers400a and400b may be mounted on a flexible printed circuit film (not shown) and attached to the liquidcrystal panel assembly300 in a tape carrier package (TCP) form. In an embodiment of the present invention, thegate drivers400a and400b may be mounted on a separate printed circuit board (PCB) (not shown).

At least one polarizer (not shown) for polarizing light can be attached on the outer surface of the liquidcrystal panel assembly300.

Thegray voltage generator800 generates two sets of a plurality of gray voltages (or reference gray voltages) related to the transmittance of the pixels PX1-PX3. Gray voltages of a first set have a positive value with respect to the common voltage Vcom, and gray voltages of a second set have a negative value with respect to the common voltage Vcom.

Thedata driver500 is connected to the data lines D1-Dm of the liquidcrystal panel assembly300, and applies data signals selected from the gray voltages that are supplied from thegray voltage generator800 to the data lines D1-Dm. When thegray voltage generator800 does not supply voltages for all grays but supplies only the reference gray voltages of a predetermined number, thedata driver500 divides the reference gray voltages to generate gray voltages for all grays and selects data signals from the generated gray voltages. In an embodiment of the present invention, thedata driver500 may be directly mounted on the liquidcrystal panel assembly300 in the form of IC chips. In an embodiment of the present invention, thedata driver500 may be mounted on a flexible printed circuit film (not shown) and attached to the liquidcrystal panel assembly300 in a tape carrier package (TCP) form. In an embodiment of the present invention, thedata driver500 may be mounted on a separate printed circuit board (PCB) (not shown). Alternatively, thedata driver500 may be integrated into the liquidcrystal panel assembly300 along with the signal lines G1-Gn and D1-Dm and the thin film transistor switching elements Q.

Thesignal controller600 controls thegate drivers400a and400b and thedata driver500.

Thesignal controller600 is supplied with input image signals R, G, and B and input control signals for controlling the display of the input image signals R, G, and B from an external graphics controller (not shown). The input image signals R, G, and B include luminance information of respective pixels PX, and the luminance has a predetermined number of, for example, 1024(=2¹⁰), 256(=2⁸), or 64(=2⁶) grays. The input control signals include, for example, a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a main clock signal MCLK, and a data enable signal DE.

On the basis of the input control signals and the input image signals R, G, and B, thesignal controller600 processes the input image signals R, G, and B for the operating conditions of the liquidcrystal panel assembly300 and generates gate control signals CONT1 and data control signals CONT2. Then, thesignal controller600 transmits the gate control signals CONT1 to thegate drivers400a and400b and transmits the processed image signals DAT and the data control signals CONT2 to thedata driver500. The processing of image signals by thesignal controller600 includes an operation of rearranging the input image signals R, G, and B according to the disposition of pixels illustrated, for example, inFIG. 1.

The gate control signals CONT1 include a scanning start signal STV for instructing to start scanning and at least one clock signal for controlling the output time of the gate-on voltage Von. The gate control signals CONT1 may further include an output enable signal OE for defining the duration of the gate-on voltage Von.

The data control signals CONT2 include a horizontal synchronization start signal STH for informing of a start of digital image signal DAT transmission for a row of pixels, a load signal LOAD for instructing to apply analog data signals to the data lines D1-Dm, and a data clock signal HCLK. The data control signals CONT2 may further include an inversion signal RVS for reversing the voltage polarity of the analog data signals with respect to the common voltage Vcom (the “voltage polarity of the data signals with respect to the common voltage Vcom” is referred to as “polarity of the data signals”).

Responding to the data control signals CONT2 from thesignal controller600, thedata driver500 sequentially receives the digital image signals DAT for a row of pixels PX and selects gray voltages corresponding to the respective digital image signals DAT, thereby converting the digital image signals DAT into analog data signals, which are applied to the corresponding data lines D1-Dm.

Thegate drivers400a and400b apply the gate-on voltage Von to the gate lines G1-Gn in response to the gate control signals CONT1 from thesignal controller600, thereby turning on the switching elements Q connected to the gate lines G1-Gn.

Then, data signals applied to the data lines D1-Dm are applied to the corresponding pixels PX through the turned-on switching elements Q.

For example, the difference between the voltage of the data signal applied to the pixel PX and the common voltage Vcom appears as a charged voltage of the liquid crystal capacitor Clc. The charged voltage can be referred to as a pixel voltage. The arrangement of the liquid crystal molecules varies depending on the intensity of the pixel voltages. Thus the polarization of light passing through theliquid crystal layer3 varies. This variation of the light polarization causes a change of light transmittance by the polarizers attached to the liquidcrystal panel assembly300. Thus, the pixels PX display images having the luminance represented by the grays of the image signals DAT.

By repeating this procedure by a unit of the horizontal period (which can be denoted as “1H” and can be substantially equal to one period of the horizontal synchronization signal Hsync and the data enable signal DE), all gate lines G1-Gn are sequentially supplied with the gate-on voltage Von, thereby applying the data signals to all pixels PX to display an image for a frame.

When one frame is finished, the next frame starts. The inversion signal RVS applied to thedata driver500 can be controlled such that the polarity of the data signals applied to the respective pixels PX can be reversed to be opposite to the polarity in the previous frame (which is referred to as “frame inversion”). In an embodiment, even in one frame, the polarity of the data signals flowing in a data line may vary (for example, row inversion and dot inversion) or the polarities of the data signals applied to the pixels in a row may be different from each other (for example, column inversion and dot inversion) in accordance with the characteristics of the inversion signal RVS.

When adjacent pixels, for example, pixels PX1, PX2, and PX3 in each column of pixels are connected to the opposite data lines, the polarities of pixel voltages of the adjacent pixels PX1, PX2, and PX3 in the row direction and the column direction are opposite to each other if thedata driver500 applies data voltages having opposite polarities to the adjacent data lines in the form of column inversion while the polarities are unchanged during a frame. That is, an apparent inversion appearing at the screen becomes the dot inversion.

FIG. 3 is a layout view of a liquid crystal panel assembly according to an exemplary embodiment of the present invention.FIG. 4 andFIG. 5 are cross-sectional views of a liquid crystal panel assembly taken along the line IV-IV and the line V-V inFIG. 3, respectively.

Referring toFIG. 3 toFIG. 5, a liquid crystal panel assembly according to an exemplary embodiment of the present invention includes a thin filmtransistor array panel100, acommon electrode panel200, and aliquid crystal layer3 interposed between the twopanels100 and200.

A plurality ofgate lines121 are formed on an insulatingsubstrate110, comprising, for example, transparent glass or plastic.

The gate lines121 for transmitting gate signals extend substantially in a transverse direction. Eachgate line121 includes a plurality ofgate electrodes124 that protrude upwardly or downwardly and anend portion129 having a large enough area for connection with another layer or an external driving circuit.

The gate lines121 may comprise, for example, an aluminum-(Al) containing metal such as Al and an Al alloy, a silver-(Ag) containing metal such as Ag and a Ag alloy, a copper-(Cu) containing metal such as Cu and a Cu alloy, a molybdenum-(Mo) containing metal such as Mo and a Mo alloy, chromium (Cr), tantalum (Ta), and titanium (Ti). In an embodiment of the present invention, thegate lines121 may have a multi-layered structure including two conductive layers (not shown) having different physical properties. One of the two conductive layers may comprise a low resistivity metal such as, for example, an Al-containing metal, an Ag-containing metal, or a Cu-containing metal for reducing signal delay or voltage drop. In an embodiment of the present invention, the other conductive layer may comprise a material such as, for example, a Mo-containing metal, Cr, Ti, and Ta, which has good physical, chemical, and electrical contact characteristics with other materials such as, for example, indium tin oxide (ITO) or indium zinc oxide (IZO). Examples of the combination of two layers include a pair of a lower Cr layer and an upper Al (alloy) layer, and a pair of a lower Al (alloy) layer and an upper Mo (alloy) layer. According to embodiments of the present invention, thegate lines121 may comprise various metals or conductors.

The lateral sides of thegate lines121 are inclined with respect to a surface of thesubstrate110, and the inclination angle thereof ranges from about 30 degrees to about 80 degrees according to an embodiment of the present invention.

Agate insulating layer140 comprising, for example, silicon nitride (SiNx) or silicon oxide (SiOx) is formed on the gate lines121.

A plurality of semiconductor islands (“semiconductors”)154 comprising, for example, hydrogenated amorphous silicon (“a-Si”) or polysilicon are formed on thegate insulating layer140. Eachsemiconductor154 is disposed on thegate electrode124. A plurality of ohmic contact islands (“ohmic contacts”)163 and165 are formed on thesemiconductors154. Theohmic contacts163 and165 may comprise, for example, n+ hydrogenated a-Si heavily doped with an n-type impurity such as phosphorus (P), or silicide. Theohmic contacts163 and165 are disposed in pairs on thesemiconductors154.

The lateral sides of thesemiconductors154 and theohmic contacts163 and165 are inclined with respect to a surface of thesubstrate110. The inclination angle thereof ranges from about 30 degrees to about 80 degrees according to an embodiment of the present invention.

A plurality of data lines171, a plurality ofdrain electrodes175, and a plurality ofstorage electrode lines131 are formed on theohmic contacts163 and165 and thegate insulating layer140.

The data lines171 for transmitting data signals extend substantially in the longitudinal direction and intersect the gate lines121. Each data line171 includes a plurality ofsource electrodes173 branched toward thegate electrodes124 and anend portion179 having a large enough area for connection with another layer or an external driving circuit. The data driving circuit (not shown) for generating data signals may be mounted on a flexible printed circuit film (not shown) attached to thesubstrate110. In an embodiment of the present invention, the driving circuit may be directly mounted on thesubstrate110. In an embodiment of the present invention, the driving circuit may be integrated with thesubstrate110. When the data driving circuit is integrated on thesubstrate110, the data lines171 may be extended and directly connected to the data driving circuit.

Eachdrain electrode175 is separated from the data line171, and is formed opposite asource electrode173 with respect to agate electrode124. Eachdrain electrode175 has an end portion having a large enough area and another stick-shaped end portion. The stick-shaped end portion is partially surrounded by thesource electrode173 in a “U” shape. Thesource electrode173 and thedrain electrode175 have a substantially bilateral symmetry.

Thegate electrode124, thesource electrode173, and thedrain electrode175, along with asemiconductor154, form a thin film transistor (TFT) having a channel formed in thesemiconductor154 disposed between thesource electrode173 and thedrain electrode175.

Thestorage electrode lines131 are supplied with a predetermined voltage such as the common voltage. Each of thestorage electrode lines131 includes a stem extending substantially parallel to the data lines171 and a plurality ofstorage electrodes133a,133b,133c and133d branched from the stem. Thestorage electrodes133a-133d extend parallel with thegate lines121 to both sides from the stem and are formed near the gate lines121. In embodiments of the present invention, the shapes and dispositions of thestorage electrode lines131 may be modified in various ways.

The data lines171, thedrain electrodes175, and thestorage electrode lines131 may comprise a refractory metal such as, for example, Mo, Cr, Ta, and Ti or an alloy thereof. The data lines171, thedrain electrodes175, and thestorage electrode lines131 may have a multi-layered structure including, for example, a refractory metal layer (not shown) and a conductive layer (not shown) having low resistivity. An example of the multi-layered structure includes a double-layered structure including a lower Cr or Mo (alloy) layer and an upper Al (alloy) layer, and a triple-layered structure including a lower Mo (alloy) layer, an intermediate Al (alloy) layer, and an upper Mo (alloy) layer. In embodiments of the present invention, the data lines171, thedrain electrodes175, and thestorage electrode lines131 may comprise various metals or conductive materials.

The lateral sides of the data lines171, thedrain electrodes175, and thestorage electrode lines131 can be inclined with respect to a surface of thesubstrate110. The inclination angles thereof can be in a range of about 30 degrees to about 80 degrees according to an embodiment of the present invention.

Theohmic contacts163 and165 are interposed between theunderlying semiconductors154 and the overlying data lines171 and thedrain electrodes175. Theohmic contacts163 and165 reduce the contact resistance therebetween. Thesemiconductors154 include exposed portions which are not covered with the data line171 and thedrain electrode175 such as the portion located between thesource electrode173 and thedrain electrode175.

Apassivation layer180 is formed on the data lines171, thedrain electrodes175, and the exposed portions of thesemiconductors154. Thepassivation layer180 may comprise an inorganic insulator such as, for example, silicon nitride or silicon oxide. Alternatively, thepassivation layer180 may comprise an organic insulator, and the surface thereof may be flat. The organic insulator may have photosensitivity, and the dielectric constant thereof can be lower than about 4.0 in an embodiment of the present invention. Thepassivation layer180 may have a double-layered structure, including a lower inorganic layer and an upper organic layer, to reduce damage to the exposed portions of thesemiconductors154 and to enhance insulating characteristics of an organic layer.

Thepassivation layer180 has a plurality ofcontact holes182 and185 respectively exposing theend portions179 of the data lines171 and thedrain electrodes175. Thepassivation layer180 and thegate insulating layer140 have a plurality ofcontact holes181 exposing theend portions129 of the gate lines121.

A plurality ofpixel electrodes191, a plurality of connectingmembers81, and a plurality ofcontact assistants82 are formed on thepassivation layer180. These components may comprise, for example, a transparent conductive material such as ITO and IZO, or a reflective metal such as Al, Ag, Cr, or an alloy thereof.

Eachpixel electrode191 has four major sides that are substantially parallel to thegate lines121 or the data lines171. The length of the two transverse sides191l that are parallel to the gate lines121 is substantially longer, for example, by three times, than the length of the twolongitudinal sides191s that are parallel to the data lines171. Compared to when the transverse sides are shorter than the longitudinal sides, the number ofpixel electrodes191 located in each row is fewer, and the number ofpixel electrodes191 located in each column is greater. Accordingly, since the number of the data lines171 is decreased, the number of IC chips for thedata driver500 can be reduced. Thegate drivers400a and400b can be integrated into theassembly300 along with thegate lines121, data lines171, and the TFTs according to an embodiment of the present invention.

Thepixel electrode191 is physically and electrically connected with thedrain electrode175 through thecontact hole185, and receives a data voltage from thedrain electrode175. Thepixel electrode191 receiving a data voltage generates an electric field in cooperation with thecommon electrode270 on thecommon electrode panel200 supplied with a common voltage. The orientations of the liquid crystal molecules in theliquid crystal layer3 interposed between the twoelectrodes191 and270 are determined using the electric field. In accordance with the determined orientations of the liquid crystal molecules, the polarization of light passing through theliquid crystal layer3 is varied. Thepixel electrode191 and thecommon electrode270 form a liquid crystal capacitor to store and to preserve the applied voltage even after the TFT is turned off.

Thepixel electrode191 overlaps thestorage electrode line131 including thestorage electrodes133a-133d to form a storage capacitor that enhances the voltage storing capacity of the liquid crystal capacitor. In an embodiment of the present invention, the stem of thestorage electrode line131 traverses across the middle of thepixel electrode191 in a longitudinal direction. The top and bottom boundaries of thepixel electrode191 are located on thestorage electrodes133a-133d extending to the right and left from the stem. In an embodiment of the present invention, electromagnetic interference between thegate line121 and thepixel electrode191 can be blocked by thestorage electrodes133a-133d, thereby stably maintaining the voltage of thepixel electrode191. In this structure, the conducting wire in the longitudinal direction is decreased as compared to a structure in which thestorage electrodes133a-133d are disposed at the left and right boundaries of thepixel electrode191. Thus the transverse width of pixels is reduced such that sufficient space for integratinggate drivers400a and400b can be generated. Thestorage electrodes133a-133d can block light leakage between thepixel electrodes191. A step difference caused by disposing the stem of thestorage electrode line131 in the middle of thepixel electrode191 can be compensated by making a slight inclination of the lateral sides of thestorage electrode line131.

Eachcontact assistant82 is connected to theend portion179 of the data line171 through thecontact hole182. Thecontact assistants82 supplement the adhesive property of theend portions179 of the data lines171 to exterior devices, and protect the exterior devices.

Each connectingmember81 is connected to anend portion129 of thegate line121 through thecontact hole181. The connectingmembers81 connect theend portions129 of thegate lines121 to thegate drivers400a and400b. If thegate drivers400a and400b are in the form of IC chips, the connectingmembers81 may have substantially similar shapes and functions with thecontact assistants82.

Alight blocking member220 is formed on an insulatingsubstrate210 comprising, for example, transparent glass or plastic. Thelight blocking member220 can be referred to as a black matrix, and prevents light leakage.

A plurality ofcolor filters230 are formed on thesubstrate210 and thelight blocking member220. The color filters230 are disposed substantially in the regions enclosed by thelight blocking member220, and may extend along a transverse direction substantially along the rows ofpixel electrodes191. Each of thecolor filters230 may represent one of the primary colors such as red, green, and blue.

Anovercoat250 is formed on thecolor filters230 and thelight blocking member200. Theovercoat250 may comprise, for example, an organic insulator. Theovercoat250 prevents thecolor filters230 from being exposed and provides a flat surface. Theovercoat250 may be omitted according to an embodiment of the present invention.

Alignment layers11 and21 are coated on inner surfaces of thepanels100 and200. The alignment layers11 and21 may be vertical alignment layers. Polarizers12 and22 are provided on outer surfaces of thepanels100 and200. Polarization axes of thepolarizers12 and22 may be parallel or perpendicular to each other. One of the two polarizers may be omitted when the LCD is a reflective type LCD according to an embodiment of the present invention.

An LCD according to an exemplary embodiment may further include a retardation film (not shown) for compensating the retardation of theliquid crystal layer3. The LCD may further include a backlight unit (not shown) for supplying light to thepolarizers12 and22, the retardation film, thepanels100 and200, and theliquid crystal layer3.

Theliquid crystal layer3 is in a state of positive or negative dielectric anisotropy. The liquid crystal molecules in theliquid crystal layer3 are aligned such that their long axes are substantially parallel or vertical to the surfaces of thepanels100 and200 in the absence of an electric field.

An LCD according to an exemplary embodiment of the present invention is described with reference toFIG. 6 andFIG. 7.

FIG. 6 is a layout view of an LCD according to an exemplary embodiment of the present invention.FIG. 7 is a cross-sectional view of an LCD taken along the line VII-VII inFIG. 6.

Referring toFIG. 6 andFIG. 7, an LCD according to an exemplary embodiment includes theTFT array panel100, thecommon electrode panel200, theliquid crystal layer3 interposed between the twopanels100 and200, andpolarizers12 and22 attached to outer surfaces of the twopanels100 and200.

The plurality ofgate lines121 and the plurality ofstorage electrodes133 are formed on thesubstrate110. Eachgate line121 includes the plurality ofgate electrodes124 that protrude upwardly and downwardly, and theend portion129 having a large enough area for connection with another layer or thegate driver400a or400b. Eachstorage electrode133 includes a stem portion extending substantially perpendicular to thegate line121, andbranch portions133a-133d extending to the left and right from the stem portion.

Thegate insulating layer140, the plurality ofsemiconductor islands154 having projections, and the plurality ofohmic contact islands163 and165 are sequentially formed on thegate lines121 and thestorage electrodes133. The plurality of data lines171 includingsource electrodes173 and endportions179 are formed on theohmic contacts163 and165 and thegate insulating layer140, and apassivation layer180 is formed thereon.

Thepassivation layer180 has the plurality ofcontact holes182 and185 respectively exposing theend portions179 of the data lines171 and thedrain electrodes175. Thepassivation layer180 and thegate insulating layer140 have the plurality ofcontact holes181 exposing theend portions129 of thegate lines121 and a plurality ofcontact holes183 exposing a substantially center portion of thebranch portions133a-133b and a substantially center portion of thebranch portions133c and133e at thestorage electrodes133.

The plurality ofpixel electrodes191, a plurality ofoverpasses83, the plurality of connectingmembers81, and the plurality ofcontact assistants82 are formed on thepassivation layer180.

Theoverpasses83 cross over the gate lines121. Theoverpasses83 are connected to thestorage electrodes133 through the contact holes183 that are disposed opposite each other with respect to the gate lines121. Theoverpasses83 form a storage electrode line along with thestorage electrodes133.

Thelight blocking member220, thecolor filters230, theovercoat250, thecommon electrode270, and thealignment layer21 are sequentially formed on an insulatingsubstrate210.

An LCD according to an exemplary embodiment of the present invention is described with reference toFIG. 8 andFIG. 9.

FIG. 8 is a layout view of an LCD according to an exemplary embodiment of the present invention.FIG. 9 is a cross-sectional view of an LCD taken along the line IX-IX inFIG. 8.

Referring toFIG. 8 andFIG. 9, the plurality ofgate lines121 including thegate electrodes124 and the plurality ofstorage electrode lines131 are formed on the insulatingsubstrate110 comprising, for example, transparent glass or plastic.

Thestorage electrode line131 is supplied with a predetermined voltage, and extends substantially parallel to thegate line121. Eachstorage electrode line131 is disposed between twoadjacent gate lines121 and is formed near the lower one of the twogate lines121. Thestorage electrode line131 includes anexpansion137 extending upwardly.

Thegate insulating layer140, the plurality ofsemiconductor islands154, and the plurality ofohmic contact islands163 and165 are sequentially formed on thegate lines121 and the storage electrode lines131.

The plurality of data lines171 including thesource electrodes173 and theend portions179, and the plurality ofdrain electrodes175 are formed on theohmic contacts163 and165 and thegate insulating layer140. Thedrain electrode175 may include a stick-shaped end portion, anexpansion177 connected to the stick-shaped end portion, and a transverse portion extending in a transverse direction from theexpansion177 and overlapping thestorage electrode line131.

Thepassivation layer180 is formed on the data lines171, thedrain electrodes175, and the exposed portions of thesemiconductors154. The dielectric constant of thepassivation layer180 may be low in a range of about 3 to about 3.5. Thepassivation layer180 may comprise an organic insulator that is relatively thick and the surface thereof may be flat.

Thepassivation layer180 has the plurality ofcontact holes182 and185 respectively exposing theend portions179 of the data lines171 and thedrain electrodes175. Thepassivation layer180 and thegate insulating layer140 have the plurality ofcontact holes181 exposing theend portions129 of the gate lines121.

The plurality ofpixel electrodes191 and the plurality ofcontact assistants81 and82 are formed on thepassivation layer180. Eachpixel electrode191 overlaps a gate line above eachpixel electrode191 to form a storage capacitor. Eachpixel electrode191 partially overlaps each data line171 to increase the aperture ratio. Since the dielectric constant of thepassivation layer180 is low and the thickness thereof is large, the parasitic capacitance generated by overlapping eachpixel electrode191, eachgate line121, and each data line171 can be reduced.

The alignment layer11 is formed on thepixel electrodes191 and thepassivation layer180.

Thelight blocking member220, thecolor filters230, theovercoat250, thecommon electrode270, and thealignment layer21 are sequentially formed on the insulatingsubstrate210.

According to an embodiment of the present invention, the number of data lines and data drivers can be reduced.

Although exemplary embodiments have been described with reference to the accompanying drawings, it is to be understood that the present invention is not limited to these precise embodiments but various changes and modifications can be made by one skilled in the art without departing from the spirit and scope of the present invention. All such changes and modifications are intended to be included within the scope of the invention as defined by the appended claims.

Claims (30)

What is claimed is:

1. A liquid crystal display comprising:

a substrate;

a plurality of gate lines formed on the substrate and extended in a first direction;

a plurality of data lines intersecting the plurality of gate lines and extended in a second direction;

a plurality of thin film transistors connected to the plurality of gate lines and the plurality of data lines; and

a plurality of pixel electrodes connected to the plurality of thin film transistors and arranged in a matrix,

wherein each of the pixel electrodes is formed in a substantially rectangular shape elongated in the first direction and includes a first side parallel to each gate line and a second side being formed next to the first side, wherein the length of the first side is about three times longer than the length of the second side,

wherein the plurality of pixel electrodes that are adjacent to each other in the second direction are connected to different data lines from each other.

2. The liquid crystal display ofclaim 1, further comprising a storage electrode line, wherein at least a portion of the storage electrode line overlaps a pixel electrode.

3. The liquid crystal display ofclaim 2, wherein the storage electrode line extends perpendicular to a gate line.

4. The liquid crystal display ofclaim 3, wherein the storage electrode line is located in the same layer as a data line.

5. The liquid crystal display ofclaim 3, wherein the storage electrode line comprises:

a plurality of first parts located in the same layer as the gate line and disposed between two adjacent gate lines; and

a plurality of second parts located in a different layer from the gate line, wherein the plurality of second parts intersect the gate line and connect the plurality of first parts with each other.

6. The liquid crystal display ofclaim 5, wherein each second part is located in the same layer as the pixel electrode.

7. The liquid crystal display ofclaim 3, wherein the storage electrode line includes at least one branch being adjacent to one of the plurality of gate lines and extending substantially parallel to the plurality of gate lines.

8. The liquid crystal display ofclaim 7, wherein a boundary of the pixel electrode is located on the at least one branch of the storage electrode line.

9. The liquid crystal display ofclaim 2, wherein the storage electrode line is substantially parallel to a gate line and arranged alternately with the gate line, wherein the storage electrode line is located in a same layer as the gate line.

10. The liquid crystal display ofclaim 9, wherein the thin film transistor comprises a drain electrode overlapping the storage electrode line.

11. The liquid crystal display ofclaim 9, wherein a boundary of the pixel electrode is located on the storage electrode line.

12. The liquid crystal display ofclaim 9, wherein the pixel electrode covers a gate line.

13. The liquid crystal display ofclaim 9, wherein a data line and the pixel electrode overlap each other.

14. The liquid crystal display ofclaim 13, further comprising an organic layer formed between the pixel electrode and the data line and between the pixel electrode and the gate line.

15. The liquid crystal display ofclaim 1, wherein a thin film transistor comprises:

a gate electrode connected to a gate line; a source electrode connected to a data line; and

a drain electrode connected to a pixel electrode, wherein the source electrode and the drain electrode have a substantially bilateral symmetry.

16. The liquid crystal display ofclaim 1, further comprising a gate driver connected to the plurality of gate lines, wherein the gate driver comprises:

a first gate driving circuit connected to first gate lines; and

a second gate driving circuit connected to second gate lines, wherein the first and the second gate driving circuits are located in a same layer as the plurality of gate lines, the plurality of data lines, and the plurality of thin film transistors.

17. The liquid crystal display ofclaim 16, wherein the first gate driving circuit and the second gate driving circuit are disposed opposite each other with respect to the substrate.

18. A liquid crystal display comprising:

a substrate;

a first gate line disposed on the substrate and extend in a first direction;

a second gate line parallel to the first gate line, and separated from the first gate line;

a first data line crossing the first gate line and extended in a second direction;

a second data line parallel to the first data line;

a first thin film transistor connected to the first gate line and the first data line;

a first pixel electrode connected to the first thin film transistor and including a first side parallel to the first gate line and a second side being formed next to the first side;

a second thin film transistor connected to the second gate line and the second data line;

a second pixel electrode connected to the second thin film transistor;

a first storage electrode disposed on the substrate and comprising a first line section and a first expansion expanding from the first line section; and

a second storage electrode disposed on the substrate and comprising a second line section and a second expansion expanding from the second line section,

wherein the first pixel electrode overlaps the first storage electrode,

wherein the first pixel electrode is formed in a substantially rectangular shape elongated in the first direction,

wherein the length of the first side is about three times longer than the length of the second side,

wherein the first pixel electrode and the second pixel electrode are disposed between the first data line and the second data line, and

wherein the first expansion is adjacent to the first data line and the second expansion is adjacent to the second data line, and

wherein a drain of the first thin film transistor comprises a third expansion overlapping the first expansion and a first stick-shaped end portion overlapping the first line section.

19. The liquid crystal display of claim 18, wherein the second storage electrode is disposed between the first gate line and the second gate line, and wherein the second pixel electrode overlaps the first storage electrode line and the second storage electrode line.

20. The liquid crystal display of claim 19, wherein the second pixel electrode covers the first gate line.

21. The liquid crystal display of claim 20, wherein a drain of the second thin film transistor comprises a fourth expansion overlapping the second expansion and a second stick-shaped end portion overlapping the second line section.

22. The liquid crystal display of claim 21, wherein the first pixel electrode and the second pixel electrode overlap the first data line and the second data line, respectively.

23. The liquid crystal display of claim 22, wherein the first thin film transistor is adjacent to the first data line, and

wherein the second thin film transistor is adjacent to the second data line.

24. The liquid crystal display of claim 18, further comprising:

a first gate driving circuit connected to the first gate line; and

a second gate driving circuit connected to the second gate line,

wherein the first and the second gate driving circuits are disposed on a same layer as the gate lines, the data lines, and the thin film transistors.

25. The liquid crystal display of claim 24, wherein the first gate driving circuit and the second gate driving circuit are disposed opposite each other with respect to the substrate.

26. The liquid crystal display of claim 18, wherein the first storage electrode is disposed on the same layer as the first gate line.

27. The liquid crystal display of claim 26, wherein the first pixel electrode overlaps the first line section or the first expansion.

28. The liquid crystal display of claim 18, wherein the second data line is disposed on opposite side of the first pixel electrode to the first data line.

29. The liquid crystal display of claim 28, wherein the first data line is adjacent to the second data line.

30. The liquid crystal display of claim 29, wherein the first pixel electrode is adjacent to the second pixel electrode.

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