USRE44246E1 - Method for containing a device and a corresponding device - Google Patents

Abstract

A method of enclosing a micromechanical element formed between a base layer and one or more metallization layers includes forming one or more encapsulating layers over the micromechanical element and providing an encapsulating wall surrounding the element extending between the base layer and the one or more encapsulating layers. An electrical connection is provided between the base layers and the one or more metallization layers formed above the micromechanical element.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of PCT/GB04/05122, filed Dec. 6, 2004, and titled “Method for Containing a Device and a Corresponding Device,” which claims priority to Great Britain Patent Application No. GB 0330010.0, filed on Dec. 24, 2003, and titled “Method for Containing a Device and a Corresponding Device,” the entire contents of which are hereby incorporated by reference.

FIELD OF THE INVENTION

The present invention relates to the encapsulation of micromechanical elements for use, in particular, but not exclusively, in semiconductor devices.

BACKGROUND

In recent years, the potential has escalated for the use of micromechanical elements in a variety of technical arenas such as semiconductor devices. Typically the micromechanical elements are integrated into semiconductor devices, and are housed in cavities or voids formed upon or within, for example, a complimentary metal oxide semiconductor (CMOS) device. While integrating the micromechanical element onto the CMOS substrate, it is equally important to provide adequate environmental protection for the micromechanical elements, and provide electrical connection to the upper layers of the circuit.

The micromechanical element could be moveable or non-moveable, for example, a charge transfer device movable between electrodes or a microfuse element which blows on the application of a suitable current. One of the principal concerns facing the micro-electromechanical systems (MEMS) industry is that the micromechanical elements are highly sensitive to their operational environments which include thermal, chemical and mechanical exposure which may be detrimental to the performance of the semiconductor device. Hence, it is desirable to provide such micromechanical elements with some form of protective seal or seals.

The device incorporating the micromechanical element may equally become damaged, for example, while being handled during subsequent packaging steps or to provide electrical connection to the upper circuit; hence, the need for suitable protection.

It can be appreciated that micromechanical elements require stringent measures of protection, therefore, it is an object of the present invention to provide reliable an enclosure for the micromechanical element in the form of hermetic seals, without increasing the size and cost of the devices. It can be seen therefore, that there is a need to fabricate reliable micromechanical elements for use in semiconductor devices.

SUMMARY

The present invention provides environmental protection for sensitive micromechanical elements, such as fuses or charge transfer elements, via hermetic layers formed above the elements while being integrated with the CMOS portions of the device. Additional sealing is provided laterally relative to the plane of the encapsulating layers by forming lateral walls embedded within the CMOS and encapsulating layers of the device.

This type of encapsulation is particularly advantageous as the protected micromechanical devices can be integrated into CMOS processes in every metallization sequence, other than the last metallization layer. The present invention permits the micromechanical element to be formed closer to the CMOS transistor levels of the device. This is particularly so since the base layers within which the micromechanical element is integrated tend to become thicker in the metallization steps far removed from the CMOS transistor levels.

An advantage of the present invention is that the encapsulation process of the present invention lends itself to standard CMOS processing. The formation of such devices is contingent upon the provision of traditional and modern industrial processes, for example, it is necessary that the planarizing steps include chemical mechanical processing (CMP). This technique is commonly used to planarize insulating and metal layers during the fabrication of a semiconductor device.

Therefore, according to the present invention, there is provided a method of enclosing a micromechanical element formed between a base layer and one or more metallization layers comprising: forming one or more encapsulating layers over the micromechanical element; providing an encapsulating wall surrounding the element extending between the base layer and the one or more encapsulating layers; and providing electrical connection between the base layers and the one or more metallization layers formed above the micromechanical element. The method may further comprise: depositing one or more encapsulating layers over at least part of the micromechanical element; planarizing the one or more encapsulating layers; forming one or more openings in the one or more encapsulating layers; applying one or more sacrificial layers contacting the micromechanical element; and removing the one or more sacrificial layers to expose the micromechanical element within a cavity.

The one or more openings formed in the one or more encapsulating layers may be exposed using dry etching.

Advantageously, the planarizing may recede the one or more encapsulating layers closer to the one or more sacrificial layers, and is carried out using chemical-mechanical polishing (CMP).

The one or more sacrificial layers may comprise different forms of the same materials or comprise different materials.

The one or more sacrificial layers may comprise an etchable Silicon-based material such as silicon nitride, silicon oxide or amorphous silicon. The materials may be etchable using fluorine-based compounds.

Advantageously, the one or more encapsulating layers may be formed from silicon-based materials such as silicon oxide, or silicon nitride.

One or more sacrificial layers can be deposited using plasma enhanced chemical vapor deposition (PECVD).

The operation of removing the one or more sacrificial layers can include introducing an etchant through the one or more openings in the one or more encapsulating layers.

The one or more sacrificial layers may comprise an etchable polymer-based material such as polyimide, which may be etched using an oxygen plasma.

The walls may be formed from one or more stacked plugs. Further, the plugs may also provide electrical connection between the base layer and the uppermost metallization layers of the underlying the micromechanical element.

Advantageously, the wall members may extend through the dielectric layer and the encapsulating layers.

In another aspect of the present invention, there is provided, a semiconductor device comprising: a micromechanical element formed on a base layer; one or more encapsulating layers disposed over the micromechanical element and an encapsulating wall surrounding the micromechanical element extending from the base layer into the one or more encapsulating layers.

In yet a further aspect of the present invention, there is provided a method of forming a micromechanical element comprising: providing a base layer that may be patterned; applying one or more sacrificial layer of an etchable material; patterning the one or more sacrificial layer to define at least a portion of the shape of the element; applying at least one layer defining a mechanical material; patterning the micromechanical element to form at least a portion of the element; and removing part of sacrificial layer to at least partly free the element.

The above and still further features and advantages of the present invention will become apparent upon consideration of the following definitions, descriptions and descriptive figures of specific embodiments thereof wherein like reference numerals in the various figures are utilized to designate like components. While these descriptions go into specific details of the invention, it should be understood that variations may and do exist and would be apparent to those skilled in the art based on the descriptions herein.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings in which:

FIG. 1 shows a cross section of the device after forming the micromechanical element and depositing the first encapsulating layer;

FIG. 2 shows a cross section of the device after planarization of the first encapsulation layer followed by via formation through the first encapsulation layer;

FIG. 3 shows a cross section of the device incorporating on the tungsten plugs a conducting layer and TiN contact layer;

FIG. 4 shows a cross section of the device wherein an opening is formed in the first encapsulation layer, with the formation of the opening impeded by the stop layer;

FIG. 5 shows a cross section of the device in which the micromechanical element is released by exposing the sacrificial layers to a release etch passed through the opening, the release being effected up to the encapsulating wall;

FIG. 6 shows a cross section of the device in which a second encapsulation layer is deposited over the device; and

FIG. 7 shows a plan view of the device according to the present invention wherein the encapsulating wall forms a lateral enclosure surrounding the micromechanical element.

FIGS. 8a-8g show schematics of the different steps applied to form a micromechanical element for which encapsulation may be provided.

DETAILED DESCRIPTION

FIG. 1 shows the device of the present invention embodied in the standard CMOS starting base layers, which would be familiar to those skilled in the art, within which the micromechanical element is formed comprising:base layer1, which would be disposed on the CMOS transistor levels (not shown); dielectric3,metal interconnects5,7,9,11 and via plugs formed at13,15,17,19 for providing electrical contact between the CMOS substrate layers beneath thebase layers1, themicromechanical element28 integrated thereon and contacts to the upper metal interconnect layers.

Referring toFIG. 1, theplugs13,15,17,19 are formed using standard CMOS processes, for example, thetungsten plugs15,17, and19 are formed by etching a via which is lined withTiN liner21, for example, of a predetermined thickness and subsequently deposited with a tungsten (W) filling. Surplus W deposited over a substantial part of the device is etched back to theTiN layer21 as shown. This is followed by capping over the device asecond TiN layer23 which is patterned together withTiN layer21 and selectively etched back to thedielectric layer3 as shown.

Portions of theTiN layer23 together withTiN layer21 will form contacts and/or electrodes for enabling operation of the device100. Next a firstsacrificial layer25, for example Silicon Nitride, is deposited over the dielectric3 andTiN layer23 overlaying theTiN layer21 followed by selective etching thereof.

Again referring toFIG. 1, material forming themicromechanical element28 is deposited in the next layer over the device100, which is selectively patterned and etched to define the structure of themicromechanical element28. Once themicromechanical element28 has been formed, and before themicromechanical element28 is released, additional process sequences are introduced to initiate the encapsulation stages of the micromechanical element.

A secondsacrificial layer30 is deposited over the layer comprising themicromechanical element28 and the firstsacrificial layer25 as shown inFIG. 1. The secondsacrificial layer30 which is amenable to physical or chemical vapor deposition technology is applied on theTiN layer23 using Plasma Enhanced Chemical Vapor Deposition (PECVD) or other conventional methods known to the skilled person in the art. Thesacrificial layer30 may preferably be formed from silicon-based materials such as silicon nitride, silicon oxide, amorphous silicon or spin on glass (SOG) materials.

Thesacrificial layer30 should be selected so as to have the desired properties, for example, the etchable material should permit isotropic or non-isotropic etching and should not impose unfavorable reactions with sensitive micromechanical elements.

Further silicon nitride or polyimide could be used for the both the firstsacrificial layer25 and secondsacrificial layer30. A hydrogen-rich silicon nitride layer can increase the etch rate, for example, the different hydrogen contents in the silicon nitride can make the etch rate change by a factor of ten. Hydrogen content can be controlled by controlling the silane and ammonia ratios during plasma processing of the layer.

To provide a hermetic seal so as to protect themicromechanical element28 from environmental exposure, afirst encapsulating layer33 is deposited on the device.

This operation involves an oxide deposition process to apply on the second sacrificial layer30 a micromachinable insulating material such as Silicon Oxide. Preferably, the oxide forming the first encapsulating layer is deposited using Chemical Vapor Deposition (CVD), which substantially coversmicromechanical element28, as shown inFIG. 1.

According to one aspect of the invention, the uneven surface topography resulting from the previous step as shown inFIG. 1 is further processed. In a next step, chemical-mechanical polishing (CMP), which provides a rapid and effective method for substantially planarizing topographies, is used to recede thefirst encapsulating layer33 to a predetermined level spaced from thesacrificial layer30. CMP may be readily applied at any level in the deposition procedures described herein. Moreover, the use of CMP at this stage of the invention on thefirst encapsulating layer33 enables the encapsulation method of the present invention to be integrated into the CMOS in every metallization sequence, in particular closer to the base layer.

In the next stage, at least part of the device ofFIG. 1 is masked so as to permit the formation of via26 and via32 on the right hand side of the micromechanical element shown in theFIG. 2. In this step, a tungsten plug is introduced which can also be used to make a lateral seal ring around themicromechanical element28.

As shown inFIG. 2, a masking step is implemented to etch via26 and via32 through a portion of the CMP-treatedfirst encapsulation layer33 and secondsacrificial layer30, followed by the deposition of (to provide a conducting path between electrical contacts which may lie above and below the oxide layer) a TiN lining27 for the via26 and via32. The openings are etched by a technique incorporating a plasma.

In a next step, the TiN-lined vias are filled with tungsten deposited by CVD to form viaplugs28,29, and again the superfluous material may be dry etched or planarized using CMP to the aforementioned predetermined level spaced from thesacrificial layer30, as shown inFIG. 3. CMP may be effective in removing any excess W or TiN filling encroaching above the vias, thereby planarizing the excess filling deposit so that it is level with the surface of the oxide forming thefirst encapsulating layer33. It is important to prevent accidental removal of the W filling material from inside the vias as this may interfere with subsequent deposition steps and impair electrical contact.

Referring toFIG. 3, in a next step, the Aluminum (Al)/copper (Cu)metallization layer40 is applied over the device by further patterning and etching stages so as to form aconducting layer42 over the W plugs29, as shown inFIG. 3.Metallization layer40 is deposited further with an additional thin film ofcontact metal42, made from TiN, to promote good electrical contact. This layer is patterned and etched using techniques that would be familiar to the skilled in the art.

In the present invention,FIG. 3 shows that awall44 comprising the tungsten plugs is formed around themicromechanical element28, while the tungsten plugs and the interconnecting layers applied thereon serve to form the metal interconnects which permit electrical connection between the upper and lower layers of the device, and the underlying CMOS transistor levels.

In a next step, represented in the cross section ofFIG. 4, first encapsulation layer33 (LHS) is patterned using a mask so as to etch anopening46 which is exposed by etching through theoxide encapsulation layer33 and partially through the secondsacrificial layer30 until further etching of theopening46 is impeded at abarrier48, composed of TiN, formed during the micromechanical element formation described hereinbefore. Typically, the etching step is effected by a technique incorporating a plasma. The TiN barrier should be sufficiently inert to the etching step so as to prevent the etching of an opening through the underlyingdielectric layer3, which would be detrimental to the performance of the device.

In a further step shown inFIG. 5, an etch release process step frees themicromechanical element28 such that, in use, it is operable withincavity50. Introducing an etching agent through opening46 effects the removal of the firstsacrificial layer25 and secondsacrificial layer30 so as to free themicromechanical element28. The removal of thesacrificial layer25 andsacrificial layer30 involve a dry etching process such as a fluorine-based etch like SF6.FIG. 5 shows that thewall44 formed from tungsten plugs has a two fold function: it prevents the etching substances from releasing themicromechanical element28 beyond thewall44 and it forms a lateral sealing wall surrounding themicromechanical element28. The latter provides protection for the micromechanical element in its operating environment or alternatively could be an additional electrode above themicromechanical element28.

It is important that the structural integrity of themicromechanical element28 is not impaired owing to detrimental reaction of the etching agent with themicromechanical element28. This is achieved by selecting suitable chemically compatible materials and conditions of the release etch process and the equipment in which the process is carried out.

In a next step shown inFIG. 6, asecond encapsulation layer60 is deposited over the device, namely over the first encapsulation layer and themetallization portion42 so as to provide a further hermetic seal. The second encapsulating material may be selected from a nitride material, for example silicon nitride. Given the relative sizes of the openings46 (FIG. 5) and thecavity50 containing themicromechanical element28, the deposition conditions for applying thesilicon nitride layer60 are controlled so as to ensure that the hole is plugged. In particular, theopening46 is far removed from the micromechanical element so as to prevent deposition thereon.

FIG. 7 shows a plan view of an embodiment of the present invention, wherein thewall44 is disposed laterally to surround themicromechanical element28. Release of themicromechanical element28 is effected, for example, by passing the etchant through therelease opening46.

FIGS. 8a-8g show schematics of the different steps applied to form a micromechanical element for which encapsulation may be provided. Referring toFIG. 8a, In a first step aconducting layer2 of nitrogen-rich titanium nitride is deposited onsubstrate1. This can be achieved using reactive sputtering.

In a second step, depicted inFIG. 8b, theconducting layer2 is patterned and etched by techniques that are normal in the micro-electronics industry using process equipment commonly available in most semiconductor fabrication facilities. Thus, a non-moveable lowerfirst electrode11 is formed.

In a third step, depicted inFIG. 8c, asacrificial layer3 of a silicon-based material is deposited on the patternedconductive layer2′, possibly after a special surface treatment of theconductive layer2 or the patternedconductive layer2′. Amorphous silicon or silicon nitride may be used, or any other silicon-based material that has suitable properties, specifically including sputtered amorphous silicon and silicon nitride deposited by PECVD (Plasma-Enhanced Chemical Vapor Deposition). Furthermore, an etch process exists that can etch these materials isotropically or near isotropically, selectively with respect to titanium nitride with a limited and controlled amount of etch into the titanium nitride material.

In a fourth step, depicted inFIG. 8d, thesacrificial layer3 is patterned and etched by techniques that are normal in the micro-electronics industry using process equipment commonly available in most semiconductor fabrication facilities.

In a fifth step shown inFIG. 8e,structural layer4 of Nitrogen rich titanium nitride is deposited on the patterned sacrificial layer, preferably using bias sputtering so as to control the properties of theconducting layer2. Further, deposition may be controlled so as to achieve good electrical contact between thepatterned conducting layer2′ and thestructural layer4′ where these two layers make contact in the completedmicromechanical element10.

In a sixth step shown inFIG. 8f, thestructural layer4 is patterned and etched in a manner similar to that described in the second step. In a seventh step, shown inFIG. 8g, theelement10 is partially released by etching away the patternedsacrificial layer3′ in a plasma etch system using fluorine-based etch. The plasma system may be of a dual radio frequency system.

The skilled artisan will appreciate that the present invention may be applied for encapsulating movable and non-movable micromechanical elements such as a fuse, switches or other charge transfer elements operable within a cavity.

Having described preferred embodiments of the invention, it is believed that other modifications, variations and changes will be suggested to those skilled in the art in view of the teachings set forth herein. It is therefore to be understood that all such variations, modifications and changes are believed to fall within the scope of the present invention as defined by the appended claims. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.

Claims (30)

What is claimed is:

1. A method of enclosing a micromechanical element formed between a base layer and one or more metallization layers comprising:

forming a first encapsulating layer over at least part of the micromechanical element;

depositing a second encapsulating layer over the first encapsulating layer and providing an encapsulating wall surrounding the micromechanical element to form a lateral sealing wall extending between the base layer and the one or more encapsulating layers;

depositing the one or more metallization layers over the first encapsulating layer;

providing electrical connection between the base layer and the one or more metallization layers formed above the micromechanical element;

etching through the first encapsulating layer and a sacrificial layer disposed therebelow to form an opening through the first encapsulating layer and the sacrificial layer;

introducing an etching agent through the opening; and

removing the sacrificial layer, wherein the micromechanical element is disposed in a cavity that is at least partially bordered by the encapsulating wall.

2. The method according toclaim 1, wherein the encapsulating wall comprises a via filled with tungsten.

3. The method according toclaim 1, wherein the encapsulating wall comprises a via that is lined with TiN and filled with tungsten.

4. The method according toclaim 3, wherein the encapsulating wall provides an electrical connection between the base layer and the one or more metallization layers.

5. The method according toclaim 1, wherein the encapsulating wall extends through the base layer and the first and second encapsulating layers.

6. The method according toclaim 1, wherein the encapsulating wall is formed from one or more stacked plugs.

7. The method according toclaim 6, wherein the one or more stacked plugs provide electrical connection between the base layer and the one or more metallization layers.

8. The method according toclaim 7, wherein the one or more stacked plugs comprises a TiN liner and tungsten fill.

9. A method of forming and enclosing a micromechanical element between a base layer and one or more metallization layers, comprising:

applying a first sacrificial layer of an etchable material over at least a portion of the base layer;

patterning the first sacrificial layer to define at least a portion of the shape of the micromechanical element;

applying at least one layer of a micromechanical element material over at least a portion of the first sacrificial layer;

patterning the micromechanical element material to form at least a portion of the micromechanical element;

applying a second sacrificial layer of an etchable material over the micromechanical element;

applying a first encapsulating layer over at least a portion of the second sacrificial layer;

depositing a second encapsulating layer over the first encapsulating layer and providing an encapsulating wall surrounding the micromechanical element to form a lateral sealing wall extending between the base layer and the one or more encapsulating layers;

depositing the one or more metallization layers over the first encapsulating layer;

providing electrical connection between the base layer and the one or more metallization layers;

etching through the first encapsulating layer and the second sacrificial layer to form an opening through the first encapsulating layers and the second sacrificial layer;

introducing an etching agent through the opening; and

removing at least part of the first and second sacrificial layers to at least partly free the micromechanical element, wherein the micromechanical element is disposed in a cavity that is at least partially bordered by the encapsulating wall.

10. The method according toclaim 9, wherein the first and second sacrificial layers comprise an etchable silicon-based material.

11. The method according toclaim 9, wherein the first and second sacrificial layers comprise an etchable polymer-based material.

12. The method according toclaim 9, wherein the first or second sacrificial layers comprise an etchable silicon-based material.

13. The method according toclaim 9, wherein the first or second sacrificial layers comprise an etchable polymer-based material.

14. The method according toclaim 9, further comprising planarizing the first encapsulating layer.

15. The method according toclaim 14, wherein the planarizing comprises chemical-mechanical polishing.

16. The method according toclaim 9, wherein the encapsulating wall comprises a via filled with tungsten.

17. The method according toclaim 9, wherein the encapsulating wall comprises a via that is lined with TiN and filled with tungsten.

18. The method according toclaim 9, wherein the encapsulating wall extends through the base layer and the one or more encapsulating layers.

19. The method according toclaim 9, wherein the encapsulating wall provides an electrical connection between the base layer and the one or more metallization layers.

20. The method according toclaim 9, wherein the encapsulating wall is formed from one or more stacked plugs.

21. The method according toclaim 20, wherein the one or more stacked plugs provide electrical connection between the base layer and the one or more metallization layers.

22. The method according toclaim 21, wherein the one or more stacked plugs comprises a TiN liner and tungsten fill.

23. A method of enclosing a micromechanical element, comprising:

forming a first encapsulating layer over at least part of the micromechanical element;

depositing a second encapsulating layer over the first encapsulating layer and providing an encapsulating wall surrounding the micromechanical element to form a lateral sealing wall extending between the base layer and the one or more encapsulating layers;

depositing one or more metallization layers over the first encapsulating layer to provide an electrical connection between the base layer and the one or more metallization layers formed above the micromechanical element; and

freeing the micromechanical element disposed between the one or more metallization layers and the base layer, the freeing comprising:

etching through the first encapsulating layer and a sacrificial layer disposed therebelow to form an opening through the first encapsulating layer and the sacrificial layer;

introducing an etching agent through the opening; and

removing the sacrificial layer, wherein the micromechanical element is disposed in a cavity that is at least partially bordered by the encapsulating wall.

24. The method according to claim 23, wherein the encapsulating wall comprises tungsten.

25. The method according to claim 23, wherein the encapsulating wall comprises titanium nitride.

26. The method according to claim 25, wherein providing the encapsulating wall comprises forming the encapsulating wall between the base layer and the one or more metallization layers to provide an electrical connection therebetween.

27. The method according to claim 23, wherein providing the encapsulating wall comprises forming the encapsulating wall to extend through the base layer and the first and second encapsulating layers.

28. The method according to claim 23, wherein providing the encapsulating wall comprises forming one or more stacked plugs.

29. The method according to claim 28, wherein forming the one or more stacked plugs comprises forming the one or more stacked plugs to provide an electrical connection between the base layer and the one or more metallization layers.

30. The method according to claim 29, wherein forming the one or more stacked plugs comprises forming a titanium nitride liner and a tungsten fill.

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