USRE42658E1 - Gate driver multi-chip module - Google Patents
Gate driver multi-chip moduleDownload PDFInfo
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- USRE42658E1 USRE42658E1US11/787,234US78723407AUSRE42658EUS RE42658 E1USRE42658 E1US RE42658E1US 78723407 AUS78723407 AUS 78723407AUS RE42658 EUSRE42658 EUS RE42658E
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
- H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
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- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H02M3/00—Conversion of DC power input into DC power output
- H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
- H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
- H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
- H02M3/1588—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load comprising at least one synchronous rectifier element
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Definitions
- the present inventionrelates to a multi-chip module (MCM). More specifically, the present invention relates to an MCM power circuit for a computer motherboard.
- MCMmulti-chip module
- Power supply circuitrytypically occupies a substantial area on a computer motherboard. It would be desirable to reduce the size of the power circuitry on a computer motherboard without sacrificing performance.
- the present inventionprovides an MCM which includes a MOSFET gate driver, two power MOSFETs, and associated passive elements including an input capacitor all mounted on a ball grid array (BGA) substrate and packaged in a single chip.
- BGAball grid array
- the power MOSFETs of the MCM of the present inventionare connected in a half-bridge arrangement between an input voltage and ground.
- the MOSFET gate driveris connected to respective gate inputs of the two power MOSFETs, and alternately switches the power MOSFETs to generate an alternating output voltage at a common output node between the power MOSFETs.
- At least one Schottky diodeis disposed on the BGA substrate and connected between a common output node and ground to minimize losses during deadtime conduction periods.
- the passive circuit componentsinclude an input capacitor connected between the input voltage and ground which provides input capacitance for the converter.
- the input capacitoris physically close to all other components. Additional components provide appropriate biasing for the gate driver. All components are encased in a molding compound to form the MCM package.
- the location of the input capacitor within the MCM packageprovides layout independence for the mother board, which no longer needs to contain that capacitor (at a distance from the MOSFETs in the MCM package).
- the capacitoracts as a bypass to conduction of unintended current (with a high di/dt) through the body diode of one of the MOSFETs in the package and acts to help clamp the Q RR (reverse recovery charge) of the MOSFET.
- the modulepreferably is enclosed in a package that has side dimensions of about 11 mm ⁇ 11 mm (i.e., about 1 cm ⁇ 1 cm) or less. Accordingly, the input capacitor is located less than 1 cm from the MOSFET.
- the MCM of the present inventionadvantageously results in a 50% reduction in size with no performance trade off and is printed circuit board (PCB) independent.
- PCBprinted circuit board
- the packageadvantageously provides a performance increase over the discrete solution.
- FIG. 1is a plan view drawing of the co-packaged active and passive components in the MCM of the present invention.
- FIG. 2is an elevation view drawing of an MCM according to the present invention.
- FIG. 3is a circuit schematic of an MCM according to the present invention.
- FIG. 3Ais an equivalent circuit diagram of a portion of FIG. 3 .
- FIG. 4is a timing diagram for an MCM according to the present invention.
- MCM 2includes six die mounted on a BGA substrate 4 .
- a plurality of bonding pads 6are disposed on the upper surface of substrate 4 .
- Die 8 and 10are power MOSFETs, preferably IRFC7811A and IRFC7809A power MOSFETs, respectively, mounted in a half-bridge configuration.
- Die 12is a MOSFET gate driver, preferably a Semtech SC1405 High Speed Synchronous Power MOSFET Smart Driver.
- Die 14 , 16 , and 18are Schottky diodes, preferably SKM863 diodes, connected as shown in the circuit schematic of FIG. 3 .
- the active components mounted on the upper surface of substrate 4are connected electrically to corresponding bonding pads 6 using wire bonds 20 .
- the passive components shown in FIG. 1include resistor R 1 , and capacitors C 1 , C 2 , C 3 , and C 4 , also connected as shown in the circuit schematic of FIG. 3 .
- the passive componentsare shown bonded directly to corresponding pads 6 .
- capacitor C 4is mounted close to MOSFETs 8 and 10 .
- MCM 2 of the present inventionis shown in elevation.
- a plurality of solder balls 22are arranged on the lower surface of substrate 4 .
- the components on the upper surface of substrate 4are encapsulated in a mold compound 24 such as Nitto HC 100.
- the dimension of housing 2is about 1 cm ⁇ 1 cm so it will take very little space on a mother board.
- FIG. 3a circuit schematic of power supply MCM 2 is shown.
- Power MOSFETs 8 and 10are mounted in a half-bridge configuration, connected in series between an input voltage V IN and ground P GND .
- External circuit capacitance C EXTis connected to V IN .
- a high-side output gate drive TG of MOSFET gate driver 12is connected to a gate input 20 of high-side power MOSFET 8 .
- a low-side output gate drive BG of MOSFET gate driver 12is connected to a gate input 22 of low-side power MOSFET 10 .
- Gate driver 12alternately switches the power MOSFETs to generate an alternating output voltage at a common output node SW NODE between the power MOSFETs.
- Schottky diodes 16 and 18are connected between common output node SW NODE and ground to minimize losses during dead time conduction periods.
- An input capacitor C 4is connected between the input voltage V IN and ground P GND .
- the use of two parallel diodes 16 and 18helps in keeping a symmetrical layout of components.
- An output inductor 30generally will be connected to the SW NODE and to the output voltage terminal V OUT .
- An output capacitor C OUTis also in the output circuit.
- a supply voltage V DDis provided to MOSFET gate driver 12 on pin V CC .
- a bootstrap circuitconsisting of Schottky diode 14 , and resistor R 1 /capacitor C 2 connected between the bootstrap pin BST and the DRN pin, is provided to develop a floating bootstrap voltage for high-side MOSFET 8 .
- a TTL-level input signalis provided on line DRV_IN to MOSFET driver pin CO. Operation of the device is enabled by providing a minimum of 2.0 volts on enable pin EN of MOSFET driver 12 .
- Status pin P RDYindicates the status of the +5V supply voltage. When the supply voltage is less than 4.4V, this output is driven low. When the supply voltage is greater than 4.4V, this output is driven high. This output has a 10 mA source and 10 ⁇ A capability. When P RDY is low, undervoltage circuitry built into driver 12 guarantees that both driver outputs TG and BG are low.
- a timing diagram for MCM 2is shown.
- a turn on delay t D(ON) of typically 63 nsexists between the signal input DRV_IN and output SW NODE of MCM 2 .
- a turn off delay t D(OFF) of typically 26 nsexists between the signal input DRV_IN and output SW NODE of MCM 2 .
- a portion of the delayis inherent in driver 12 .
- the supply voltagecan range between 4.2 and 6.0 V. Input voltages of between 5 and 12 volts can be used, providing an output voltage range of 0.9-2.0 V. Output current is typically 15A.
- the deviceoperates at frequencies from 300-1,000 kHz.
- MOSFET 10has a parasitic capacitance C OSS .
- the circuit including the stray inductance L and C OSStends to ring at its resonant frequency. By reducing L, the ring is also reduced.
- FIG. 3Ais an equivalent circuit of portions of FIG. 3 showing in particular the body diode of MOSFET 10 .
- FIG. 3Ashows in particular the body diode of MOSFET 10 .
- the dead timeduring which both MOSFETs 8 and 10 are off, conduction takes place through Schottky diodes 16 and 18 of FIG. 3 , but some “residual” current also is conducted through the body diode of MOSFET 10 .
- MOSFET 8turns on while the body diode of MOSFET 10 is conducting, a reverse recovery current will be fed from the external capacitor C EXT with very high di/dt.
- Capacitor C 4will act as a bypass to this high di/dt.
- the capacitor C 4 of FIG. 3serves similar purposes.
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Dc-Dc Converters (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electronic Switches (AREA)
Abstract
Description
This is a continuation of U.S. patent application Ser. No. 09/813,011, filed Mar. 21, 2001 abandoned, which is based upon and claims priority of U.S. Provisional Application Ser. No. 60/191,125, filed Mar. 22, 2000.
1. Field of the Invention
The present invention relates to a multi-chip module (MCM). More specifically, the present invention relates to an MCM power circuit for a computer motherboard.
2. Description of the Related Art
Power supply circuitry typically occupies a substantial area on a computer motherboard. It would be desirable to reduce the size of the power circuitry on a computer motherboard without sacrificing performance.
The present invention provides an MCM which includes a MOSFET gate driver, two power MOSFETs, and associated passive elements including an input capacitor all mounted on a ball grid array (BGA) substrate and packaged in a single chip.
The power MOSFETs of the MCM of the present invention are connected in a half-bridge arrangement between an input voltage and ground. The MOSFET gate driver is connected to respective gate inputs of the two power MOSFETs, and alternately switches the power MOSFETs to generate an alternating output voltage at a common output node between the power MOSFETs. At least one Schottky diode is disposed on the BGA substrate and connected between a common output node and ground to minimize losses during deadtime conduction periods.
The passive circuit components include an input capacitor connected between the input voltage and ground which provides input capacitance for the converter. Advantageously, the input capacitor is physically close to all other components. Additional components provide appropriate biasing for the gate driver. All components are encased in a molding compound to form the MCM package.
By mounting the input capacitor very close to other components and within the very small package, a number of advantages are realized, as follows:
First, there is a very low stray inductance between the input capacitor and the MOSFETs which reduces the “ring” that would be caused in the circuit including the MOSFET parasitic capacitance COSSand the stray inductance L. Reducing the inductance reduces the circuit ring.
Second, the location of the input capacitor within the MCM package provides layout independence for the mother board, which no longer needs to contain that capacitor (at a distance from the MOSFETs in the MCM package).
Third, the capacitor acts as a bypass to conduction of unintended current (with a high di/dt) through the body diode of one of the MOSFETs in the package and acts to help clamp the QRR(reverse recovery charge) of the MOSFET.
The module preferably is enclosed in a package that has side dimensions of about 11 mm×11 mm (i.e., about 1 cm×1 cm) or less. Accordingly, the input capacitor is located less than 1 cm from the MOSFET.
The MCM of the present invention advantageously results in a 50% reduction in size with no performance trade off and is printed circuit board (PCB) independent. The package advantageously provides a performance increase over the discrete solution.
Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.
Referring toFIG. 1 , a diagram of a preferred layout forMCM 2 of the present invention is shown. MCM2 includes six die mounted on a BGA substrate4. A plurality ofbonding pads 6 are disposed on the upper surface of substrate4.
Die8 and10 are power MOSFETs, preferably IRFC7811A and IRFC7809A power MOSFETs, respectively, mounted in a half-bridge configuration. Die12 is a MOSFET gate driver, preferably a Semtech SC1405 High Speed Synchronous Power MOSFET Smart Driver. Die14,16, and18 are Schottky diodes, preferably SKM863 diodes, connected as shown in the circuit schematic ofFIG. 3 . The active components mounted on the upper surface of substrate4 are connected electrically tocorresponding bonding pads 6 usingwire bonds 20.
The passive components shown inFIG. 1 include resistor R1, and capacitors C1, C2, C3, and C4, also connected as shown in the circuit schematic ofFIG. 3 . The passive components are shown bonded directly tocorresponding pads 6. Significantly, capacitor C4 is mounted close toMOSFETs
Referring toFIG. 2 ,MCM 2 of the present invention is shown in elevation. A plurality ofsolder balls 22 are arranged on the lower surface of substrate4. In the finished package, the components on the upper surface of substrate4 are encapsulated in amold compound 24 such as Nitto HC 100. The dimension ofhousing 2 is about 1 cm×1 cm so it will take very little space on a mother board.
Referring toFIG. 3 , a circuit schematic ofpower supply MCM 2 is shown.Power MOSFETs MOSFET gate driver 12 is connected to agate input 20 of high-side power MOSFET 8. A low-side output gate drive BG ofMOSFET gate driver 12 is connected to agate input 22 of low-side power MOSFET 10.Gate driver 12 alternately switches the power MOSFETs to generate an alternating output voltage at a common output node SW NODE between the power MOSFETs.
A supply voltage VDDis provided toMOSFET gate driver 12 on pin VCC. A bootstrap circuit, consisting of Schottkydiode 14, and resistor R1/capacitor C2 connected between the bootstrap pin BST and the DRN pin, is provided to develop a floating bootstrap voltage for high-side MOSFET 8.
A TTL-level input signal is provided on line DRV_IN to MOSFET driver pin CO. Operation of the device is enabled by providing a minimum of 2.0 volts on enable pin EN ofMOSFET driver 12. Status pin PRDYindicates the status of the +5V supply voltage. When the supply voltage is less than 4.4V, this output is driven low. When the supply voltage is greater than 4.4V, this output is driven high. This output has a 10 mA source and 10 μA capability. When PRDYis low, undervoltage circuitry built intodriver 12 guarantees that both driver outputs TG and BG are low.
Referring toFIG. 4 , a timing diagram forMCM 2 is shown. A turn on delay tD(ON)of typically 63 ns exists between the signal input DRV_IN and output SW NODE ofMCM 2. A turn off delay tD(OFF)of typically 26 ns exists between the signal input DRV_IN and output SW NODE ofMCM 2. A portion of the delay is inherent indriver 12.
The supply voltage can range between 4.2 and 6.0 V. Input voltages of between 5 and 12 volts can be used, providing an output voltage range of 0.9-2.0 V. Output current is typically 15A. The device operates at frequencies from 300-1,000 kHz.
The operation of the circuit ofFIG. 3 is considerably enhanced by the inherently close spacing between input capacitor C4 andMOSFET 10.
First, the removal of capacitor C4 from the mother board increases layout flexibility for the mother board.
Second, since the capacitor C4 is very close toMOSFETs FIG. 3 ,MOSFET 10 has a parasitic capacitance COSS. The circuit including the stray inductance L and COSStends to ring at its resonant frequency. By reducing L, the ring is also reduced.
A third benefit of capacitor C4 is that it clamps QRR(reverse recovery charge) ofMOSFET 10 and keeps high di/dt from flowing out ofmodule 2 and into the mother board. More specifically,FIG. 3A is an equivalent circuit of portions ofFIG. 3 showing in particular the body diode ofMOSFET 10. During the dead time, during which bothMOSFETs Schottky diodes FIG. 3 , but some “residual” current also is conducted through the body diode ofMOSFET 10. WhenMOSFET 8 turns on while the body diode ofMOSFET 10 is conducting, a reverse recovery current will be fed from the external capacitor CEXTwith very high di/dt. Capacitor C4, however, will act as a bypass to this high di/dt. The capacitor C4 ofFIG. 3 serves similar purposes.
Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art.
Claims (13)
1. A multi-chip module (MCM) for providing power circuitry on a computer motherboard, comprising:
a ball grid array (BGA) substrate having a first surface and a second opposing surface;
two power MOSFETs disposed on the first surface of the BGA substrate and connected in a half-bridge arrangement between an input voltage and ground;
a MOSFET gate driver disposed on the first surface of the BGA substrate and electrically connected to respective gate inputs of the two power MOSFETs for alternatively switching the power MOSFETs to generate an alternating output voltage at a common output node between the power MOSFETs; and
at least one diode disposed on the first surface of the BGA substrate and connected between the common output node and ground to minimize losses during deadtime connection periods; and
an input capacitor disposed on the first surface of the BGA and connected between the input voltage and ground;
wherein the input capacitor is located adjacent to, and spaced less than 1 cm from the first and second MOSFETs, and wherein the input capacitor and the first and second MOSFETs are positioned side-by-side.
2. The module ofclaim 1 , further comprising another diode connected in parallel with the diode connected between the common output node and between the common output node and ground.
3. The module ofclaim 1 , wherein the substrate has an area of about 1 cm by 1 cm or less.
4. The module ofclaim 1 , which further includes an insulation housing enclosing the substrate, the MOSFETs, the gate driver and the at least one diode, the ball grid array being exposed through the bottom of the housing for mounting to a mother board.
5. A multichip module comprising:
a substrate having a first surface and an opposing second surface;
a power input connection;
a ground connection;
two power switching devices disposed on said first surface of said substrate and connected in series according to a half-bridge arrangement between said power input connection and said ground connection, a terminal of one of said two power switching devices directly connected to said power input connection and a terminal of another of said two power switching devices directly connected to said ground connection; and
an input capacitor connected between said power input connection and said ground connection, wherein said input capacitor is disposed on said first surface of said substrate and spaced no more than one centimeter from said two either power switching devices device, and wherein said input capacitor and said power switching devices are positioned side-by-side.
6. A The multichip module according toclaim 5 , wherein said power switching devices are MOSFETs.
7. A The multichip module according toclaim 5 , wherein said substrate is a ball grid array.
8. A The multichip module according toclaim 5 , wherein said half-bridge connection includes an output node located between said two power switching devices, and further comprising at least one Schottky diode connected between said output node and said ground connection.
9. A The multichip module according toclaim 8 , further comprising another Schottky diode connected between said output node and said ground connection.
10. A The multichip module according toclaim 5 , further comprising a controller disposed on said substrate for selective control of the operation of said two power switching devices.
11. A The multichip module according toclaim 5 , wherein said multichip module is 1 cm by 1 cm or less.
12. A The multichip module according toclaim 5 , wherein said input capacitor reduces the stray inductance to reduce the ringing due to resonance in said at least one of said two power switching devices.
13. A The multichip module according toclaim 5 , wherein said input capacitor is disposed on said substrate and spaced no more than one centimeter from the low side power switching device in said half-bridge arrangement.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/787,234USRE42658E1 (en) | 2000-03-22 | 2007-04-12 | Gate driver multi-chip module |
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US19112500P | 2000-03-22 | 2000-03-22 | |
| US09/813,011US20020021560A1 (en) | 2000-03-22 | 2001-03-21 | Gate driver multi-chip module |
| US10/252,988US6879491B2 (en) | 2000-03-22 | 2002-09-23 | Gate driver multi-chip module |
| US11/787,234USRE42658E1 (en) | 2000-03-22 | 2007-04-12 | Gate driver multi-chip module |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US10/252,988ReissueUS6879491B2 (en) | 2000-03-22 | 2002-09-23 | Gate driver multi-chip module |
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| USRE42658E1true USRE42658E1 (en) | 2011-08-30 |
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| US10/252,988CeasedUS6879491B2 (en) | 2000-03-22 | 2002-09-23 | Gate driver multi-chip module |
| US11/787,234Expired - LifetimeUSRE42658E1 (en) | 2000-03-22 | 2007-04-12 | Gate driver multi-chip module |
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| US09/813,011AbandonedUS20020021560A1 (en) | 2000-03-22 | 2001-03-21 | Gate driver multi-chip module |
| US10/252,988CeasedUS6879491B2 (en) | 2000-03-22 | 2002-09-23 | Gate driver multi-chip module |
Country Status (6)
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| JP (1) | JP3943395B2 (en) |
| CN (1) | CN1284421C (en) |
| AU (1) | AU2001247631A1 (en) |
| TW (1) | TWI250406B (en) |
| WO (1) | WO2001072092A1 (en) |
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Also Published As
| Publication number | Publication date |
|---|---|
| WO2001072092A1 (en) | 2001-09-27 |
| JP3943395B2 (en) | 2007-07-11 |
| JP2003528449A (en) | 2003-09-24 |
| US6879491B2 (en) | 2005-04-12 |
| AU2001247631A1 (en) | 2001-10-03 |
| US20030016505A1 (en) | 2003-01-23 |
| TWI250406B (en) | 2006-03-01 |
| CN1419798A (en) | 2003-05-21 |
| US20020021560A1 (en) | 2002-02-21 |
| CN1284421C (en) | 2006-11-08 |
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