USRE41625E1 - Semiconductor device and method of fabricating the same - Google Patents

Abstract

A protective insulating film is deposited over first and second field-effect transistors formed on a semiconductor substrate. A capacitor composed of a capacitor lower electrode, a capacitor insulating film composed of an insulating metal oxide film, and a capacitor upper electrode is formed on the protective insulating film. A first contact plug formed in the protective insulating film provides a direct connection between the capacitor lower electrode and an impurity diffusion layer of the first field-effect transistor. A second contact plug formed in the protective insulating film provides a direct connection between the capacitor upper electrode and an impurity diffusion layer of the second field-effect transistor.

Description

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor device comprising a capacitor having a capacitor insulating film composed of an insulating metal oxide film such as a ferroelectric film or a high-dielectric-constant film and to a method of fabricating the same.

With the advancement of digital technology in recent years, there have been increasing tendencies to process or store a larger amount of data. Under such circumstances, electronic equipment has been more sophisticated than ever, which has rapidly increased the integration density of a semiconductor integrated circuit used in the electronic equipment and promoted the miniaturization a semiconductor element used therein.

To increase the integration density of a dynamic RAM composing the semiconductor integrated circuit, research and development has been conducted widely on a technique using a ferroelectric film or a high-dielectric-constant film as a capacitor insulating film in place of a silicon oxide film or a silicon nitride film that has been used conventionally.

To implement an actually usable nonvolatile RAM which operates at a low voltage and permits a high-speed write or read operation performed thereto, vigorous research and development has been conducted on a ferroelectric film having the property of spontaneous polarization.

The most significant challenge to the implementation of a semiconductor device comprising a capacitor having a capacitor insulating film made of an insulating metal oxide such as a ferroelectric film or a high-dielectric-constant film is the development of a process which allows the integration of the capacitor into a CMOS integrated circuit without degrading the properties of the capacitor. In particular, the most important point is to prevent the degradation of the properties of the capacitor due to the reduction of an insulating metal oxide composing the capacitor insulating film by hydrogen.

Referring now toFIG. 8, a conventional semiconductor device comprising a capacitor insulating film made of an insulating metal oxide and a fabrication method therefor will be described.

As shown inFIG. 8, adevice isolation region11 is formed in a surface portion of asemiconductor substrate10, followed by agate electrode13 formed on thesemiconductor substrate10 with agate insulating film12 interposed therebetween. Then, impurity ions at a low concentration are implanted by using thegate electrode13 as a mask. Subsequently, impurity ions at a high concentration are implanted by using thegate electrode13 and the gate protectiveinsulating film14 as a mask, wherebyimpurity diffusion layers15 each having an LDD structure and serving as a source or drain region of the field-effect transistor is formed.

Next, a first protectiveinsulating film16 is deposited over the entire surface of thesemiconductor substrate10. Then, a first contact hole is formed in the first protectiveinsulating film16 and a conductive film is filled in the first contact hole, whereby afirst contact plug17 connected to one of theimpurity diffusion layers15 which serves as the source or drain region of the first field-effect transistor forming a memory cell is formed.

Next, a capacitorlower electrode18 composed of a multilayer film consisting of a titanium film, a titanium nitride film, an iridium oxide film, and a platinum film and connected to thefirst contact plug17 and acapacitor insulating film19 composed of an insulating metal oxide are formed on the first protectiveinsulating film16. Thereafter, aninsulating film20 is formed on the first protectiveinsulating film16 to be located between the capacitorlower electrode18 and the capacitorinsulating film19.

Next, a capacitorupper electrode21 composed of a multilayer film consisting of a platinum film and a titanium film is formed over the plurality of .capacitor insulating films19 and theinsulating film20 to have a peripheral portion extending over the first protectiveinsulating film16. The foregoing capacitorlower electrode18, thecapacitor insulating film19, and the capacitorupper electrode21 constitute a capacitor for storing data. The capacitor and the first field-effect transistor constitute a memory cell. A plurality of memory cells constitute a memory cell array.

Next, ahydrogen barrier film22 composed of a silicon nitride film or a boron nitride film is formed to cover the capacitorupper electrode21. Then, a second protectiveinsulating film23 is deposited entirely over thehydrogen barrier film22 and the first protectiveinsulating film16. Thehydrogen barrier layer22 has the function of preventing a hydrogen atom from being diffused in the capacitorupper electrode21, reaching thecapacitor insulating film19, and reducing the insulating metal oxide composing thecapacitor insulating film19.

Next, a second contact hole27 (see FIG.9(a)) is formed in the second protectiveinsulating film23 and then a third contact hole28 (see FIG.9(b)) is formed in the first and second protectiveinsulating films16 and23. Subsequently, a conductive film is deposited on the second protectiveinsulating film23 such that the second andthird contact holes27 and28 are filled therewith and then patterned, thereby forming asecond contact plug24 connected to the capacitorupper electrode21, athird contact plug25 connected to theimpurity diffusion layer15 of the second field-effect transistor forming a sense amp, and awiring layer26 for providing a connection between the second andthird contact plugs24 and25.

In a semiconductor memory comprising a capacitor for storing data which has thecapacitor insulating film19 made of an insulating metal oxide, a voltage is applied to the capacitorlower electrode18 for every one bit so that the capacitorlower electrode18 is connected to theimpurity diffusion layer15 of the first field-effect transistor via thefirst contact plug17. On the other hand, since a voltage is applied to the capacitorupper electrode21 for every plural bits, the capacitorupper electrode21 is connected to theimpurity diffusion layer15 of the second field-effect transistor forming a sense amp via thesecond contact plug24, thewiring layer26, and thethird contact plug25.

In the process of inspecting the properties of the capacitor of the semiconductor device obtained by the method described above, the present inventors noticed that the insulating metal oxide composing thecapacitor insulating film19 was reduced irrespective of thehydrogen barrier film22 provided on the capacitorupper electrode21 with the view to preventing the reduction of the insulating metal oxide and the properties of the capacitor were degraded thereby.

As a result of making a wide variety of examinations on the cause of the reduction of the insulating metal oxide, the present inventors found that the insulating metal oxide was reduced in accordance with the following mechanism. A description will be given to the mechanism whereby the insulating metal oxide film is reduced irrespective of thehydrogen barrier film22 provided on the capacitorupper electrode21.

In the step of forming thesecond contact hole27 in the second protectiveinsulating film23 by using thefirst resist pattern29 and removing thefirst resist pattern29 by using an oxygen plasma, as shown in FIG.9(a), and in the step of forming thethird contact hole28 in the first and secondprotective insulating films16 and23 by using thesecond resist pattern30 and removing thesecond resist pattern30 by using an oxygen plasma, as shown in FIG.9(b), the capacitorupper electrode21 is exposed in thesecond contact hole27 via the opening formed in thehydrogen barrier film22, as shown in FIG.10(a). Although FIG.10(a) shows the state in which thesecond resist pattern30 is formed on the second protectiveinsulating film23, the capacitorupper electrode21 is also opposed to thefirst resist pattern29 via the opening formed in thehydrogen barrier film22 even if thesecond contact hole27 is formed in the second protectiveinsulating film23 by using thefirst resist pattern29.

As a result, most of OH groups generated in removing the first andsecond resist patterns29 and30 by using the oxygen plasma are evaporated but some of the generated OH groups are decomposed by the catalytic reaction of platinum present on a surface of the capacitorupper electrode21, so that active hydrogen is generated on the surface of the capacitorupper electrode21 as shown in FIG.10(b). Oxygen generated through the decomposition of the OH group is combined with carbon in the resist pattern to form CO, which is evaporated. The active hydrogen generated on the surface of the capacitorupper electrode21 is diffused in the capacitorupper electrode21 through the opening of thehydrogen barrier film22 of the capacitorupper electrode22 to reach thecapacitor insulating film19 and reduce the insulating metal oxide composing thecapacitor insulating film19, as shown in FIG.10(c), which degrades the properties of the capacitor.

If thewiring layer26 formed by patterning the conductive film deposited on the second protectiveinsulating film23 is subjected to an annealing process (sintering) performed in a hydrogen atmosphere, a hydrogen atom is diffused in thesecond contact plug24 and in the capacitorupper electrode21 to reach thecapacitor insulating film19 and reduce the insulating metal oxide composing thecapacitor insulating film19, as shown inFIG. 11, which also degrades the properties of the capacitor.

SUMMARY OF THE INVENTION

In view of the foregoing, it is therefore an object of the present invention to prevent the reduction of an insulating metal oxide composing a capacitor insulating film and thereby prevent the degradation of the properties of the capacitor.

To attain the object, a semiconductor device according to the present invention comprises: a protective insulating film deposited on a semiconductor substrate having first and second field-effect transistors formed thereon; a capacitor composed of a capacitor lower electrode, a capacitor insulating film made of an insulating metal oxide, and a capacitor upper electrode which are formed in upwardly stacked relationship on the protective insulating film; a first contact plug formed in the protective insulating film to provide a direct connection between an impurity diffusion layer serving as a source or drain region of the first field-effect transistor and the capacitor lower electrode; and a second contact plug formed in the protective insulating film to provide a direct connection between an impurity diffusion layer serving as a source or drain region of the second field-effect transistor and the capacitor upper electrode.

In the semiconductor device according to the present invention, the capacitor upper electrode of the capacitor is connected directly to the impurity diffusion layer of the second field-effect transistor by the second contact plug formed in the protective insulating film, not by the wiring layer formed on the protective insulating film deposited on the capacitor as in the conventional semiconductor device. This obviates the necessity to form a contact hole for providing a connection between the wiring layer formed on the protective insulating film on the capacitor and the capacitor upper electrode and hence the necessity for a resist pattern for forming the contact hole. As a result, there can be circumvented a situation in which hydrogen generated in removing the resist pattern by using an oxygen plasma reaches the capacitor insulating film. Since the capacitor upper electrode is covered with the protective insulating film on the capacitor during the formation of the contact hole for providing a connection between the wiring layer formed on the protective insulating film on the capacitor and the impurity diffusion layer of the second field-effect transistor, there can be circumvented a situation in which hydrogen generated in removing the resist pattern for forming the contact hole by using an oxygen plasma reaches the capacitor insulating film. Even if the wiring layer formed on the protective insulating film on the capacitor is treated with heat in a hydrogen atmosphere, hydrogen in the hydrogen atmosphere is prevented from reaching the capacitor insulating film since the wiring layer is not connected to the capacitor upper electrode. This prevents the reduction of the insulating metal oxide composing the capacitor insulating film and improves the properties of the capacitor.

In the semiconductor device according to the present invention, the capacitor insulating film is preferably formed conformally to the capacitor lower electrode, the semiconductor device preferably further comprising: insulating sidewalls formed on respective side surfaces of the capacitor lower electrode and the capacitor insulating film, wherein the capacitor upper electrode is preferably formed over the capacitor insulating film and the sidewalls.

In the arrangement, it is sufficient for the insulating metal oxide film serving as the capacitor insulating film to be formed excellently over an upper portion of the capacitor lower electrode having a flat configuration, so that the insulating metal oxide film is formed easily.

In this case, the sidewalls are preferably made of silicon oxide.

In the semiconductor device according to the present invention, the capacitor lower electrode preferably includes a plurality of capacitor lower electrodes formed on the protective insulating film, the semiconductor device preferably further comprising: an insulating film formed between the plurality of capacitor lower electrodes, wherein the capacitor insulating film is preferably formed over the plurality of capacitor lower electrodes and the insulating film.

In the arrangement, the insulating metal oxide film serving as the capacitor insulating film is formed over the plurality of capacitor lower electrodes and the insulating film having a flat configuration, so that the insulating metal oxide film is formed easily.

In this case, the insulating film is preferably composed of silicon oxide.

The semiconductor device according to the present invention preferably further comprises: a hydrogen barrier film entirely covering the capacitor upper electrode.

The arrangement positively prevents a situation in which a hydrogen atom is diffused in the capacitor upper electrode to reach the capacitor insulating film and reduce the insulating metal oxide film composing the capacitor insulating film.

In the semiconductor device according to the present invention, each of the first and second contact plugs is preferably made of polysilicon or tungsten.

In the semiconductor device according to the present invention, the capacitor insulating film is preferably made of a ferroelectric material having a bismuth layered perovskite structure, lead zirconate titanate (PZT), barium strontium titanate, or tantalum pentaoxide.

A method of fabricating a semiconductor device according to the present invention comprises the steps of: depositing a protective insulating film on a semiconductor substrate having first and second field-effect transistors formed thereon; forming a first contact plug and a second contact plug in the protective insulating film, the first contact plug being connected to an impurity diffusion layer serving as a source or drain region of the first field-effect transistor, the second contact plug being connected to an impurity diffusion layer serving as a source or drain region of the second field-effect transistor; forming, on the protective insulating film, a capacitor lower electrode connected directly to the first contact plug; forming, on the capacitor lower electrode, a capacitor insulating film made of an insulating metal oxide; and forming, on the capacitor insulating film, a capacitor upper electrode having a peripheral portion located on the protective insulating film and connected directly to the second contact plug.

In the method of fabricating a semiconductor device according to the present invention, the capacitor upper electrode of the capacitor is connected directly to the impurity diffusion layer of the second field-effect transistor by the second contact plug formed in the protective insulating film, not by the wiring layer formed on the protective insulating film deposited on the capacitor as in the conventional semiconductor device. This obviates the necessity to form a contact hole for providing a connection between the wiring layer formed on the protective insulating film on the capacitor and the capacitor upper electrode and therefore the necessity for a resist pattern for forming the contact hole. As a result, there can be circumvented a situation in which hydrogen generated in removing the resist pattern by using an oxygen plasma reaches the capacitor insulating film. Since the capacitor upper electrode is covered with the protective insulating film on the capacitor during the formation of the contact hole for providing a connection between the wiring layer formed on the protective insulating film on the capacitor and the impurity diffusion layer of the second field-effect transistor, there can be circumvented a situation in which hydrogen generated in removing the resist pattern for forming the contact hole by using an oxygen plasma reaches the capacitor insulating film. Even if the wiring layer formed on the protective insulating film on the capacitor is treated with heat in a hydrogen atmosphere, hydrogen in the hydrogen atmosphere is prevented from reaching the capacitor insulating film since the wiring layer is not connected to the capacitor upper electrode. This prevents the reduction of the insulating metal oxide composing the capacitor insulating film and improves the properties of the capacitor.

The method of fabricating a semiconductor device according to the present invention preferably further comprises the step of: forming a hydrogen barrier film covering the capacitor upper electrode.

The arrangement positively prevents a situation in which a hydrogen atom is diffused in the capacitor upper electrode to reach the capacitor insulating film and reduce the insulating metal oxide composing the capacitor insulating film.

In the method of fabricating a semiconductor device according to the present invention, the step of forming the capacitor insulating film preferably includes the step of forming a capacitor insulating film which is conformal to the capacitor lower electrode, the method preferably further comprising, between the step of forming the capacitor insulating film and the step of forming the capacitor upper electrode, the step of: forming insulating sidewalls on respective side surfaces of the capacitor lower electrode and the capacitor insulating film, wherein the step of forming the capacitor upper electrode preferably includes the step of forming the capacitor upper electrode over the capacitor insulating film and the sidewalls.

In the arrangement, it is sufficient for the insulating metal oxide film serving as the capacitor insulating film to be formed excellently over an upper portion of the capacitor lower electrode having a flat configuration, so that the insulating metal oxide film is formed easily.

In the method of fabricating a semiconductor device according to the present invention, the step of forming the capacitor lower electrode preferably includes the step of forming a plurality of capacitor lower electrodes on the protective insulating film, the method preferably further comprising, between the step of forming the capacitor lower electrode and the step of forming the capacitor insulating film, the step of: forming an insulating film between the plurality of capacitor lower electrodes, wherein the step of forming the capacitor insulating film preferably includes the step of forming the capacitor insulating film over the plurality of capacitor lower electrodes and the insulating film.

In the arrangement, the insulating metal oxide film serving as the capacitor insulating film is formed over the plurality of capacitor lower electrodes and the insulating film having a flat configuration, so that the insulating metal oxide film is formed easily.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention;

FIGS.2(a) and (b) are cross-sectional views illustrating a method of fabricating the semiconductor device according to the first embodiment;

FIGS.3(a) and (b) are cross-sectional views illustrating a method of fabricating the semiconductor device according to the first embodiment;

FIG. 4 is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention;

FIGS.5(a) and (b) are cross-sectional views illustrating a method of fabricating the semiconductor device according to the second embodiment;

FIG. 6 is a cross-sectional view of a semiconductor device according to a third embodiment of the present invention;

FIGS.7(a) and (b) are cross-sectional views illustrating a method of fabricating the semiconductor device according to the third embodiment;

FIG. 8 is a cross-sectional view of a conventional semiconductor device;

FIGS.9(a) and (b) are cross-sectional views each illustrating a process step of a conventional method of fabricating a semiconductor device;

FIGS.10(a) to (c) are cross-sectional views illustrating problems associated with the conventional semiconductor device and the fabrication method therefor; and

FIG. 11 is a cross-sectional views illustrating problems associated with the conventional semiconductor device and the fabrication method therefor.

DETAILED DESCRIPTION OF THE INVENTIONEMBODIMENT 1

A semiconductor device according to a first embodiment of the present invention will be described with reference to FIG.1.

As shown inFIG. 1, adevice isolation region101 and impurity diffusion layers105 each serving as the source or drain region of a first field-effect transistor or the source or drain region of the second field-effect transistor are formed in a surface portion of asemiconductor substrate100. Agate electrode103 is formed on thesemiconductor substrate100 to be located between the pair of impurity diffusion layers105 with agate insulating film102 interposed therebetween. The top and side surfaces of thegate electrode103 are covered with a gate protectiveinsulating film104.

A first protective insulatingfilm106 is deposited over the gate protectiveinsulating film104 and thesemiconductor substrate100. In the first protective insulatingfilm106, there are formed first and second contact plugs107 and108 each composed of a tungsten or polysilicon film. Thefirst contact plug107 is connected to one of the impurity diffusion layers105 which serves as the source or drain region of the first field-effect transistor forming a memory cell and asecond contact plug108 is connected to one of the impurity diffusion layers105 which serves as the source or drain region of the second field-effect transistor forming a sense amp.

A plurality of capacitorlower electrodes109 each composed of a multilayer film consisting of a titanium film, a titanium nitride film, an iridium oxide film, and a platinum film and connected to thefirst contact plug107 are formed on the first protective insulatingfilm106. Acapacitor insulating film110A made of SrBi₂(Ta_1-xNb_x)O₉having a bismuth layered perovskite structure is formed over the plurality of capacitorlower electrodes109 to extend to the exterior thereof.

A capacitorupper electrode111 composed of a multilayer film consisting of a platinum film and a titanium film or a titanium nitride film and connected to thesecond contact plug108 is formed on thecapacitor insulating film110A. The capacitorupper electrode111 is covered with ahydrogen barrier film112 composed of a silicon nitride film or a boron nitride film.

The foregoing capacitorlower electrode109, thecapacitor insulating film110A, and the capacitorupper electrode111 constitute a capacitor for storing data. The capacitor and the first field-effect transistor constitute a memory cell. A plurality of memory cells constitute a memory array.

A second protective insulatingfilm113 is deposited on the first protective insulatingfilm106. Athird contact plug114 connected to the other of the impurity diffusion layers105 serving as the source or drain region of the second field-effect transistor is formed in the first and second protective insulatingfilms106 and113. Awiring layer115 connected to thethird contact plug114 is formed on the second protective insulatingfilm113. Each of thethird contact plug114 and thewiring layer115 is composed of a multilayer film consisting of a titanium film, a titanium nitride film, an aluminum film, and a titanium nitride film which are deposited in upwardly stacked relationship or a multilayer film consisting of a titanium film, a titanium nitride film, a tungsten film, a titanium film, a titanium nitride film, an aluminum film, and a titanium nitride film which are deposited in upwardly stacked relationship.

Referring to FIGS.2(a) and (b) and FIGS.3(a) and (b), a description will be given to a method of fabricating the semiconductor device according to the first embodiment.

First, as shown in FIG.2(a), thedevice isolation region101 is formed in the surface portion of thesemiconductor substrate100, followed by thegate electrode103 formed on thesemiconductor substrate100 with thegate insulating film102 interposed therebetween. Then, impurity ions at a low concentration are implanted by using thegate electrode103 as a mask and the gate protectiveoxide insulating film104 is formed on the top and side surfaces of thegate electrode103. Subsequently, impurity ions at a high concentration are implanted by using thegate electrode103 and the gate protectiveinsulating film104 as a mask, whereby the impurity diffusion layers105 each having an LDD structure and serving as the source or drain region of the first field-effect transistor or the source or drain region of the second field-effect transistor are formed.

Next, the first protective insulatingfilm106 is deposited over the entire surface of thesemiconductor substrate100 and a contact hole is formed by dry etching in the first protective insulatingfilm106. Then, a conductive film composed of a tungsten film or a polysilicon film is deposited by CVD over the entire surface of the first protective insulatingfilm106. Subsequently, the portion of the conductive film located over the first protective insulatingfilm106 is removed by an etch-back or CMP process, whereby thefirst contact plug107 connected to one of the impurity diffusion layers105 which serves as the source or drain region of the first field-effect transistor forming the memory cell is formed and thesecond contact plug108 connected to one of the impurity diffusion layers105 which serves as the source or drain region of the second field-effect transistor disposed in the peripheral portion of the memory cell array to form a sense amp is formed.

Next, the multilayer film consisting of the titanium film, the titanium nitride film, the iridium oxide film, and the platinum film which are deposited in upwardly stacked relationship is formed over the entire surface of the first protective insulatingfilm106 and then patterned by dry etching, thereby forming the capacitorlower electrode109 connected to thefirst contact plug107, as shown in FIG.2(b).

Next, a ferroelectric film made of SrBi₂(Ta_1-xNb_x)O₉having a bismuth layered perovskite structure and having a thickness of about 100 nm to 200 nm is deposited entirely over the capacitorlower electrodes109 and the first protective insulatingfilm106 by metal organic decomposition (MOD), metal organic chemical vapor deposition (MOCVD), or sputtering and then patterned, thereby forming thecapacitor insulating film110A extending over the plurality of capacitorlower electrodes109 to the exterior thereof.

Next, a multilayer film consisting of a platinum film and a titanium film which are deposited in upwardly stacked relationship or a multilayer film consisting of a platinum film and a titanium nitride film which are deposited in upwardly stacked relationship is formed entirely over the capacitor insulating film1010A and the firstprotective film106 and then patterned by dry etching, thereby forming the capacitorupper electrode111 connected to thesecond contact plug108, as shown in FIG.3(a).

Next, a silicon nitride film or a boron nitride film is deposited entirely over the capacitorupper electrode111 and the first protective insulatingfilm106 by CVD or sputtering and then patterned by dry etching, thereby forming thehydrogen barrier film112 covering the capacitor.

Next, as shown in FIG.3(b), the second protective insulatingfilm113 is deposited entirely over thehydrogen barrier film112 and the first protective insulatingfilm106. Then, a contact hole is formed in the second protective insulatingfilm113 and in the first protective insulatingfilm106. Thereafter, a multilayer film consisting of a titanium film, a titanium nitride film, an aluminum film, and a titanium nitride film which are deposited in upwardly stacked relationship or a multilayer film consisting of a titanium film, a titanium nitride film, a tungsten film, a titanium film, a titanium nitride film, an aluminum film, and a titanium nitride film which are deposited in upwardly stacked relationship is formed over the entire surface of the second protective insulatingfilm113 and then patterned, thereby forming thethird contact plug114 connected to the other of the impurity diffusion layers105 which serves as the source or drain region of the second field-effect transistor and thewiring layer115 connected to thethird contact plug114.

In the semiconductor device according to the first embodiment and the fabrication method therefor, the capacitorupper electrode111 of the capacitor for storing data which forms the memory cell is connected directly to theimpurity diffusion layer105 of the second field-effect transistor by thesecond contact plug108 formed in the first protective insulatingfilm106. Unlike the conventional embodiment shown inFIG. 8, the capacitorupper electrode111 is not connected to theimpurity diffusion layer105 via thesecond contact plug24, thewiring layer26, and thethird contact plug25. Since an opening is not formed in thehydrogen barrier film112 covering the capacitorlower electrode111, there can be circumvented a situation in which active hydrogen generated by the catalytic reaction of platinum is diffused in the capacitorupper electrode111 to reach thecapacitor insulating film110A in the step of removing the resist pattern used to form the second orthird contact plug24 or25 by using an oxygen plasma and a situation in which a hydrogen atom is diffused in the capacitorupper electrode111 to reach thecapacitor insulating film110A in the step of performing an annealing process with respect to thewiring layer115 formed on the second protective insulating film.113 in a hydrogen atmosphere. Accordingly, the insulating metal oxide composing thecapacitor insulating film110A is not reduced by hydrogen and the properties of the capacitor are improved.

EMBODIMENT 2

A semiconductor device according to a second embodiment of the present invention will be described with reference to FIG.4.

As shown inFIG. 4, adevice isolation region101 and impurity diffusion layers105 each serving as the source or drain region of a first field-effect transistor or as the source or drain region of a second field-effect transistor are formed in a surface portion of asemiconductor substrate100, similarly to the first embodiment. Agate electrode103 is formed on thesemiconductor substrate100 to be located between the pair of impurity diffusion layers105. The top and side surfaces of thegate electrode103 are covered with the gate protectiveinsulating film104.

Similarly to the first embodiment, a first protective insulatingfilm106 is deposited over thesemiconductor substrate100 and the gate protectiveinsulating film104. In the first protective insulatingfilm106, there are formed afirst contact plug107 and asecond contact plug108 each composed of a tungsten or polysilicon film. Thefirst contact plug107 is connected to one of the impurity diffusion layers105 which serves as the source or drain region of the first field-effect transistor forming a memory cell. Thesecond contact plug108 is connected to one of the impurity diffusion layers105 which serves as the source or drain region of the second field-effect transistor disposed in a peripheral portion of the memory cell to serve as a sense amp.

A capacitorlower electrode109 composed of a multilayer film consisting of a titanium film, a titanium nitride film, an iridium oxide film, and a platinum film and connected to thefirst contact plug107 is formed on the first protective insulatingfilm106. Acapacitor insulating film110B made of SrBi₂(Ta_1-xNb_x)O₉having a bismuth layered perovskite structure and conformal to the capacitorlower electrode109 is formed on the capacitorlower electrode109. The capacitorlower electrode109 and thecapacitor insulating film110B have respective side surfaces covered withsidewalls116 composed of a silicon oxide film.

A capacitorupper electrode111 composed of a multilayer film consisting of a platinum film and a titanium film or a titanium nitride film is formed over the plurality of capacitorlower electrodes109 and thecapacitor insulating film110B to extend to the exterior thereof and connected to thesecond contact plug108. The capacitorupper electrode111 is covered with ahydrogen barrier film112 composed of a silicon nitride film or a boron nitride film.

The foregoing capacitorlower electrode109, thecapacitor insulating film110B, and the capacitorupper electrode111 constitute a capacitor for storing data. The capacitor and the first field-effect transistor constitute a memory cell. A plurality of memory cells constitute a memory array.

Similarly to the first embodiment, a second protective insulatingfilm113 is deposited on the first protective insulatingfilm106. Athird contact plug114 connected to the other of the impurity diffusion layers105 which serves as the source or drain region of the second field-effect transistor is formed in the first and second protective insulatingfilms106 and113. Awiring layer115 connected to thethird contact plug114 is formed on the second protective insulatingfilm113. Each of thethird contact plug114 and thewiring layer115 is composed of a multilayer film consisting of a titanium film, a titanium nitride film, an aluminum film, and a titanium nitride film which are deposited in upwardly stacked relationship or a multilayer film consisting of a titanium film, a titanium nitride film, a tungsten film, a titanium film, a titanium nitride film, an aluminum film, and a titanium nitride film which are deposited in upwardly stacked relationship.

Referring to FIGS.5(a) and (b), a description will be given to a method of fabricating a semiconductor device according to the second embodiment.

First, as shown in FIG.5(a), thedevice isolation region101 is formed in the surface portion of thesemiconductor substrate100, followed by thegate electrode103 formed on thesemiconductor substrate100 with thegate insulating film102 interposed therebetween and the gate protectiveinsulating film104 formed over thegate electrode103. Thereafter, the impurity diffusion layers105 each serving as the source or drain region of the first field-effect transistor or as the source or drain region of the second field-effect transistor and having an LDD structure are formed. Then, the first protective insulatingfilm106 is deposited over the entire surface of thesemiconductor substrate100. After that, thefirst contact plug107 connected to one of the impurity diffusion layers105 which serves as the source or drain region of the first field-effect transistor forming the memory cell is formed in the first protective insulating film, while thesecond contact plug108 connected to one of the impurity diffusion layers105 which serves as the source or drain region of the second field-effect transistor forming the sense amp is formed in the first protective insulatingfilm106.

Next, a multilayer film consisting of a titanium film, a titanium nitride film, an iridium oxide film, and a platinum film which are deposited in upwardly stacked relationship is formed by sputtering over the entire surface of the first protective insulatingfilm106. Then, a ferroelectric film made of SrBi₂(Ta_1-xNb_x)O₉having a bismuth layered perovskite structure and having a thickness of 100 nm to 200 nm is deposited on the multilayer film by metal organic decomposition, metal organic chemical vapor deposition, or sputtering. Thereafter, the multilayer film and the ferroelectric film are patterned by dry etching to form the capacitorlower electrode109 composed of the multilayer film and thecapacitor insulating film110B composed of the ferroelectric film.

Next, thesilicon oxide film108 having a thickness of 300 nm is deposited entirely over the capacitorlower electrode109 and thecapacitor insulating film110B and subjected to an isotropic etching, thereby forming thesidewalls116 on the respective side surfaces of the capacitorlower electrode109 and thecapacitor insulating film110B, as shown in FIG.5(b).

Next, a multilayer film consisting of a platinum film and a titanium film which are deposited in upwardly stacked relationship or a multilayer film consisting of a platinum film and a titanium nitride film which are deposited in upwardly stacked relationship is deposited over the capacitor insulating film and the firstprotective film106, similarly to the first embodiment. Thereafter, the multilayer film is patterned by dry etching, thereby forming the capacitor upper electrode111 (seeFIG. 4) connected to thesecond contact plug108 and then forming the hydrogen barrier film112 (seeFIG. 4) covering the capacitorupper electrode111.

Next, the second protective insulatingfilm113 is deposited over thehydrogen barrier film112 and the first protective insulatingfilm106. Thereafter, the third contact plug114 (seeFIG. 4) connected to the other of the impurity diffusion layers105 which serves as the source or drain region of the second field-effect transistor is formed in the first and second protective insulatingfilms106 and113, while the wiring layer115 (seeFIG. 4) connected to thethird contact plug114 is formed on the second protective insulatingfilm113.

In the semiconductor device according to the second embodiment and the fabrication method therefor, the capacitorupper electrode111 of the capacitor for storing data which forms the memory cell is connected directly to theimpurity diffusion layer105 of the second field-effect transistor by thesecond contact plug108 formed in the first protective insulatingfilm106. Since an opening is not formed in thehydrogen barrier film112 covering the capacitorlower electrode111, there can be circumvented a situation in which active hydrogen generated by the catalytic reaction of platinum and a hydrogen atom in a hydrogen atmosphere in which thewiring layer115 is annealed are diffused in the capacitorupper electrode111 to reach thecapacitor insulating film110A. Accordingly, thecapacitor insulating film110A is not reduced by hydrogen and the properties of the capacitor are improved.

In particular, the second embodiment has deposited the ferroelectric film serving as thecapacitor insulating film110B on the multilayer film serving as the capacitorlower electrode109, i.e., the second embodiment has deposited the ferroelectric film on the flat multilayer film. This allows easy formation of the ferroelectric film.

Moreover, since the multilayer film serving as the capacitorupper electrode111 is deposited after thesidewalls116 are formed on the respective side surfaces of the capacitorlower electrode109 and thecapacitor insulating film110B, there is no conduction between the capacitorlower electrodes109.

EMBODIMENT 3

As shown inFIG. 6, adevice isolation region101 and impurity diffusion layers105 each serving as the source or drain region of a first field-effect transistor or as the source or drain region of a second field-effect transistor are formed in a surface portion of asemiconductor substrate100, similarly to the first embodiment. Agate electrode103 is formed on thesemiconductor substrate100 to be located between the pair of impurity diffusion layers105. The top and side surfaces of thegate electrode103 are covered with the gate protectiveinsulating film104.

Similarly to the first embodiment, a first protective insulatingfilm106 is deposited over thesemiconductor substrate100 and the gate protectiveinsulating film104. In the first protective insulatingfilm106, there are formed afirst contact plug107 and asecond contact plug108 each composed of a tungsten or polysilicon film. Thefirst contact plug107 is connected to one of the impurity diffusion layers105 which serves as the source or drain region of the first field-effect transistor forming a memory cell. Thesecond contact plug108 is connected to one of the impurity diffusion layers105 which serves as the source or drain region of the second field-effect transistor disposed in a peripheral portion of the memory cell to serve as a sense amp.

A capacitorlower electrode109 composed of a multilayer film consisting of a titanium film, a titanium nitride film, an iridium oxide film, and a platinum film and connected to thefirst contact plug107 is formed on the first protective insulatingfilm106. An insulatingfilm117 composed of a silicon oxide film is formed on the first protective insulatingfilm106 to be located between the capacitorlower electrodes109.

A capacitor insulating film10C made of SrBi₂(Ta_1-xNb_x) O₉having a bismuth layered perovskite structure is formed over the plurality of capacitorlower electrodes109 and the insulatingfilm117 to extend to the exterior thereof.

A capacitorupper electrode111 composed of a multilayer film consisting of a platinum film and a titanium film or a titanium nitride film and connected to thesecond contact plug108 is formed on the capacitor insulating film10C to extend to the exterior thereof. The capacitorupper electrode111 is covered with ahydrogen barrier film112 composed of a silicon nitride film or a boron nitride film.

The foregoing capacitorlower electrode109, thecapacitor insulating film110C, and the capacitorupper electrode111 constitute a capacitor for storing data. The capacitor and the first field-effect transistor constitute a memory cell. A plurality of memory cells constitute a memory array.

Similarly to the first embodiment, a second protective insulatingfilm113 is deposited on the first protective insulatingfilm106. Athird contact plug114 connected to the other of the impurity diffusion layers105 which serves as the source or drain region of the second field-effect transistor is formed in the first and second protective insulatingfilms106 and113. Awiring layer115 connected to thethird contact plug114 is formed on the second protective insulatingfilm113. Each of thethird contact plug114 and thewiring layer115 is composed of a multilayer film consisting of a titanium film, a titanium nitride film, an aluminum film, and a titanium nitride film which are deposited in upwardly stacked relationship or a multilayer film consisting of a titanium film, a titanium nitride film, a tungsten film, a titanium film, a titanium nitride film, an aluminum film, and a titanium nitride film which are deposited in upwardly stacked relationship.

Referring to FIGS.7(a) and (b), a description will be given to a method of fabricating a semiconductor device according to the third embodiment.

First, as shown in FIG.7(a), thedevice isolation region101 is formed in the surface portion of thesemiconductor substrate100, followed by thegate electrode103 formed on thesemiconductor substrate100 with thegate insulating film102 interposed therebetween and the gate protectiveinsulating film104 formed over thegate electrode103. Thereafter, the impurity diffusion layers105 each serving as the source or drain region of the first field-effect transistor or as the source or drain region of the second field-effect transistor and having an LDD structure are formed. Then, the first protective insulatingfilm106 is deposited over the entire surface of thesemiconductor substrate100. After that, thefirst contact plug107 connected to one of the impurity diffusion layers105 which serves as the source or drain region of the first field-effect transistor forming the memory cell is formed in the first protective insulating film, while thesecond contact plug108 connected to one of the impurity diffusion layers105 which serves as the source or drain region of-the second field-effect transistor forming the sense amp is formed in the first protective insulatingfilm106.

Next, a multilayer film consisting of a titanium film, a titanium nitride film, an iridium oxide film, and a platinum film which are deposited in upwardly stacked relationship is formed by sputtering over the entire surface of the first protective insulatingfilm106. The multilayer film is then patterned by dry etching, thereby forming the capacitorlower electrode109.

Next, asilicon oxide film117A having a thickness of 300 nm is deposited over the entire surface of the capacitorlower electrode109. Subsequently, the portion of thesilicon oxide film117A overlying the capacitorlower electrode109 is removed by CMP, whereby the insulatingfilm117 composed of thesilicon oxide film117A is formed on the first protective insulatingfilm106 to be located between the capacitorlower electrodes109, as shown in FIG.7(b).

Next, a ferroelectric film made of SrBi₂(Ta_1-xNb_x)O₉having a bismuth layered perovskite structure and having a thickness of 100 nm to 200 nm is deposited over the plurality of capacitorlower electrodes109 and the insulatingfilm117 by metal organic decomposition, metal organic chemical vapor deposition, or sputtering. The ferroelectric film is then patterned by dry etching to form the capacitor insulating film10C extending over the plurality of capacitorlower electrodes109 to the exterior thereof.

Next, a multilayer film consisting of a platinum film and a titanium film which are deposited in upwardly stacked relationship or a multilayer film consisting of a platinum film and a titanium nitride film which are deposited in upwardly stacked relationship is deposited over the capacitor insulating film and the firstprotective film106, similarly to the first embodiment. Thereafter, the multilayer film is patterned by dry etching, thereby forming the capacitor upper electrode111 (seeFIG. 6) connected to thesecond contact plug108 and then forming the hydrogen barrier film112 (seeFIG. 6) covering the capacitorupper electrode111.

Next, the second protective insulatingfilm113 is deposited over thehydrogen barrier film112 and the first protective insulatingfilm106. Thereafter, the third contact plug114 (seeFIG. 6) connected to the other of the impurity diffusion layers105 which serves as the source or drain region of the second field-effect transistor is formed in the first and second protective insulatingfilms106 and113, while the wiring layer115 (seeFIG. 6) connected to thethird contact plug114 is formed on the second protective insulatingfilm113.

In the semiconductor device according to the third embodiment and the fabrication method therefor, the capacitorupper electrode111 of the capacitor for storing data which forms the memory cell is connected directly to theimpurity diffusion layer105 of the second field-effect transistor by thesecond contact plug108 formed in the first protective insulatingfilm106. Since an opening is not formed in thehydrogen barrier film112 covering the capacitorlower electrode111, there can be circumvented a situation in which active hydrogen generated by the catalytic reaction of platinum and a hydrogen atom in a hydrogen atmosphere in which thewiring layer115 is annealed are diffused in the capacitorupper electrode111 to reach thecapacitor insulating film110A. Accordingly, thecapacitor insulating film110A is not reduced by hydrogen and the properties of the capacitor are improved.

In particular, the third embodiment has deposited the ferroelectric film serving as thecapacitor insulating film110C over the plurality of capacitorlower electrodes109 and the insulatingfilm117 having their surfaces planarized. This allows easy formation of the ferroelectric film.

Although thecapacitor insulating films110A,110B, and110C according to the first to third embodiments have been formed of SrBi₂(T_1-xNb_x)O₉, each of thecapacitor insulating films110A,110B, and110C may also be formed of a ferroelectric film having a bismuth layered perovskite structure having another composition or of a high-dielectric-constant film such as lead zirconate titanate, barium strontium titanate, or tantalum pentaoxide.

Although the capacitorupper electrode111 according to each of the first to third embodiments has been formed of the multilayer film consisting of the platinum film and the titanium film which are deposited in upwardly stacked relationship or of the multilayer film consisting of the platinum film and the titanium nitride film which are deposited in upwardly stacked relationship, it is not limited thereto. The capacitorupper electrode111 may be formed appropriately so long as it contains a platinum film, an iridium film, a ruthenium film, a rhodium film, or a multilayer film consisting of some of the films listed above.

Although the capacitorlower electrode109 according to each of the first to third embodiments has been formed of the multilayer film consisting of the titanium film, the titanium nitride film, the iridium oxide film, and the platinum film which are deposited in upwardly stacked relationship, it is not limited thereto. The capacitorlower electrode109 may be formed appropriately so long as it contains a platinum film, an iridium film, a ruthenium film, a rhodium film, or a multilayer film consisting of some of the films listed above.

Claims (8)

1. A semiconductor device comprising:

a protective insulating film deposited on a semiconductor substrate having first and second field-effect transistors formed thereon;

a capacitor composed of a capacitor lower electrode, a capacitor insulating film made of an insulating metal oxide, and a capacitor upper electrode which are formed in upwardly stacked relationship on the protective insulating film;

wherein an edge portion of the capacitor upper electrode is formed onto the protective insulating film;

a first contact plug formed in the protective insulating film to provide a direct connection between an impurity diffusion layer serving as a source or drain region of the first field-effect transistor and the capacitor lower electrode;

a second contact plug formed in the protective insulating film to provide a direct connection between an impurity diffusion layer serving as a source or drain region of the second field-effect transistor and the edge portion of the capacitor upper electrode; and

a hydrogen barrier film entirely covering the capacitor upper electrode.

2. The semiconductor device ofclaim 1, wherein the capacitor insulating film is formed conformally to the capacitor lower electrode, the semiconductor device further comprising:

insulating sidewalls formed on respective side surfaces of the capacitor lower electrode and the capacitor insulating film, wherein

the capacitor upper electrode is formed over the capacitor insulting film and the sidewalls.

3. The semiconductor device ofclaim 2, wherein the sidewalls are made of silicon oxide.

4. The semiconductor device ofclaim 1, wherein the capacitor lower electrode includes a plurality of capacitor lower electrodes formed on the protective insulating film, the semiconductor device further comprising:

an insulating film formed between the plurality of capacitor lower electrodes, wherein

the capacitor insulating film is formed over the plurality of capacitor lower electrodes and the insulating film.

5. The semiconductor device ofclaim 4, wherein the insulating film is composed of silicon oxide.

6. The semiconductor device ofclaim 1, wherein each of the first and second contact plugs is made of polysilicon or tungsten.

7. The semiconductor device ofclaim 1, wherein the capacitor insulating film is made of a ferroelectric material having a bismuth layered perovskite structure, lead zirconate titanate, barium strontium titanate, or tantalum pentaoxide.

8. The semiconductor device ofclaim 1,

wherein the first contact plug includes materials different from materials composing the capacitor lower electrode, and

the second contact plug includes materials different from materials composing the capacitor upper electrode.

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