USRE40916E1 - Liquid crystal driver and liquid crystal display device using the same - Google Patents

Abstract

A liquid crystal driver includes a voltage generator for generating gray scale voltages on the basis of reference voltages, and an output device for selecting one gray scale voltage from the generated gray scale voltages in accordance with display data, for applying inversion/non-inversion control to the selected gray scale voltage with respect to an inversion reference voltage on the basis of the selected gray scale voltage, an AC switching signal and the inversion reference voltage, and for outputting different liquid crystal supply voltages for one and the same display data to a liquid crystal panel.

Description

CROSS-REFERENCE TO RELATED APPLICATION

Notice: More than one reissue application has been filed for the reissue of U.S. Pat. No.5,774,106. This reissue applications are application Ser. Nos.09/324,168, now U.S. Pat. No. RE39,366;11/406,488;11/980,700 (the present application); and11/980,691; all of which are reissues of U.S. Pat. No.5,774,106.

This application is related to application Ser. No. 08/135,357 filed on Oct. 19, 1993, entitled “Liquid Crystal Display Driving Method/Driving Circuit Capable of Being Driven with Equal Voltages” which is assigned to the same assignee as the present application. The contents of application Ser. No. 08/135,537 are incorporated herein by reference.This application is a continuation reissue application of continuation reissue U.S. application Ser. No.11/406,488, filed Apr.19,2006, which is a continuation reissue application of U.S. reissue application Ser. No.09/324,168, filed Jun.2,1999, now U.S. Pat. No. RE39,366 issued Oct.31,2006, which is a reissue application of U.S. Pat. No.5,774,106, issued Jun.30,1998, the subject matter of which is incorporated by reference herein. This application is related to continuation reissue U.S. application Ser. No.11/980,691, filed Oct.31,2007, which is a continuation reissue of continuation reissue U.S. application Ser. No.11/406,488, filed Apr.19,2006.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a liquid crystal driver and a liquid crystal display device using the same and, particularly, relates to an active matrix type liquid crystal driver and a liquid crystal display device using the same.

2. Description of the Related Art

A conventional liquid crystal driver using a data driver LSI HD66310 described in Hitachi LCD driver LSI databook (Published by Hitachi Ltd., March 1994, pp. 1166-1185) will be explained below.

FIG. 2 is a configuration diagram of the conventional data driver HD66310.

InFIG. 2, thereference numeral201 designates a data driver;202, display data transferred from a system thereto;203, a group of control signals for controlling the data driver;204, a timing control circuit;205, a control signal for controlling the timing of latching thedisplay data202;206, display data;207, a display timing signal;208, a latch address control circuit;209, a group of latch signals generated by the latchaddress control circuit208;210, a latch circuit for latching thedisplay data206 successively;211, display data latched by thelatch circuit210 simultaneously;212, a latch circuit for latching thedisplay data211 simultaneously on the basis of thetiming signal207;213, display data latched by thelatch circuit212;214, a level shifter for shifting a logic voltage level to a liquid crystal driving voltage level;215, display data of voltage level shifted by thelevel shifter214;216, a reference voltage for a liquid crystal driving voltage;217, a liquid crystal driving circuit for generating a liquid crystal driving voltage on the basis of thereference voltage216; and218, a group of liquid crystal driving signals for driving a liquid crystal panel.

InFIG. 2, twelve bits ofdisplay data202, which are for four pixels (3 bits for gray scales×4 pixels), are transferred together from the system, so that display data corresponding to 160 pixels (4 pixels×40 times) are latched successively by thelatch circuit210 on the basis of thelatch signal209 generated by the latchaddress control circuit208. The thus latcheddisplay data211 corresponding to 160 pixels are further latched simultaneously by thelatch circuit212 on the basis of thetiming signal207 synchronized with a gate selection signal of a scanning driver. The voltage levels of thedisplay data213 are shifted to liquid crystal driving voltage levels by thelevel shifter214, so that thelevel shifter214 outputs displaydata215. The liquidcrystal driving circuit217 selects voltage levels corresponding to thedisplay data215 from eight levels V7 to V0 of thereference voltage216 and outputs the selected voltage levels as a group of liquidcrystal driving signals218. In this manner, display of eight gray scales corresponding to display data can be achieved by driving a liquid crystal panel on the basis of eight voltage levels.

FIG. 3 shows the relation between liquid crystal driving voltage and display brightness. In liquid crystal, display brightness varies correspondingly to a voltage applied to a common electrode. Therefore, display of eight gray scales is achieved by applying eight voltage levels V7 to V0 to the liquid crystal. Further, when voltages which are equal but different in polarity (positive polarity and negative polarity) are applied to the common electrode, the brightness does not change. Generally, in order to prevent the liquid crystal panel from burning, the voltage to be applied thereto is driven to alternate between positive polarity and negative polarity periodically.

FIG. 4 is a configuration diagram of a liquid crystal display device having data drivers in opposite sides of a liquid crystal panel. InFIG. 4, thereference numeral401 designates an power supply circuit for generating reference voltages for driving liquid crystal;402, an AC switching signal expressing AC switching timing;403 and404, reference voltages obtained by AC switching in different timing;405, a scanning driver LSI (hereinafter referred to as “scanning driver”) for driving gate lines of aliquid crystal panel411;406, the gate lines of theliquid crystal panel411 driven by thescanning driver405;407, a data driver for driving data lines arranged in the upper side of theliquid crystal panel411;408, the data lines driven by thedata driver407;409, a data driver for driving data lines arranged in the lower side of theliquid crystal panel411;410, the data lines driven by thedata driver409; and411, the liquid crystal panel.

FIG. 5 shows the timing of an AC switching signal which serves as a reference voltage signal for AC switching outputs in the case where data drivers are arranged in the upper and lower sides of the liquid crystal panel as shown in FIG.4. Thepower supply circuit401 generates an upper data driverreference AC voltage403 and a lower data driverreference AC voltage404 in synchronism with theAC switching signal402. The upper data driverreference AC voltage403 and the lower data driverreference AC voltage404 are reversed to each other in the timing of polarity (positive polarity and negative polarity). Thescanning driver405 selectsgate lines406 one line by one line successively and pixels on selected one of the gate lines are driven one pixel by one pixel alternatively by the upper andlower data drivers407 and409. Accordingly, liquid crystal cells on the gate lines successively driven by thescanning driver405 can be driven so that liquid crystal cells on each of the gate lines alternate their polarity between positive one and negative one). As a result, the quality of an image on the display is improved.

FIG. 6 is a configuration diagram of a liquid crystal display device having a data driver in one side of a liquid crystal panel. InFIG. 6, thereference numeral601 designates an power supply circuit for generating a reference voltage for driving liquid crystal;602, an AC switching signal expressing AC switching timing;603, a reference AC voltage obtained by AC switching;604, a scanning driver for driving gate lines of aliquid crystal panel608;605, the gate lines of theliquid crystal panel608 driven by thescanning driver604;606, a data driver for driving data lines arranged in the upper side of theliquid crystal panel608;607, the data lines driven by thedata driver606; and608, the liquid crystal panel.

FIG. 7 shows the timing of an AC switching signal which serves as a reference voltage signal for AC switching an output in the case where a data driver is arranged singly in the upper side of the liquid crystal panel as shown in FIG.6. Thepower supply circuit601 generates areference AC voltage603 in synchronism with theAC switching signal602. Thescanning driver604 selectsgate lines605 one by one successively so that selected one of the gate lines is driven by theupper data driver602. Accordingly, liquid crystal cells on the gate lines successively driven by thescanning driver604 are driven so that liquid crystal cells on one and the same gate line have the same (positive or negative) polarity. As a result, the quality of an image on the display is deteriorated.

FIG. 8 is a view showing another voltage applying method adapted to the case where the data driver shown inFIG. 6 is used. AlthoughFIG. 7 has shown the case where thereference voltage603 is supplied as an AC voltage,FIG. 8 shows the case where burning of the liquid crystal panel is prevented by changing both the electric potential Vcom of the common electrode (common electrode drive) and thereference voltage603. Also in this method, all liquid crystal cells on one and the same gate line have the same (positive or negative) polarity, so that the quality of an image on the display is deteriorated.

Alternate-column inversion drive of the liquid crystal panel has an advantage in that display quality is improved with compared with the case of no use of alternate-column inversion drive, because voltages applied to liquid crystal cells are inverted on alternate columns so that the current flowing in the common electrode at the time of liquid crystal drive becomes smaller. As for the conventional data driver arrangement, therefore, data drivers are arranged in the upper and lower portions of the liquid crystal panel. On the other hand, the liquid crystal display device is on strong demands not only for high quality display but also for small size and light weight. Arrangement of one data driver in a single side makes it easy to reduce size and weight. The arrangement of one data driver in a single side of the liquid crystal panel, however, has a problem that display quality deteriorates compared with the case of alternate-column inversion drive of the liquid crystal panel.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a liquid crystal driver for performing alternate-column inversion drive in which liquid crystal cells are driven so as to be inverted on alternate columns in order to obtain high image quality while one data driver is arranged in a single side of a liquid crystal panel in order to reduce the size and weight of a liquid crystal display, that is, in order to reduce a liquid crystal panel driving circuit for the purpose of high-density mounting, and to provide a liquid crystal display device using the liquid crystal driver.

To achieve the foregoing object, according to an aspect of the present invention, a voltage generating means for generating a plurality of gray scale voltages on the basis of reference voltages and an output means for selecting one gray scale voltage from the generated gray scale voltages correspondingly to display data and for outputting different-polarity liquid crystal supply voltages for one and the same display data in the liquid crystal panel on the basis of the selected gray scale voltage, an AC switching signal and an inversion AC switching signal are provided in a liquid crystal driver.

According to another aspect of the present invention, a level-shift circuit for shifting the level of a digital input signal is provided in a scanning driver so that the level of the digital input signal is shifted by the level-shift circuit to a signal level allowed operate in the inside of the scanning driver.

Alternate-column inversion drive can be achieved by one data driver as long as the aforementioned voltage generating means and the aforementioned output means are used.

Accordingly, the circuit scale of an electric source circuit for generating reference voltages can be reduced.

In addition, because the level-shift circuit provided in the input side of the scanning driver can shift the level of the digital input signal to a signal level allowed to operate in the inside of the scanning driver, the circuit scale of the liquid crystal display can be reduced without necessity of use of any external level-shift circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a configuration diagram of a liquid crystal display device as a first embodiment of the present invention;

FIG. 2 is a configuration diagram of a conventional liquid crystal driver;

FIG. 3 is a graph showing voltage-brightness characteristic of liquid crystal;

FIG. 4 is a configuration diagram of a conventional liquid crystal display device;

FIG. 5 is a timing chart of liquid crystal reference voltage in the prior art;

FIG. 6 is a configuration diagram of a conventional liquid crystal display device;

FIG. 7 is a timing chart of liquid crystal reference voltage in the prior art;

FIG. 8 is a timing chart of liquid crystal output voltage due to common electrode AC drive;

FIG. 9 is a block diagram of a liquid crystal driving circuit in the first embodiment;

FIG. 10 is a configuration diagram of a gray scale voltage generating circuit in the first embodiment;

FIG. 11 is a configuration diagram of an output circuit in the first embodiment;

FIG. 12 is a configuration diagram of an output buffer circuit in the first embodiment;

FIG. 13 is a timing chart of liquid crystal AC output voltages in the first embodiment;

FIG. 14 is a view showing process voltages in the first embodiment;

FIG. 15 is a view showing alternate-column inversion drive in the first embodiment;

FIG. 16 is a view showing alternate-dot inversion drive in the first embodiment;

FIG. 17 is a view showing the levels of driver voltages in the first embodiment;

FIG. 18 is a view showing the levels of driver voltages in the first embodiment;

FIG. 19 is a configuration diagram of the level-shift circuit in the first embodiment;

FIG. 20 is a configuration diagram of the level-shift circuit in the first embodiment;

FIG. 21 is a block diagram of a liquid crystal driver according to a second embodiment of the present invention;

FIG. 22 is a block diagram of the gray scale voltage generating circuit in the second embodiment;

FIG. 23 is a block diagram of the output circuit in the second embodiment;

FIG. 24 is a block diagram of a liquid crystal display device according to a third embodiment of the present invention;

FIG. 25 is a block diagram of the liquid crystal driver circuit in the third embodiment;

FIG. 26 is a configuration diagram of the voltage generating circuit in the third embodiment;

FIG. 27 is a timing chart showing the generation of liquid crystal reference voltages in the third embodiment;

FIG. 28 is a configuration diagram of a liquid crystal display device according to a fourth embodiment of the present invention;

FIG. 29 is a configuration diagram of the voltage generating circuit in the fourth embodiment;

FIG. 30 is a timing chart showing the generation of liquid crystal reference voltages in the fourth embodiment;

FIG. 31 is a configuration diagram of a voltage generating circuit according to a fifth embodiment of the present invention;

FIG. 32 is a timing chart showing the generation of liquid crystal reference voltages in the fifth embodiment;

FIG. 33 is a configuration diagram of a liquid crystal display device according to a sixth embodiment of the present invention;

FIG. 34 is a block diagram of a liquid crystal driver circuit in the sixth embodiment;

FIG. 35 is a configuration diagram of the voltage generating circuit in the sixth embodiment;

FIG. 36 is a timing chart showing the generation of liquid crystal reference voltages in the sixth embodiment;

FIG. 37 is a timing chart showing liquid crystal AC output voltages according to a seventh embodiment of the present invention; and

FIG. 38 is a block diagram of the output circuit in the seventh embodiment.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 is a block diagram of a liquid crystal display device according to the present invention. InFIG. 1, thereference numeral101 designates display data transferred from a system;102, a group of control signals;103, an power supply circuit;104, a group of reference voltage signals of 9 voltage levels to be applied to liquid crystal;105, an inversion reference voltage for AC inverting a voltage to be applied to liquid crystal;106, an AC switching signal expressing the timing of AC switching;107, a selection signal for controlling inversion outputs for each column; and108, a control signal for performing output circuit driving control. The reference numerals109-1 to109-8 designate data drivers for 240 outputs;110, a timing control circuit;111, a group of timing signals,112, display data;113, a display timing signal expressing display timing;114, a buffer circuit which receives and buffers the group of reference voltage signals104 and theinversion reference voltage105; and115 and119, a reference voltage and an inversion reference voltage, respectively, outputted from thebuffer circuit114.

Thereference numeral116 designates an EOR circuit for performing control as to whether theAC switching signal106 is to be inverted or not to be inverted on the basis of theselection signal107;117, an AC switching signal outputted from theEOR circuit116;118, a level shifter circuit for converting the level of thecontrol signal108 into a signal level for a high rate withstand voltage process;120, a signal outputted from thelevel shifter circuit118 by shifting the level of theAC switching signal106;121, a signal outputted from thelevel shifter circuit118 by shifting the level of theAC switching signal117; and122, a signal outputted from thelevel shifter circuit118 by shifting the level of thecontrol signal108. Thereference numeral123 designates a latch address control circuit;124, a group of latch signals generated by the latchaddress control circuit123;125, a latch circuit for latching thedisplay data112 successively;126, display data latched by thelatch circuit125;127, a latch circuit for latching thedisplay data126 simultaneously in synchronism with thedisplay timing signal113; and128, display data latched by thelatch circuit127.

Thereference numeral129 designates a gray scale voltage generating circuit for generating 64 levels of gray scale voltages from 9 levels ofreference voltages115 and outputting one level of gray scale voltages corresponding to display data;130, the gray scale voltages generated by the gray scalevoltage generating circuit129; and131, an output circuit for outputting voltages obtained by inverting or non-inverting thegray scale voltages130 on the basis of theinversion reference voltage119 correspondingly to the AC switching signals120 and121. Output currents of theoutput circuit131 are controlled by thecontrol signal122. Thereference numeral132 designates liquid crystal driving voltages. Thereference numeral133 designates a scanning circuit;134, gate driving signals successively selected by thescanning circuit133; and135, a liquid crystal panel of 640 dots×480 lines.

InFIG. 1, eight data drivers are required because the number of outputs from each of the data drivers109-1 to109-8 is 240 and because the resolution of theliquid crystal panel135 is 640×RGB×480 pixels. Thetiming control circuit110 generates control signals inside each data driver on the basis of 18 bits of display data101 (3 pixels×6 bits for gray scales) and a group of control signals, such as a horizontal synchronizing signal, a display data transfer clock signal, etc., transferred from a system and performs timing control. In thetiming control circuit110, thedisplay data101 are controlled by the timing inside the data driver so as to be transferred asdisplay data112 to thelatch circuit125. The latchaddress control circuit123 generates alatch signal124 synchronized with thedisplay data112 from thecontrol signal group111 outputted from thetiming control circuit110 on the basis of the timing inside the data driver, so that thedisplay data112 are latched by thelatch circuit125 successively.

Each of thelatch circuits125 has 240 outputs (6 bits per one output) so that display data corresponding to one horizontal line can be latched successively in the data drivers109-1 to109-8. Thedisplay data126 thus latched by thelatch circuits125 correspondingly to one horizontal line are further latched simultaneously by thelatch circuits127 on the basis of thedisplay timing signal113 synchronized with thegate selection signal134 outputted from thescanning circuit133. Each of thelatch circuits127 has 240 outputs (6 bits per one output) so that display data corresponding to one horizontal line can be latched simultaneously in the data drivers109-1 to109-8. Thedisplay data128 thus latched by thelatch circuits127 are transferred to the gray scalevoltage generating circuits129. Theelectric source circuit103 generates 9-level reference signals104 for generating gray scale voltages and aninversion reference voltage105 for AC switching. Each of thebuffer circuits114 buffers thereference voltages104 and theinversion reference voltage105 supplied from thepower supply circuit103 and supplies these voltages asreference voltage115 andinversion reference voltage119 to the gray scalevoltage generating circuits129 and the output circuit.

The gray scalevoltage generating circuit129 generates 64 levels of gray scale voltages from thereference voltages115, selects one level of gray scale voltages corresponding to display data for each output and sends the selected voltage level to theoutput circuit131. TheAC switching signal106 is a signal for designating the timing of AC switching. Theselection signal107 is a signal for selecting whether the timing of AC switching is to be changed or not to be changed for every output. TheAC switching signal117 is a signal obtained by inverting or non-inverting theAC switching signal106 correspondingly to theselection signal107. Thecontrol signal108 is a signal for performing driving control of theoutput circuit131. The input signal levels of thedisplay data101,control signal group102,reference voltage104,inversion reference voltage105,AC switching signal106,selection signal107 and control signal108 are all in a range of from 0 V to 5 V. On the other hand, the level of the liquid crystal driving voltage requires about 15 V for the purpose of AC drive.

Accordingly, it is necessary to use a high rate withstand voltage process (rate voltage: 15 V) as the output circuit for outputting liquid crystal driving voltages. Therefore, thelevel shifter118 shifts the levels of the AC switching signals106 and117 and of thecontrol signal108 to high rate withstand voltage levels to supply these signals to theoutput circuit131. Theoutput circuit131 inverts or non-inverts thegray scale voltages130 on the basis of theinversion reference voltage105 correspondingly to the AC switching signals120 and121 to buffer-output inverted/non-inverted voltages as liquidcrystal driving voltages132. Thescanning circuit133 generates agate selection signal134 for selecting horizontal lines one by one on theliquid crystal panel135. Thus, theliquid crystal panel135 is driven by a liquidcrystal driving voltage132 supplied in synchronism with thegate selection signal134 so that display can be performed by liquid crystal driving voltages corresponding to display data, which are among the 64 levels of gray scale voltages of positive polarity or negative polarity.

FIG. 9 is a block diagram showing one of the data drivers depicted in FIG.1. InFIG. 9, the reference numerals901-1 to901-240 designate 6-bit latch circuits respectively for latching display data on the basis of thelatch signal124;902-1 to902-240, 6-bit latch circuits respectively for latching the display data simultaneously on the basis of thedisplay timing signal113;903, a gray scale voltage generating circuit for generating 64 levels of gray scale voltages from 9 levels ofreference voltages115;904, 64-level gray scale voltages generated by the gray scalevoltage generating circuit903;905-1 to905-240, selection circuits each of which selects one voltage level from the 64 grayscale voltage levels904 correspondingly to thedisplay data128 for each output;906-1 to906-240, output circuits each of which outputs a voltage obtained by inverting or non-inverting thegray scale voltage130 on the basis of theinversion reference voltage119 correspondingly to theAC switching signal120 or121 for each output; and132, the liquid crystal driving voltage.

Display data101 are latched successively by three pixels by thelatch circuit125 on the basis of thelatch signal124 generated by the latchaddress control circuit123. Specifically, thedisplay data112 are latched by three pixels (18 bits) successively by thelatch circuit125 so thatdisplay data112 are latched by 6-bit latch circuits901-1,901-2 and901-3 corresponding to the first group of three pixels, latched by 6-bit latch circuits901-4,901-5 and901-6 corresponding to the second group of three pixels and finally latched by 6-bit latch circuits901-238,901-239 and901-240 corresponding to the last group of three pixels.

Thus, the eight data drivers latch the display data successively, so that latching of display data corresponding to one line is completed. Thedisplay data126 thus latched by thelatch circuit125 correspondingly to one line are further latched by thelatch circuit127 simultaneously on the basis of thedisplay timing signal113. The reference voltages104 are 9-level voltages, which are buffered by thebuffer circuit114 and outputted asreference voltages115. Then, the gray scalevoltage generating circuit903 generates 64 levels of gray scale voltages from the 9 levels ofreference voltages115.

Referring now toFIG. 10, the gray scalevoltage generating circuit903 will be described in detail. The gray scalevoltage generating circuit903 generates 64 levels of gray scale voltages904 (from VG63 to VG0) by dividing 8 difference voltages between the 9-level reference voltages115 (from V8 to V0) bufferred by thebuffer circuit114 into 8 parts, respectively, with use of a resistance element. On the other hand, theinversion reference voltage105 is buffered by thebuffer circuit114 and outputted as aninversion reference voltage119.

Referring back toFIG. 9, thegray scale voltages904 are supplied to the gray scale voltage selection circuits905-1 to905-240 corresponding to the respective outputs. The gray scale voltage selection circuits905-1 to905-240 decode display data correspondingly to thedisplay data128 corresponding to the respective outputs, and each of the gray scale voltage selection circuits905-1 to905-240 selects one level from the 64 levels ofgray scale voltages904 to output the selected voltage as agray scale voltage130. That is, 64 levels ofgray scale voltages904 in a voltage level range of from 0 V to 5 V are generated from thereference voltages104 in a voltage level range of from 0 V to 5 V, so thatgray scale voltages130 corresponding to display data are selected from the 64 levels ofgray scale voltages904 correspondingly to the respective outputs.

Further, theAC switching signal106 and theselection signal107 are supplied to theEOR circuit116, in which theAC switching signal106 is outputted without inversion when the level of theselection signal107 is “Low” whereas theAC switching signal106 is outputted with inversion when the level of theselection signal107 is “High”. That is, theAC switching signal117 is the same as theAC switching signal106 when the level of theselection signal107 is “Low” whereas theAC switching signal117 is a signal obtained by inverting theAC switching signal106 when the level of theselection signal107 is “High”. Thecontrol signal108 is a signal for designating control of driving currents of the output circuits906-1 to906-240. The respective levels of the AC switching signals106 and117 and of thecontrol signal108 are shifted by thelevel shifter circuit118 in order to adjust the voltage to the signal level of theoutput circuit131 allowed to operate in a liquid crystal driving voltage level range (of from 5 V to −10 V), so that these signals are outputted as AC switching signals120 and121 and acontrol signal122, respectively.

In theoutput circuit131, each of the output circuits906-1 to906-240 corresponding to the respective outputs receives a positive-polaritygray scale voltage130, aninversion reference voltage119, AC switching signals120 and121 and acontrol signal122 and inverts or non-inverts thegray scale voltage130 on the basis of theinversion reference voltage119 correspondingly to the AC switching signal to thereby drive the liquid crystal panel. Referring now toFIG. 11, the output circuit906-1 will be described in detail. The output circuit906-1 is composed of aninversion amplification circuit1101, aselection circuit1103 and anoutput buffer circuit1105. A positive-polaritygray scale voltage130 is inverted with respect to theinversion reference voltage119 by theinversion amplification circuit1101, so that the resulting voltage is outputted as aninversion voltage1102. Thisinversion voltage1102 is obtained by inverting the positive-polaritygray scale voltage130.

Eithergray scale voltage130 orinversion voltage1102 selected by theselection circuit1103 correspondingly to theAC switching signal120 is outputted as anoutput voltage1104 and buffered by theoutput buffer circuit1105 to drive theliquid crystal panel135. Referring toFIG. 13, the timing of the AC output voltage will be described in detail. AC switching signals120 and121 correspond alternately to even-numbered and odd-numbered data driver outputs, respectively. Accordingly, in the case where the level of theselection signal107 is turned to a “High” level, the AC switching signals120 and121 become signals inverted to each other so that the timing of AC switching of the even-numbered outputs is different from the timing of AC switching of the odd-numbered outputs. That is, in this case, the odd-numbered outputs have negative polarity when the even-numbered outputs have positive polarity whereas the odd-numbered outputs have positive polarity when the even-numbered outputs have negative polarity. Further, in the case where the level of theselection signal107 is turned to a “Low” level, the AC switching signals120 and121 have equal polarity so that the timing of AC switching of the even-numbered outputs becomes equal to the timing of AC switching of the odd-numbered outputs. That is, in this case, the odd-numbered outputs have positive polarity when the even-numbered outputs have positive polarity whereas the odd-numbered outputs have positive negative when the even-numbered outputs have negative polarity. Further, in this case, the positive-polarity gray scale voltage and the negative-polarity gray scale voltage are reversed so as to be symmetric with respect to the inversion reference voltage119 (Vcen).

FIG. 12 is a configuration diagram of the output buffer circuit depicted in FIG.11. InFIG. 12, thereference numeral1201 designates a differential amplification circuit;1202 and1203, current amplification circuits; and1204, a selection circuit for making thecurrent amplification circuit1203 operative on the basis of thecontrol signal122.

Theoutput buffer circuit1105 is a voltage follower circuit which makes thedifferential amplification circuit1201 receive theoutput voltage1104 and makes thecurrent amplification circuits1202 and1203 amplify the current to drive theliquid crystal panel135. Thecontrol signal122 is a signal for controlling thecurrent amplification circuit1203. Thecurrent amplification circuit1203 is enabled to operate by turning the level of thecontrol signal122 to “High” level so that thecurrent amplification circuit1203 can cooperate with thecurrent amplification circuit1202 to output a large current, whereas thecurrent amplification circuit1203 is disabled from operating by turning the level of thecontrol signal122 to a “Low” level so that thecurrent amplification circuit1202 alone can output a small current. In this manner, electric power consumed by the current amplification circuits can be saved because current amplification can be performed by using the twocurrent amplification circuits1202 and1203 when a large output current is required and because thecurrent amplification circuit1203 can be disabled from operating so that thecurrent amplification circuit1202 alone is used for current amplification when such a large output current is not required.

Further, circuit portions surrounded by the broken line in the data driver inFIGS. 1 and 9 represent high rate withstand voltage processes (rate voltage: 15 V) and the others represent low rate withstand voltage processes (rate voltage: 5 V). As shown inFIG. 14, the chip area can be reduced by setting the level of the input signal in a range of from 5 V to GND, which allows the low rate withstand voltage process to operate and by setting thetiming control circuit110, the latchaddress control circuit123, thelatch circuits125 and127 and the gray scalevoltage generating circuit129 to be low ate withstand voltage processes small in gate length except setting theoutput circuit131 to be a high rate withstand voltage process large in gate length. In the present state of things, the gate length of the low rate withstand voltage process (rate voltage: about 5 V to about 3 V) which is the latest fine process is from about 1.0 μm to about 0.6 μm and the gate length of the high rate withstand voltage process (rate voltage: about 30 V to about 10 V) is about 5 μm to about 2 μm.

In the liquid crystal display using data drivers of this embodiment as described above, alternate-column inversion drive can be performed so that high quality image display can be made even in the case where the data drivers are arranged in one side of the liquid crystal panel as shown in FIG.15. Further, alternate-column inversion drive can be performed by AC switching for each line as shown inFIG. 16, so that higher quality image display can be made. Further, this embodiment may be applied to common electrode AC drive as long as the setting of theselection signal107 can be changed.

Although this embodiment has shown the case where 240-output data drivers are used as the data drivers, it is to be understood that the present invention may be applied also to the case where 192- or 160-output data drivers are used as the data drivers and that 192- or 160-output data drivers can be provided easily by rearranging the latch address control circuits and the latch circuits correspondingly to the number of outputs. Although the description of this embodiment has been made upon the case where the rate voltage of the low rate withstand voltage process and the rate voltage of the high rate withstand voltage process are 5 V and 15 V, respectively, the same effect as in this embodiment can be obtained in the case where the rate voltage of the low rate withstand voltage process and the rate voltage of the high rate withstand voltage process are, for example, in a range of from 5 V to 3 V and in a range of 30 V to 10 V, respectively.

The scanning driver in this embodiment will be described below.

As shown inFIG. 17, the operating voltage level of the data driver and the operating voltage level of the scanning driver are different from each other. Because of the characteristic of TFT of the liquid crystal panel, it is necessary that the gate selection signal outputted from the scanning driver be a voltage signal having upper and lower limits which are larger by about 3 V than the respective upper and lower limits of the liquid crystal supply voltage outputted from the data driver. Because the digital signal operating level of the scanning driver is 5 V which is a potential difference between VCC and VDD, there arises a difference between the voltage level of the digital input signal of the data driver and the voltage level of the digital input signal of the scanning driver. In a conventional liquid crystal panel, the level of the digital input signal is set as the signal level of the data driver while the level of the input signal to the scanning driver which is small in the number of signal lines is shifted by an external circuit so as to be adjusted before the input signal is inputted to the scanning driver. This is a main cause of increase in size of peripheral circuits used for the liquid crystal display.

In this embodiment, a level-shift circuit is provided in the input side of the scanning driver so that the circuit scale of the peripheral circuits can be reduced.FIG. 19 shows an example of configuration of the level-shift circuit. InFIG. 19, thereference numeral1901 designates a one-signal level-shift circuit using an inversion amplification circuit;1902, an input signal;1903, an inversion reference voltage for inversion and amplification; and1904, a signal obtained by inverting theinput signal1902 and then shifting the level thereof. This level-shift circuit1901 can be adapted to various input voltage levels as long as theinversion reference signal1903 is set correspondingly to the voltage level of the input signal. Further,FIG. 20 shows another example of configuration of the level-shift circuit. InFIG. 20, thereference numeral2001 designates a level-shift circuit;2002, an input signal;2003, a signal obtained by non-inverting theinput signal2002 and then shifting the level thereof; and2004 and2005, inverter circuits.

The threshold voltage of the inverter circuit2004 is set to the center of the input signal level, and the amplitude level thereof is VCC-VSS. The amplitude level of the inverter circuit2005 is VCC-VSS. In this level-shift circuit2001, inversion/non-inversion level-shifted signals can be outputted without necessity of the reference voltage as shown in the level-shift circuit1901.

Further, as shown inFIG. 18, the level of the input signal may be shifted to the level of VCC-VSS so that circuit operation is performed at the amplitude level of VCC-VSS. Also in this case, the reduction of the circuit scale of peripheral circuits can be attained. This can be realized when an inverter circuit having a threshold voltage set to the center of the input signal level is provided in the input side of the scanning driver.

As described above, in this embodiment, because a buffer circuit for buffering 9-level liquidcrystal reference voltages104 is arranged in the input side of each data driver, the driving current is small so that the circuit scale of theelectric source circuit103 can be reduced.

A second embodiment of the present invention in which data drivers for performing 64-level gray scale display on the basis of 9-level reference voltages are used will be described below. The gray scale voltage generating circuit in this embodiment is different from that in the first embodiment, but the other circuits in this embodiment are similar to those in the first embodiment.

FIG. 21 is a detailed block diagram of the data driver109-1 depicted in FIG.1.

InFIG. 21, the reference numerals2101-1 to2101-240 designate selection circuits each of which selects one level from thereference voltages115 correspondingly to displaydata128 for each output;2102-1 to2102-240, output circuits each of which outputs a voltage obtained by inverting or non-inverting thegray scale voltage130 on the basis of theinversion reference voltage119 correspondingly to theAC switching signal120 or121 for each output; and132, liquid crystal driving voltages.

Thedisplay data101 are latched by three pixels successively by thelatch circuit125 on the basis of thelatch signal124 generated by the latchaddress control circuit123. Specifically, thedisplay data101 are latched by three pixels (18 bits) by thelatch circuit125 successively in a manner so thatdisplay data112 are latched by 6-bit latch circuits901-1,901-2 and901-3 corresponding to the first group of three pixels, next latched by 6-bit latch circuits901-4,901-5 and901-6 corresponding to the second group of three pixels and finally latched by 6-bit latch circuits901-238,901-239 and901-240 corresponding to the last group of three pixels.

Thus, the eight data drivers latch the display data successively, so that latching of display data corresponding one line is completed. Thedisplay data126 thus successively latched by thelatch circuit125 correspondingly to one line are latched simultaneously by thelatch circuit127 on the basis of thedisplay timing signal113. The reference voltages104 which are 9-level reference voltages are buffered by thebuffer circuit114 and then outputted asreference voltages115. On the other hand, theinversion reference voltage105 is buffered by thebuffer circuit114 and then outputted as aninversion reference voltage119.

The reference voltages115 are supplied to the gray scale voltage generating circuits2101-1 to2101-240 corresponding to respective outputs. The gray scale voltage generating circuits2101-1 to2101-240 generategray scale voltages130 corresponding to display data from thedisplay data128 and thereference voltages115 corresponding to the respective outputs.

FIG. 22 is a block diagram of one of gray scale voltage generating circuits in a data driver. InFIG. 22, thereference numeral2201 designates a decoder for decoding thedisplay data128;2202, a decoded signal constituted by upper three bits of the display data decoded by thedecoder2201;2203, a decoded signal constituted by lower three bits of the display data decoded by thedecoder2201;2204, a selection circuit for selecting one level from 8 levels of from V8 to V1 among the 9-level reference voltages115 on the basis of he decodedsignal2202;2205, a selection circuit for electing one level from 8 levels of from V7 to V0 among the 9-level reference voltages115 on the basis of the decodedsignal2202;2206 and2207, voltages selected by theselection circuits2204 and2205, respectively;2208, a voltage dividing circuit for dividing the potential difference between the selectedvoltages2206 and2207 into eight by eight resistance elements;2209, 8 levels of gray scale voltages obtained by thevoltage dividing circuit2208; and2210, a selection circuit for selecting one level from the 8 levels ofgray scale voltages2209 on the basis of the decodedsignal2203.

The 6-bit display data128 which express 64 gray scales are decoded by thedecoder2201 so that the upper three bits of thedisplay data128 and the lower three bits thereof are independent from each other. The decodedsignal2202 of the upper three bits on 8 lines is supplied to theselection circuits2204 and2205, and the decoded signal of the lower three bits on 8 lines is supplied to theselection circuit2210. Theselection circuit2204 selects one level from 8 levels of from V8 to V1 among the 9-level reference voltages115 (V8 to V0) correspondingly to the decodedsignal2202. Theselection circuit2205 selects one level from 8 levels of from V7 to V0 among the 9-level reference voltages115 (V8 to V0) correspondingly to the decodedsignal2202. Assume now that combinations of the two voltages which are selected by theselection circuits2204 and2205, respectively, are V8-V7, V7-V6, V6-V5, V5-V4, V4-V3, V-3-V2, V2-V1, and V1-V0.

Thevoltage dividing circuit2208 divides the potential difference between the two selectedvoltages2206 and2207 into eight to generate 8 levels of gray scale voltages in between the two selected voltages. Theselection circuit2210 selects one level from the 8 levels ofgray scale voltages2209 generated by the voltage dividing circuit correspondingly to the decodedsignal2203 to output the selected level as agray scale voltage130. In this manner, 64 levels of gray scale voltages can be generated by using eight combinations of the selectedvoltages2206 and2207 and division of potential difference in each combination into eight. That is, 64 levels of gray scale voltages in a range of from 0 V to 5 V are generated from thereference voltages104 having voltage levels of from 0 V to 5 V, so that agray scale voltage130 corresponding to the display data is selected from the 64 levels of gray scale voltages correspondingly to each output.

FIG. 23 is a block diagram of one of theoutput circuits131 in a data driver. Each of output circuits2102-1 to2102-240 corresponding to respective outputs receives a positive-polaritygray scale voltage130, aninversion reference voltage119, AC switching signals120 and121 and acontrol signal122. Thegray scale voltage130 is inverted or non-inverted on the basis of theinversion reference voltage119 correspondingly to theAC switching signal120 to thereby drive the liquid crystal panel. The output circuit2102-1 is composed of anon-inversion amplification circuit2301, aninversion amplification circuit2302, and aselection circuit2305. The positive-polaritygray scale voltage130 is amplified by thenon-inversion amplification circuit2301 and outputted as apositive voltage2303. On the other hand, the positive-polaritygray scale voltage130 is inverted on the basis of theinversion reference voltage119 by theinversion amplification circuit2302 and outputted as aninversion voltage2304.

Theinversion voltage2304 which is a voltage obtained by inverting the positive-polaritygray scale voltage130 corresponds to a negative-polarity liquid crystal driving voltage. Eitherpositive voltage2303 orinversion voltage2304 is selected by theselection circuit2305 correspondingly to theAC switching signal120 and outputted as anoutput voltage132 to drive theliquid crystal panel135.

A third embodiment of the present invention will be described below. This embodiment is different from the first embodiment in the circuit for inverting the reference voltage.

FIG. 24 is a configuration diagram of the liquid crystal display device in the third embodiment. InFIG. 24, thereference numeral2401 designates display data transferred from a system;2402, a group of control signals;2403, an AC switching signal expressing the timing of AC switching;2404, an power supply circuit or generating reference voltages which are used for generating liquid crystal driving voltages; and2405 and2406, DC reference voltages generated by theelectric source circuit2404. The reference numerals2407-1 to2407-10 designate data drivers each having 192 outputs. In each of the data drivers, thereference numeral2408 designates a timing control circuit;2409, a group of timing signals;2410, display data;2411, a timing signal expressing display timing;2412, a latch address control circuit;2413, a group of latch signals generated by the latchaddress control circuit2412;2414, a latch circuit for latching thedisplay data2410 successively;2415, display data latched by thelatch circuit2414;2416, a latch circuit for latching thedisplay data2415 simultaneously on the basis of thetiming signal2411; and2417, display data latched by thelatch circuit2416. Thereference numeral2418 designates a voltage generating circuit for generating AC reference voltages used for AC driving the liquid crystal on the basis of thereference voltages2405 and2406; and2419 and2420, AC reference voltages generated by the voltage generating circuit. Thereference numeral2421 designates a liquid crystal driving circuit for generating liquid crystal driving voltages corresponding to thedisplay data2417 on the basis of theAC reference voltages2419 and2420; and2422, liquid crystal driving voltages generated by the liquidcrystal driving circuit2421. Thereference numeral2423 designates a scanning circuit;2424, gate driving signals successively selected by thescanning circuit2423; and2425, a liquid crystal panel.

The data drivers are required because the number of outputs from each of the data drivers2407-1 to2407-10 is 192 and because the resolution of theliquid crystal panel2425 is 640×RGB×480 pixels. Thedisplay data2401 which are 18-bit display data (3 pixels×6 bits for gray scales) are transferred successively, so that latch signals2413 synchronized with thedisplay data2401 are generated by the latchaddress control circuits2412 on the basis of thecontrol signal group2409 to thereby latch thedisplay data2410 in thelatch circuits2414 successively. Each of thelatch circuits2414 has latch circuits for latching 192 pixels (6 bits per one pixel) so that display data corresponding to one horizontal line can be latched successively in the data drivers2407-1 to2407-10. Thedisplay data2415 thus latched by thelatch circuits2414 correspondingly to one horizontal line are further latched simultaneously by thelatch circuits2416 on the basis of thedisplay timing signal2411 synchronized with thegate selection signal2424 outputted from thescanning circuit2423. Thedisplay data2417 thus latched are supplied to the liquidcrystal driving circuit2421. Thevoltage generating circuit2418 generatesAC reference voltages2419 and2420 different in AC switching timing from each other on the basis of thereference voltages2405 and2406 generated by thepower supply circuit2404 and theAC switching signal2403 so as to be supplied to the liquidcrystal driving circuit2421. In the liquidcrystal driving circuit2421, liquidcrystal driving voltages2422 corresponding to thedisplay data2417 are generated on the basis of theAC reference voltages2419 and2420 to thereby drive theliquid crystal panel2425.

InFIG. 25, the reference numerals2501-1 to2501-192 designate liquid crystal driving circuits corresponding to respective outputs.

TheAC reference voltages2419 and2420 are supplied to the liquid crystal driving circuits2501-1 to2501-192 alternately for the 192 outputs. Each of the liquid crystal driving circuits2501-1 to2501-192 generates and outputs 64 levels of liquid crystal driving voltages on the basis of the display data of 6 bits per one output and 9 levels ofAC reference voltages2419 or2420. The 64 levels of liquid crystal driving voltages can be outputted by selecting 2 levels from the 9 levels of AC reference voltages with use of upper 3 bits of the 6-bit display data and then selecting one level from 8 levels of voltages obtained by dividing the selected two levels of voltages into 8 equal parts with use of lower 3 bits of the display data. In this manner, the data driver can generate a liquid crystal driving voltage in which AC switching timing varies correspondingly to each output, so that alternate-column inversion drive of theliquid crystal panel2425 can be performed.

Although this embodiment has shown the case where each of the liquid crystal driving circuits has a structure in which AC reference voltages different in AC switching timing are switched over once per one output, the present invention can be applied to the case where AC reference voltages are switched over once per two outputs or once per a plurality of outputs.

FIG. 26 is a configuration diagram of one of the voltage generating circuits depicted in FIG.24. InFIG. 26, the reference numerals2601-0 to2601-8 designate amplification buffer circuits;2602-0 to2602-8, differential amplification circuits; and2603-0 to2603-8 and2604-0 to2604-8, selection circuits.

Reference voltages2405 of 9 levels VLEV0 to VLEV9 from theelectric source circuit2404 are buffered by the amplification buffer circuits2601-0 to2601-8 and supplied to the differential amplification circuits2602-0 to2602-8 and the selection circuits2603-0 to2603-8 and2604-0 to2604-8, respectively. In the differential amplification circuits2602-0 to2602-8, the reference voltages (VLEV0 to VLEV8)2405 are inverted and outputted on the basis of the reference voltage (VCEN)2406. The selection circuits2603-0 to2603-8 and2604-0 to2604-8 receive the outputs of the amplification buffer circuits2601-0 to2601-8 and the outputs of the differential amplification circuits2602-0 to2602-8, respectively, and select these outputs on the basis of theAC switching signal2403. Because inverted AC switching signals are inputted to the selection circuits2604-0 to2604-8, the polarity of voltages selected by the selection circuits2603-0 to2603-8 and the polarity of voltages selected by the selection circuits2604-0 to2604-8 are reversed to each other.

This timing is shown in FIG.27. When the level of the AC switching signal (M)2403 is high, AC reference voltages (V1RV0 to V1RV8)2419 selected by the selection circuits2603-0 to2603-8 are outputted as values VLEV01NV-VLEV81NV, respectively, and AC reference voltages (V2RV0 to V2RV8)2420 selected by the selection circuits2604-0 to2604-8 are outputted as values VLEV0-VLEV8, respectively. When the level of the AC switching signal (M)2403 is contrariwise low, AC reference voltages (V1RV0 to V1RV8)2419 selected by the selection circuits2603-0 to2603-8 are outputted as values VLEV0-VLEV8, respectively, and AC reference voltages (V2RV0 to V2RV8)2420 selected by the selection circuits2604-0 to2604-8 are outputted as values VLEV01NV-VLEV81NV, respectively. In this manner,AC reference voltages2419 and2420 different in AC switching timing from each other are generated.

A fourth embodiment of the present invention will be described below. This embodiment is similar to the third embodiment except that voltage generating circuits used in this embodiment are assembled so as to be different from those in the third embodiment so that this embodiment can be adapted to common electrode AC drive of the liquid crystal panel.FIG. 28 is a block diagram showing the liquid crystal display device according to the present invention.

InFIG. 28, thereference numeral2801 designates control circuits for controlling the timing of AC reference voltages;2802, data drivers; and2803, voltage generating circuits for generating AC reference voltages which are used for AC driving the liquid crystal on the basis of thereference voltages2405 and2406.

The data drivers are required because the number of outputs from each of the data drivers2802-1 to2802-10 is 192 and because the resolution of theliquid crystal panel2425 is 640×RGB×480 pixels. Thedisplay data2401 which are 18-bit display data (3 pixels×6 bits for gray scales) are transferred successively, so that latch signals2413 synchronized with thedisplay data2401 are generated by the latchaddress control circuits2412 on the basis of thecontrol signal group2409 to thereby latch thedisplay data2410 in thelatch circuits2414 successively. Each of thelatch circuits2414 has latch circuits for latching 192 pixels (6 bits per one pixel) so that display data corresponding to one horizontal line can be latched successively in the data drivers2802-1 to2802-10. Thedisplay data2415 thus latched by thelatch circuits2414 correspondingly to one horizontal line are further latched simultaneously by thelatch circuits2416 on the basis of thetiming signal2411 synchronized with thegate selection signal2424 outputted from thescanning circuit2423. Thedisplay data2417 thus latched are supplied to the liquidcrystal driving circuits2421. Thevoltage generating circuits2803 generateAC reference voltages2419 and2420 on the basis of thereference voltages2405 and2406 generated by theelectric source circuit2404, theAC switching signal2403 and thecontrol signal2801 so as to be supplied to the liquidcrystal driving circuits2421. In the liquidcrystal driving circuits2421, liquidcrystal driving voltages2422 corresponding to thedisplay data2417 are generated on the basis of theAC reference voltages2419 and2420 to thereby drive theliquid crystal panel2425.

FIG. 29 is a block diagram of one of the voltage generating circuits in the fourth embodiment. InFIG. 29, thereference numeral2901 designates a circuit for switching the AC switching timing.

Reference voltages2405 of 9 levels VLEV0 to VLEV8 from theelectric source circuit2404 are buffered by the amplification buffer circuits2601-0 to2601-8 and supplied to the differential amplification circuits2602-0 to2602-8 and the selection circuits2603-0 to2603-8 and2604-0 to2604-8, respectively. In the differential amplification circuits2602-0 to2602-8, the voltages (VLEV0 to VLEV8) are inverted with respect to the reference voltage (VCEN)2406.

FIG. 30 is a timing chart showing the generation of liquid crystal reference voltages in this case. As is obvious fromFIG. 30, the voltages VLEV0 to VLEV8 are turned to voltages VLEV01NV to VLEV81NV inverted with respect to the reference voltage VCEN. The selection circuits2603-0 to2603-8 and2604-0 to2604-8 receive the outputs of the amplification buffer circuits2601-0 to2601-8 and the outputs of the differential amplification circuits2602-0 to2602-8, respectively, and select these outputs on the basis of theAC switching signal2403. Because theswitching circuit2901 performs exclusive ORing of the AC switching signal (M)2403 and the control signal (SVCOM)2801 and supplies the result of the exclusive ORing to the selection circuits2604-0 to2604-8, the polarity of voltages selected by the selection circuits2603-0 to2603-8 and the polarity of voltages selected by the selection circuits2604-0 to2604-8 are reversed to each other when the level of the control signal (SVCOM)2801 is high, and the polarity of voltages selected by the selection circuits2603-0 to2603-8 and the polarity of voltages selected by the selection circuits2604-0 to2604-8 are the same with each other when the level of the control signal (SVCOM)2801 is low. That is, when the level of the control signal (SVCOM)2801 is high, the voltage generating timing is the same as that in the third embodiment.

When the level of the control signal (SVCOM)2801 is low, as shown inFIG. 30, AC reference voltages (V1RV0 to V1RV8)2419 selected by the selection circuits2603-0 to2603-8 are outputted as values VLEV01NV to VLEV81NV and AC reference voltages (V2RV0 to V2RV8)2420 selected by the selection circuits2604-0 to2604-8 are outputted similarly as values VLEV01NV to VLEV81NV as long as the level of the AC switching signal (M)2403 is high, whereas AC reference voltages (V1RV0 to V1RV8)2419 selected by the selection circuits2603-0 to2603-8 are outputted as values VLEV0 to VLEV8 and AC reference voltages (V2RV0 to V2RV8)2420 selected by the selection circuits2604-0 to2604-8 are outputted similarly as values VLEV0 to VLEV8 as long as the level of the AC switching signal (M)2403 is low. In the case of common electrode AC drive, it is necessary to make the AC switching timing of the respective outputs of the data driver equal for AC switching the common electrode (VCOM) as shown in FIG.30. Accordingly, the timing of AC switching of theAC reference voltages2419 and2420 can be controlled by switching thecontrol signal2801, so that the present invention can be adapted to common electrode drive easily.

A fifth embodiment of the present invention will be described below. This embodiment is similar to the third embodiment except that voltage generating circuits used in this embodiment are different from those in the third embodiment.FIG. 31 is a block diagram of one of the voltage generating circuits.

InFIG. 31, the reference numerals3101-0 to3101-8 designate amplification buffer circuits;3102-0 to3102-8, level-shift circuits; and3103-0 to3103-8 and3104-0 to3104-8, selection circuits.

Reference voltages2405 of 9 levels VLEV0 to VLEV8 from theelectric source circuit2404 are buffered by the amplification buffer circuits3101-0 to3101-8 and supplied to the level-shift circuits3102-0 to3102-8 and the selection circuits3103-0 to3103-8 and3104-0 to3104-8, respectively. In the level-shift circuits3102-0 to3102-8, the levels of the reference voltages (VLEV0 to VLEV8)2405 are shifted correspondingly to the voltage level of the reference voltage (VSH)2406.

FIG. 32 shows the timing of reference voltages and liquid crystal driving voltages. The voltages VLEV0 to VLEV8 are turned to voltages VLEV0SFT to VLEV8SFT having levels shifted by the voltage level VSH, respectively. The selection circuits3103-0 to3103-8 and3104-0 to3104-8 receive the outputs of the amplification buffer circuits3101-8 to3101-0 and the outputs of the level-shift circuits3102-0 to3102-8, respectively, and select these outputs on the basis of theAC switching signal2403. Because inverted AC switching signals are supplied to the selection circuits3104-0 to3104-8, the polarity of voltages selected by the selection circuits3103-0 to3103-8 and the polarity of voltages selected by the selection circuits3104-0 to3104-8 are reversed to each other. When the level of the AC switching signal (M)2403 is high, AC reference voltages (V1LS0 to V1LS8)2419 selected by the selection circuits3103-0 to3103-8 are outputted as values VLEV8SFT to VLEV0SFT, respectively, and AC reference voltages (V2LS0 to V2LS8)2420 selected by the selection circuits3104-0 to3104-8 are outputted as values VLEV0 to VLEV8, respectively.

When the level of the AC switching signal (M)2403 is contrariwise low, AC reference voltages (V1LS0 to V1LS8)2419 selected by the selection circuits3103-0 to3103-8 are outputted as values VLEV0 to VLEV8, respectively, and AC reference voltages (V2LS0 to V2LS8)2420 selected by the selection circuits3104-0 to3104-8 are outputted as values VLEV8SFT to VLEV0SFT, respectively. In this manner,AC reference voltages2419 and2420 different in AC switching timing from each other are generated.

Next, the operation of the liquidcrystal driving circuit2421 is the same as in the third embodiment. In the configuration as described above, the data drivers can generate liquid crystal driving voltages different in AC switching timing correspondingly to each output, so that alternate-column inversion drive of theliquid crystal panel2425 can be achieved.

A sixth embodiment of the present invention will be described below.

FIG. 33 is a block diagram showing a liquid crystal display device. InFIG. 33, thereference numeral3301 designates display data transferred from a system;3302, a group of control signals;3303, an AC switching signal expressing the timing of AC switching;3304, an power supply circuit for generating reference voltages which are used for generating liquid crystal driving voltages; and3305 and3306, DC reference voltages generated by the electric source circuit3330-4. The reference numerals3307-1 to3307-10 designate data drivers each of which has 192 outputs. In each of the data drivers, thereference numeral3308 designates a timing control circuit;3309, a group of timing signals;3310, a data bus for display data and AC switching signal;3311, a timing signal expressing the display timing;3312, a latch address control circuit;3313, a group of latch signals generated by the latchaddress control circuit3312;3314, a latch circuit for latching data through thedata bus3310 successively;3315, a data bus for display data latched by thelatch circuit3314 and AC switching signal;3316, a latch circuit for latching data through thedata bus3315 simultaneously on the basis of thetiming signal3311; and3317, a data bus for display data latched by thelatch circuit3316 and AC switching signal.

Thereference numeral3318 designates a voltage generating circuit for generating AC reference voltages which are used for AC driving the liquid crystal on the basis of thereference voltages3305 and3306; and3319 and3320, positive-polarity and negative-polarity reference voltages generated by the voltage generating circuit. Thereference numeral3321 designates a liquid crystal driving circuit for generating liquid crystal driving voltages corresponding to thedata bus3317 for display data and AC switching signal on the basis of thereference voltages3319 and3320; and3322, liquid crystal driving voltages generated by the liquidcrystal driving circuit3321. The reference numeral3323 designates a scanning circuit;3324, gate driving signals successively selected by the scanning circuit3323; and3325, a liquid crystal panel.

Ten data drivers are required because the number of outputs from each of the data drivers3307-1 to3307-10 is 192 and because the resolution of theliquid crystal panel2425 is 640×RGB×480 pixels. Thedisplay data3301 which are 18-bit data (3 pixels×6 bits for gray scales), and the AC switching signal3303 composed of 3 bits per 3 pixels, are transferred successively, so that latch signals3313 synchronized with thedisplay data3301 and the AC switching signal3303 are generated by the latchaddress control circuits3312 on the basis of thecontrol signal group3309 to thereby latch the data from thedata bus3310 into thelatch circuits3314 successively. Each of thelatch circuits3314 has latch circuits for latching 192 pixels (6 bits for display data and 1 bit for AC switching signal per one pixel) so that display data and AC switching signal corresponding to one horizontal line can be latched successively in the data drivers3307-1 to3307-10.

The display data and AC switching signal latched by thelatch circuits3314 correspondingly to one horizontal line are latched simultaneously through thedata bus3315 by thelatch circuits3316 on the basis of thetiming signal3311 synchronized with the gate selection signal3324 of the scanning circuit3323. Thedata bus3317 thus latched is supplied to the liquidcrystal driving circuits3321. Thevoltage generating circuits3318 generate differentAC reference voltages3319 and3320 corresponding to two levels of AC switching on the basis of thereference voltages3305 and3306 generated by theelectric source circuit3304 and supply theAC reference voltages3319 and3320 to the liquidcrystal driving circuits3321, respectively. The liquidcrystal driving circuits3321 generate liquidcrystal driving voltages3322 corresponding to thedisplay data3317 on the basis of theAC reference voltages3319 and3320 to thereby drive the liquid crystal panel3325.

FIG. 34 is a block diagram of one of the liquid crystal driving circuits. InFIG. 34, the reference numerals3401-1 to3401-192 designate liquid crystal driving circuits for respective outputs;3317-1M to3317-192M, AC switching signals for respective outputs with respect to thedata bus3317; and3317-1D to3317-192D, display data for respective outputs.

TheAC reference voltages3319 and3320 are supplied to the liquid crystal driving circuits3401-1 to3401-192 for 192 outputs, respectively. Each of the liquid crystal driving circuits3401-1 to3401-192 generates 64 levels of liquid crystal driving voltages on the basis of thedata bus3317 containing 6-bit display data and AC switching signal per one output and the 9 levels ofAC reference voltages3319 or3320. The 64 levels of liquid crystal driving voltages can be outputted by selecting eitherAC reference voltage3319 orAC reference voltage3320 as an AC switching signal, selecting 2 levels from the 9 levels of AC reference voltages with use of upper 3 bits of the 6-bit display data and then selecting one level from 8 levels of voltages obtained by dividing the selected two levels of voltages into 8 equal parts with use of lower 3 bits of the display data.

FIG. 35 is a block diagram of one of the voltage generating circuits.Reference voltages3305 of 9 levels VLEV0 to VLEV8 from theelectric source circuit3304 are buffered by the amplification buffer circuits3501-0 to3501-8, supplied to the differential amplification circuits3502-0 to3502-8 and then outputted as reference voltages V1L0 to V1L8, respectively. In the differential amplification circuits3502-0 to3502-8, the reference voltages (VLEV0 to VLEV8)3305 are inverted with respect to the reference voltage (VCEN)3306 and outputted as reference voltages V2L0 to V2L8, respectively. The voltages VLEV0 to VLEV8 are buffered and outputted as reference voltages V1L0 to V1L8 and outputted as reference voltages V2L0 to V2L8 inverted with respect to VCEN, respectively.

FIG. 36 shows the timing of reference voltage and liquid crystal driving voltage. Liquid crystal driving voltages are generated correspondingly to AC switching signals by inverting the AC switching signals in the n-th output terminal Yn and in the (n+1)-th output terminal Yn+1 to each other. That is, when an output terminal Yn generates a liquid crystal driving voltage corresponding to the AC reference voltage3319 (V1L0 to V1L8), the next output terminal Yn+1 generates a liquid crystal driving voltage corresponding to the AC reference voltage3320 (V2L0 to V2L8). When the output terminal Yn generates a liquid crystal driving voltage corresponding to the AC reference voltage3320 (V2L0 to V2L8), the next output terminal Yn+1 generates a liquid crystal driving voltage corresponding to the AC reference voltage3319 (V1L0 to V1L8).

In the configuration as described above, the data drivers can generate liquid crystal driving voltages different in AC switching timing for respective outputs, so that alternate-column inversion drive of the liquid crystal panel3325 can be achieved. Further, the AC switching timing can be changed easily once per two outputs, once per a plurality of outputs, once per one line, or the like, by changing the setting of the AC switching signal transferred in synchronism with display data.

Further, as a seventh embodiment of the present invention, there is shown an embodiment of the output circuit for attaining saving of consumed electric power and reduction of chip size in the first and second embodiments. This embodiment is different from the first and second embodiments only in the output circuit.FIG. 37 is a timing chart showing the timing of output waveforms, andFIG. 38 is a block diagram of the output circuit.

In the first and second embodiments, a combination of a normal amplification circuit and an inversion amplification circuit is required for each output. On the contrary, in this embodiment, a combination of a normal amplification circuit and an inversion amplification circuit is used so as to be common to two outputs, so that the chip size can be reduced. InFIG. 38, the reference numerals3801-1 to3801-240 designate selectors which select gray scale voltages correspondingly to adjacent outputs of gray scale voltages130-1 to130-240. The reference numerals3802-1 to3802-240 designate normal amplification circuits and inversion amplification circuits which pass or invert the gray scale voltages selected by the corresponding selectors3801. The reference numerals3803-1 to3803-240 designate selectors each of which selects one from outputs of adjacent amplification circuits3802. These operations will be described below in conjunction with output terminals Y1 and Y2. A gray scale voltage130-1 corresponding to the output terminal Y1 and a gray scale voltage130-2 corresponding to the output terminal Y2 are supplied to the normal amplification circuit3802-1 or the inversion amplification circuit3802-2 through the selectors3801-1 and3801-2, respectively. Further, the outputs of the normal amplification circuit3802-1 and the inversion amplification circuit3802-2 are selected by the selectors3803-1 and3803-2, respectively, and outputted to the output terminals Y1, Y2. Aselection signal3805 for the selectors3801 and3803 is a selection signal switched in synchronism with theAC switching signal106. Therefore, when the gray scale voltage130-1 corresponding to the output terminal Y1 is normally supplied to the output terminal Y1, the gray scale voltage130-2 corresponding to the output terminal Y2 is inverted with respect to theinversion reference voltage119 and then supplied to the output terminal Y2. When the gray scale voltage130-1 corresponding to the output terminal Y1 is contrariwise inverted with respect to theinversion reference voltage119 and then supplied to the output terminal Y1, the gray scale voltage130-2 corresponding to the output terminal Y2 is normally supplied to the output terminal Y2. In this manner, liquid crystal driving voltages which are inverted to each other in AC switching timing can be supplied to adjacent output terminals.

Further, as shown inFIG. 37, before liquid crystal supply voltages are outputted, an equalizing period in which adjacent output terminals are connected by the switching circuits3805-1 to3805-120 while the outputs are turned into a high impedance state by the switching circuits3804-1 to3804-240 is provided so that an operation in which precharging to the level of 10 V is assisted by positive-polarity and negative-polarity electric charge on data lines of the liquid crystal panel is carried out. In this manner, liquid crystal driving power can be reduced by using electric charge remaining in the liquid crystal panel.

Claims (29)

1. A liquid crystal driver comprising:

a plurality of output terminals for outputting display voltages to be applied to a liquid crystal display device;

an input terminal for receiving display data corresponding to said plurality of output terminals; and

output means for converting said input display data into said output display voltages;

wherein said output means selects a display voltage level corresponding to one input display data and simultaneously generates two different display voltages from the selected display voltage level so that either one of said two different display voltages can be selected as an output display voltage for each of said output terminals.

2. A liquid crystal driver according toclaim 1, wherein said two different display voltages are a display voltage higher than a reference voltage and a display voltage lower than the reference voltage.

3. A liquid crystal driver according toclaim 1, wherein a display voltage to be selected from said two different display voltages is determined on the basis of a signal received from outside the liquid crystal driver.

4. A liquid crystal driver according toclaim 1, wherein a display voltage to be selected from said two different display voltages is determined on the basis of input information received together with the display data.

5. A liquid crystal driver according toclaim 2, wherein said two different display voltages are inverted relative to each other so as to be symmetric relative to each other with respect to said reference voltage.

6. A liquid crystal driver according toclaim 2, wherein one of said two different display voltages is shifted by an amount corresponding to said reference voltage compared with another one of said two different display voltages.

7. A liquid crystal driver according toclaim 1, wherein said output means includes level-shift means for shifting said output display voltages with respect to said output terminals.

8. A liquid crystal driver according toclaim 1, wherein a signal obtained by periodically switching between said two different display voltages is outputted at each of said output terminals.

9. A liquid crystal driver according toclaim 2, wherein during a certain period, a display voltage higher than said reference voltage and a display voltage lower than said reference voltage are respectively supplied to two arbitrary adjacent output terminals.

10. A liquid crystal driver according toclaim 1, wherein the liquid crystal driver is constituted by one LSI.

11. A liquid crystal display device comprising:

a liquid crystal panel including pixel portions which are arranged at positions of intersections of a plurality of data lines and a plurality of scanning lines in the form of a matrix;

a scanning driver for successively supplying voltages to said plurality of scanning lines; and

a liquid crystal driver as defined inclaim 1 for receiving display data and supplying display voltages to said plurality of data lines in correspondence to said display data.

12. A liquid crystal display device according toclaim 11, wherein said scanning driver includes a level-shift circuit for receiving an input signal of a same level as a level of a signal received by said liquid crystal driver, and shifting the level of said input signal to a level allowed to be used in said scanning driver.

13. A liquid crystal driver according toclaim 1, wherein said output means includes two different-characteristic output amplification circuits for two adjacent output terminals so that said two different display voltages can be selected and outputted by switching connections between two gray scale voltage data generated on the basis of input display data corresponding to said two output terminals and input terminals of said two output amplification circuits, and connections between output terminals of said two output amplification circuits and said two output terminals on the basis of an external signal.

14. A liquid crystal driver according toclaim 1, wherein said output means includes a combination of a non-inversion output amplification circuit and an inversion output amplification circuit for two adjacent output terminals so that said two different display voltages can be alternately outputted by alternately switching connections between two gray scale voltage data generated on the basis of input display data corresponding to said two output terminals and input terminals of said combination of output amplification circuits, and connections between output terminals of said combination of output amplification circuits and said two output terminals on the basis of an external signal.

15. A liquid crystal driver according toclaim 9, wherein said output means includes connection means which connects together two adjacent output terminals outputting a display voltage higher than said reference voltage and a display voltage lower than said reference voltage so that said two adjacent output terminals are connected together during a predetermined period before output display voltages of the two adjacent output terminals are switched.

16. A method of applying display voltages to a liquid crystal display device, the method comprising the steps of:

receiving display data corresponding to output terminals which output display voltages;

generating gray scale display voltage levels on the basis of reference voltages;

selecting one of the gray scale display voltage levels for each output terminal in accordance with said display data, the selected gray scale display voltage level being a first display voltage for the output terminal;

supplying an AC switching signal and an inversion reference voltage, said AC switching signal having a polarity which is periodically inverted;

inverting said selected gray scale voltage level with respect to said inversion reference voltage to generate an inverted selected gray scale display voltage level, the inverted selected gray scale display voltage level being a second display voltage for the output terminal, the second display voltage being different from the first display voltage, the first display voltage and the second display voltage being available simultaneously;

selecting one of the first display voltage and the second display voltage in accordance with the AC switching signal as an output display voltage for the output terminal; and

outputting the output display voltage from the output terminal.

17. A display device comprising:

a display panel having a plurality of pixels arranged corresponding to crossing points of a plurality of data lines and a plurality of scan lines; and

a driver being arranged on a single side of the display panel and connected with the data lines for outputting gray scale voltages corresponding to display data consisting of a plurality bits to the pixels via the data lines;

wherein the driver outputs the gray scale voltages having polarity different from each other to adjacent two data lines;

wherein the driver includes:

a first amplifier for outputting the gray scale voltage having a positive polarity corresponding to the display data to one of the adjacent two data lines;

a second amplifier for outputting the gray scale voltage having a negative polarity corresponding to the display data to an other of the adjacent two data lines; and

a selector for switching an output destination of the positive polarity gray scale voltage output from the first amplifier between the one of the adjacent two data lines and the other of the adjacent two data lines while switching an output destination of the negative polarity gray scale voltage output from the second amplifier between the other of the adjacent two data lines and the one of the adjacent two data lines;

wherein the adjacent two pixels on the display panel connected to the adjacent two data lines having polarity different from each other.

18. The display device according toclaim 17, wherein a pair of the first amplifier and the second amplifier is shared by the adjacent two data lines.

19. The display device according toclaim 17, wherein the selector switches the output destination of the positive polarity gray scale voltage output from the first amplifier and also switches the output destination of the negative polarity gray scale voltage output from the second amplifier in accordance with an AC switching signal.

20. The display device according toclaim 17, wherein the driver further includes:

a first latch for holding the input display data;

a second latch for collectively holding the display data in the first latch according to a timing signal; and

a selection circuit for selecting one of a plurality of gray scale voltages as the gray scale voltage corresponding to the display data in the second latch.

21. The display device according toclaim 17, wherein the first amplifier and the second amplifier simultaneously output the positive polarity gray scale voltage and the negative polarity gray scale voltage respectively.

22. The display device according toclaim 17, wherein the adjacent two pixels on the display panel connected to the adjacent two scan lines have polarity different from each other.

23. A display device comprising:

a display panel having a plurality of pixels;

a driver being arranged on a single side of the display panel;

wherein the driver has output terminals provided for data lines connected to pixels and outputs gray scale voltages corresponding to display data for each pixel consisting of a plurality of bits to the pixel from the output terminal via the data line, and a polarity of the gray scale voltage output from the output terminal at an odd-numbered position is different from a polarity of the gray scale voltage output from the output terminal at an even-numbered position,

wherein the driver includes:

a first amplifier for outputting a positive polarity gray scale voltage corresponding to the display data to the odd-numbered position output terminal;

a second amplifier for outputting a negative polarity gray scale voltage corresponding to the display data to the even-numbered position output terminal; and

a selector for switching an output destination of the positive polarity gray scale voltage output from the first amplifier between the odd-numbered position output terminal and the even-numbered position output terminals while switching an output destination of the negative polarity gray scale voltage output from the second amplifier between the even-numbered position output terminal and the odd number position output terminal;

wherein the polarity of the voltage of the pixel connected with the odd-numbered position output terminal via the data line is different from the polarity of the voltage of the pixel connected with the even-numbered position output terminal via the data line.

24. The display device according toclaim 23, wherein a pair of the first amplifier and the second amplifier is shared by the odd-position numbered output terminal and the even-numbered position output terminal adjacent to each other.

25. The display device according toclaim 23, wherein the selector switches the output destination of the positive polarity gray scale voltage output from the first amplifier and also switches the output destination of the negative polarity gray scale voltage output from the second amplifier in accordance with an AC switching signal.

26. The display device according toclaim 23, wherein the driver further includes:

a first latch for holding the input display data;

a second latch for collectively holding the display data in the first latch according to a timing signal; and

a selection circuit for selecting one of a plurality of gray scale voltages as the gray scale voltage corresponding to the display data in the second latch.

27. The display device according toclaim 23, wherein the first amplifier and the second amplifier simultaneously output the positive polarity gray scale voltage and the negative polarity gray scale voltage respectively.

28. A display device, which inverts polarity of voltage at pixels every row or dot, comprising:

a display panel having a plurality of pixels arranged corresponding to crossing points of a plurality of data lines and a plurality of scan lines; and

a driver being arranged on a single side of the display panel for outputting gray scale voltages corresponding to display data consisting of a plurality bits to the pixels via the data lines;

wherein the driver includes:

output terminals provided corresponding to the data lines;

amplifiers provided corresponding to the output terminals for outputting the gray scale voltage corresponding to the display data; and

a selector for switching a connection between the amplifier and the output terminal;

wherein the adjacent two amplifiers are shared by the adjacent two output terminals; and

wherein the selector switches the connections between the adjacent two amplifiers and the adjacent two output terminals with each other.

29. The display device according toclaim 28, wherein the driver further includes:

a first latch for holding the input display data;

a second latch for collectively holding the display data in the first latch according to a timing signal; and

a selection circuit for selecting one of a plurality of gray scale voltages as the gray scale voltage corresponding to the display data in the second latch;

wherein the amplifier is input with the gray scale voltage from the selection circuit.

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