USRE40423E1 - Multiport RAM with programmable data port configuration - Google Patents

Abstract

A RAM with programmable data port configuration provides for programmable configuration of RAM data ports, and in the case of a multiport RAM, for independent programmable configuration of each data port. A single programmable RAM cell can be utilized in a variety of data port configurations, thereby reducing the number of combinations necessary in a standard cell library or gate array in implement the every possible configuration. In one embodiment of the invention, a dual port RAM is provided with a decoder, an input multiplexer and an output multiplexer for each data port. The input multiplexer for each data port provides several different selectable mappings of a RAM input word of varying sizes to the input bit lines of the respective data port. Similarly, the output multiplexer for each data port provides several different selectable mappings of the RAM output bit lines to the RAM output word. The decoder receives configuration programming bits to determine the appropriate size of the RAM input and output word for the respective port, and based on column addressing bits, outputs a select signal to select the appropriate mapping from the input and output multiplexers. Decoding circuitry is used during RAM write operations to disable those input bits not addressed.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to the field of digital electronics, and more particularly to random access memory (RAM) data ports.

2. Description of the Related Art

In the prior art, data input/output (I/O) functions for memory cells in integrated circuits (ICs) have been confined to fixed-width word-length operations. For example, applications involving the use of an eight-bit data word utilize a memory cell having an eight-bit data port, and applications involving a sixteen-bit data word utilize a different memory cell with a hardwired sixteen-bit data port. This specificity of memory cells based on word length prevents the widespread application and re-use of general memory configurations.

In the construction of electronic circuits, many skilled practitioners use what are referred to as “standard cells” to build their circuits. These standard cells are predesigned circuit building blocks resident in a library of such building blocks. Because the standard cells are individually designed and tested before they are added to the library, performance characteristics for the standard cells are predictable. Using predesigned standard cells can reduce the amount of time between conception of a circuit design and production of a working circuit prototype.

Similarly, many designers use programmable gate arrays (PGAs) to implement digital circuit designs. Gate arrays are integrated circuits with standard logic cells (e.g., NAND gates, NOR gates, registers, etc.) already resident in an integrated circuit. Typically, gate array ICs include thousands of these individual cells with mechanisms for interconnecting the cells. The designer merely identifies the interconnection of the resident logic cells to implement his circuit design. The mechanism for interconnecting the cells may be a one-time fuse mechanism, or a programmable mechanism allowing for reuse of the gate array IC in another design.

For instance, using a field-programmable gate array (FPGA), such as one from the XILINX product line, an erasable programmable ROM chip (EPROM) or electrically erasable programmable ROM chip (EEPROM) may be used to store the programmable configuration information for one or more PGAs. To implement a new logic design on the same PGAs, the designer erases the EPROM and loads in a new set of configuration information. During the startup cycle, the PGAs adopt the new configuration by interconnecting the logic cells based on the new configuration information. Using computer aided design (CAD) tools to generate the configuration information, a recursive design process can cycle from one working design implementation to a revised working design implementation in as little time as a single day.

One drawback of gate arrays is that the number of logic cells of any particular type (e.g., NAND gate, eight-bit shift register, etc.) is fixed. For larger sized cells such as RAM (random access memory) cells, this limitation is of greater concern, because of the relatively fewer number of such cells. It is therefore beneficial to make these larger sized cells as generic as possible to increase their utility for different design needs.

With respect to RAM cells, different applications entail different RAM configurations, e.g., eight-bit word access, sixteen-bit word access, serial (one-bit) access, etc. For this reason, many gate arrays and standard cell libraries include cells of each type to serve all applications. Unfortunately, the unused configurations in a gate array constitute wasted IC area that could be utilized for other needed logic cells.

In the prior art, dual port RAM circuits have been used to increase the utility of the RAM. Examples of dual port RAM for use in video systems are U.S. Pat. Nos. 4,633,441; 4,799,053; and 5,195,056 to Ishimoto, Van Aken et al., and Pinkham et al., respectively. A dual port RAM circuit has two data ports for accessing the contents of the RAM.

In a dual port RAM, the ports may have the same or different data widths. For instance, a dual port RAM may have a first port providing eight-bit access and a second port providing one-bit or serial access to the same memory. This configuration is useful for applications requiring both byte access and serial access, such as for parallel-to-serial and serial-to-parallel conversion. However, other applications may require different configurations. For example, in a video application, a designer may require a first port providing thirty-two-bit access to write pixel data and a second port providing eight-bit access for reading out eight-bit segments of pixel RGB data. In the prior art, the eight-bit/one-bit dual port RAM cell cannot be used in the thirty-two-bit/eight-bit configuration needed in the video application.

Dual port RAM cells provide an improvement in the manner in which memory is accessed. However, designers are limited to the fixed-width configuration available in the hardwired circuit, or else an application specific circuit must be designed to provide the needed configuration. Further, it is inefficient in the standard cell and gate array environments to provide for dual port RAM cells of each possible dual port combination.

SUMMARY OF THE INVENTION

The present invention is a RAM with programmable data port configuration. Whereas prior art RAM cells or arrays have hardwired data ports of fixed sizes, the invention provides for programmable configuration of RAM data ports, and in the case of a multiport RAM, for independent programmable configuration of each data port. A single programmable RAM cell can be utilized in a variety of data port configurations, reducing the number of combinations necessary in a standard cell library or gate array to implement every possible configuration.

In one embodiment of the invention, a dual port RAM is provided with a decoder, an input multiplexer and an output multiplexer for each data port. The input multiplexer for each data port provides several different selectable mappings of a RAM input word of varying sizes to the input bit lines of the respective data port. Similarly, the output multiplexer for each data port provides several different selectable mappings of the RAM output bit lines to the RAM output word. The decoder receives configuration programming bits to determine the appropriate size of the RAM input and output word for the respective port, and based on column addressing bits, outputs a select signal to select the appropriate mapping from the input and output multiplexers. Further decoding circuitry is used during RAM write operations to disable those input bits not addressed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a dual port RAM with programmable data port configuration according to an embodiment of the invention.

FIG. 2 is a block diagram of a single programmable data port according to an embodiment of the invention.

FIG. 3 is a circuit diagram of a four-to-one multiplexer suitable for the embodiment of FIG.2.

FIG. 4 is logic diagram of a selection decoder suitable for the embodiment of FIG.2.

FIG. 5 is a diagram of an 8×4 RAM structure illustrating addressing for several configurations.

DETAILED DESCRIPTION OF THE INVENTION

A RAM with programmable data port configuration is described. In the following description, numerous specific details are set forth to provide a more thorough description of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without these specific details. In other instances, well known features have not been described in detail so as not to obscure the present invention.

In an embodiment of the invention, a RAM structure, or cell, is provided with one or more data ports having a programmably configurable data width. Whereas RAM structures of the prior art are limited to a hardwired data width, precluding the use of the same structure or design for applications of different data widths, the invention provides for a single RAM structure to be utilized in a plurality of programmable data width configurations. In a multiport embodiment of the invention, each data port is independently configurable providing for broad use of the RAM design in many different applications. Standard cell and gate array environments are able to provide a single programmable RAM cell design where, in the prior art, many fixed data width RAM cells were required.

FIG. 1 is a top level block diagram of a dual port RAM structure having programmably configurable data ports. InFIG. 1,dual port RAM100 comprises a first input/output (I/O) data port havinginput bus108,output bus109 andaddress bus106; and a second I/O data port havinginput bus117,output bus118 andaddress bus115. In some embodiments of the invention, however, one or more data ports may be read-only or write-only, comprising only an input multiplexer or an output multiplexer.

PortB input multiplexer101 is coupled toinput bus108 andexternal input bus103. PortB output multiplexer102 is coupled tooutput bus109 andexternal output bus105. In addition,input multiplexer101 andoutput multiplexer102 receiveselect signal120 fromdecoder119.Decoder119 receives loworder address bits104 andconfiguration bits107.

Port Ainput multiplexer110 is coupled toinput bus117 andexternal input bus112. Port Aoutput multiplexer111 is coupled tooutput bus118 andexternal output bus114. In addition,input multiplexer110 andoutput multiplexer111 receiveselect signal122 fromdecoder121.Decoder121 receives lowerorder address bits113 andconfiguration bits116.

Buses108,109,117 and118 have a fixed width according to the hardwired physical characteristics ofdual port RAM100.Address bus106 comprises address bit lines ADDB0, ADDB1, . . . ADDBj, which are sufficient to provide unique addresses for memory words indual port RAM100 of the width provided bybuses108 and109.Address bus115 contains address bit lines ADDA0, ADDA1, . . . ADDAk, which are sufficient to address memory words indual port RAM100 having a width corresponding tobuses117 and118.

External input bus103 contains data input lines DINB0, DINB1, . . . DINBm, to form a bus width of the same size asbus108 or smaller. Similarlyexternal input bus112 contains input lines DINA0, DINA1, . . . DINAn, to provide a bus having a width corresponding to the width ofbus117 or smaller.External output bus105 consists of bit lines DOUTB0, DOUTB1, . . . DOUTBm, to form a bus having a width having of the same size asbus109 or smaller. Similarly,external output bus114 consists of output bit lines DOUTA0, DOUTA1, . . . DOUTAn, to form a bus width of the same size asbus118 or smaller.

Typically, the configurable external bus width has a maximum value of the fixed internal bus width. Other possible programmable configurations are typically equal to the maximum bus width divided by a power of two. For example, if the internal fixed bus width is sixteen bits, common programmable external configurations are sixteen bits, eight bits, four bits, two bits and one bit. However, other configurations are also possible (e.g., twenty-four internal bits configured to twenty-four, eight, four or one external bits).

Configuration bits107 are provided on control lines for selecting between possible port configurations. For example, two configuration bits can be used to provide four different port configurations, such as for one bit, two bit, four bit and eight bit wide configurations. Three configuration bits are sufficient to support eight different configurations, etc. Similarly,configuration bits116 are provided on control lines for port A. Lowerorder address bits104 provide for selection of data bit subsets frombuses108 and109. Similarly, lowerorder address bits113 provide for selection of data bit subsets frombuses117 and118. The number of lower address bits is at least equal to log₂of the internal fixed bus width divided by the minimum external bus width.

Multiplexers101,102,110 and111 provide for mapping of the bit lines between the external buses and the respective internal buses to implement the desired configurations.Decoders119 and122 independently select the appropriate mapping from their associated multiplexers based on the respective port configuration bits, and the lower order (or column) address bits when applicable.

The configuration bits may be stored in an external memory circuit such as an EPROM, or the configuration bits may be stored in a local register. Further, the configuration bits may be set once at startup, or they may be set and reset during circuit operation to provide the utility of the different configurations while the circuit is operating. The independent programmability of each port provides a versatility advantage over memory circuits of the prior art.

FIG. 5 illustrates an addressing scheme for an eight by four RAM cell. The RAM contains eight rows (0-7) of memory words having four memory bits, B0 through B3. Row address bits A₁, A₂and A₃are used to specify one row from the eight possible rows within the RAM. A₁is the most significant row address bit, and A₃is the least significant row address bit. Column address bits CA0 and CA1 are used to specify particular columns of the RAM. CA0 is the most significant column address bit, and is used to separate the RAM into a least significant two-bit column comprising bits B0 and B1, and a most significant two-bit column comprising bits B2 and B3. CA1 is used to specify a single bit column within each two-bit column specified by CA0. Further column address bits are used to further subdivide larger RAM configurations.

TABLE 1
GENERAL MAPPING TABLE (×4, ×2, ×1)

	MEM1	MEM2	CA0	CA1	D0	D1	D2	D3
	0	0	X	X	B0	B1	B2	B3
	0	1	0	X	B0	B1	X	X
	0	1	1	X	B2	B3	X	X
	1	0	X	X	X	X	X	X
	1	1	0	0	B0	X	X	X
	1	1	0	1	B1	X	X	X
	1	1	1	0	B2	X	X	X
	1	1	1	1	B3	X	X	X
	(X = Don't care conditions)

Table 1 is a mapping diagram for a four-bit internal RAM port with programmable configurations for four-bit wide access (×4), two-bit wide access (×2), and one-bit wide or serial access (×1). D0-D3 represent the bit lines of the external port (input and output) of the programmable RAM. B0-B3 represent the fixed internal bit lines (input and output) of the programmable RAM. MEM1 and MEM2 are the configuration bit values, and CA0 and CA1 are the low order (or column) address bit values for the configurations which require finer addressing.

Table 1 contains many “don't care” conditions that allow for variations in the implementation of the data port. In general, multiplexers are used to provide the selectable paths by which the internal and external bit lines are coupled. A decoder is used to control the multiplexers based on the inputs MEM1, MEM2, CA0 and CA1, such that the definitions of Table 1 are implemented.

TABLE 2
MAPPING TABLE FOR EMBODIMENT OFFIG. 2

MEM1	MEM2	CA0	CA1	D0	D1	D2	D3
0	0	X	X	B0	B1	B2	B3	S0
0	1	0	X	B0	B1	B2	B3	S0
0	1	1	X	B2	B3	B0	B1	S2
1	0	X	X	X	X	X	X	—
1	1	0	0	B0	B1	B2	B3	S0
1	1	0	1	B1	B2	B3	B0	S1
1	1	1	0	B2	B3	B0	B1	S2
1	1	1	1	B3	B0	B1	B2	S3

Table 2 is an embodiment of Table 1 wherein the “don't care” conditions have been filled in to provide for assignment of the general bit mappings of Table 1 to four particular bit mappings for one embodiment of the programmable four-bit data port. The four particular bit mappings are labelled as S0-S3, and correspond to particular select signals output from a decoder in the implementation shown in FIG.2.

FIG. 2 is a bit level block diagram of an embodiment for one port of a RAM device having programmable configuration capabilities as defined in Table 2. In the embodiment ofFIG. 2, the hardwired width ofRAM port200 is four bits wide. Address lines A1, A2, . . . An are provided to RAMport200 to address the four bit words from the RAM device. Multiplexers (MUXs)202,204,206 and208 are used to map the four bits of the output word comprising bits BO-0, BO-1, BO-2, and BO-3 to the external output word comprising bits DO-0, DO-1, DO-2 and DO-3.Multiplexers203,204,207 and209 are used to map the four bits of the external word comprising DI-0, DI-1, DI-2 and DI-3 to the RAM port input word comprising bits BI-0, BI-1, BI-2 and BI-3.

Each bit level multiplexer has four inputs, I0-I3, and one output,O. Select signal210 is provided to each multiplexer (202-209) to select from the four inputs (I0-I3) the appropriate signal to pass to the output (O). The composition ofselect signal210 is determined by what is appropriate to drive the selected implementation of multiplexers202-209. In this embodiment, the selection of MUX input I0 from each multiplexer corresponds to decode selection S0, the selection of all I1 inputs corresponds to selection S1, etc.Input multiplexers203,205,207, and209 provide the RAM port input signals BI-0, BI-1, BI-2 and BI-3, respectively.Output multiplexers202,204,206 and208 provide output signals DO-0, DO-1, DO-2 and DO-3, respectively.

RAM port output signal BO-0 is coupled to input I0 ofMUX202, input I3 ofMUX204, input I2 ofMUX206 and input I1 ofMUX208. RAM port output signal BO-1 is coupled to input I1 ofMUX202, input I0 ofMUX204, input I3 ofMUX206 and input I2 ofMUX208. RAM port output signal BO-2 is coupled to input I2 ofMUX202, input I1 ofMUX204, input I0 ofMUX206 and input I3 ofMUX208. RAM port output signal BO-3 is coupled to input I3 ofMUX202, input I2 ofMUX204, input I1 ofMUX206 and input I0 ofMUX208.

External input signal DI-0 is coupled to input I0 ofMUX203, input I1 ofMUX205, input I2 ofMUX207 and input I3 ofMUX209. External input signal DI-1 is coupled to input I3 ofMUX203, input I0 ofMUX205, input I1 ofMUX207 and input I2 ofMUX209. External input DI-2 is coupled to input I2 ofMUX203, input I3 ofMUX205, input I0 ofMUX207 and input I1 ofMUX209. External input DI-3 is coupled to input signal I1 ofMUX203, input I2 ofMUX205, input I3 ofMUX207 and input I0 ofMUX209.

Decoder201 receives configuration signals MEM1 and MEM2 to select from three possible configurations, i.e., one-bit, two-bit and four-bit wide operations. Lower order address bits CA0 and CA1 are provided todecoder201 for addressing within the four-bit word for the one-bit wide and two-bit wide configurations. Also, further decoding circuitry acts to disable unselected RAM port input lines during write operations. The enable/disable signals are represented inFIG. 2 byline211coupling decoder201 toRAM port200.

In general, the embodiment ofFIG. 2 operates by steering the data inputs and outputs of theRAM port200 to different external ports via the multiplexers, depending on the selected configuration of the RAM (MEM1 and MEM2) and the low order address bits (or column address bits) CA0 and CA1. TheRAM port200 is internally configured as four-bit wide data words, but by use of the steering circuitry, the RAM may be accessed as a two-bit wide word or as a single bit for serial purposes. The configuration of the RAM data port inFIG. 2 is controlled by configuration bits MEM1 and MEM2 as follows:

MEM1	MEM2	Configuration
1	1	×1
0	0	×4
0	1	×2
1	0	Unused

For other embodiments, the configuration (MEM1,MEM2)=(1,0) is used to specify a fourth configuration. More configuration bits may be used to increase the number of possible configurations further.

When the RAM configuration bits MEM1 and MEM2 are set to the four-bit wide (×4) configuration, the column address bits CA0 and CA1 are not used in the decoding process because all bits are selected.Decoder201 selects the I0 input of multiplexers202-209 viaselect signal210.Multiplexers202,204,206 and208 steer internal output port signals BO-0 through BO-3 to external output ports DO-0 through DO-3, respectively.Multiplexers203,205,207 and209 steer external input port signals DI-0 through DI-3 to internal input ports BI-0 through BI-3, respectively. Thus, when the four-bit wide configuration is selected, the multiplexers pass the RAM inputs and outputs directly through without remapping.

When the RAM configuration bits are set to the two-bit wide (×2) configuration, column address bit CA0 is used to select from the two two-bit words at each row address. Address bit CA1 is unused.Decoder201 selects mapping S0, or all I0 inputs, when CA0 is “0” to couple the two least significant bits (B0, B1) of the internal buses to the two least significant bits (D0, D1) of the external buses. Similarly,decoder201 selects mapping S2, or all I2 inputs, when CA0 is “1” to couple the two most significant bits (B2, B3) of the internal buses to the two least significant bits of the external bus (D0, D1). Only the two lease significant bits are used to access the RAM in the (×2) configuration of this implementation. Alternatively, two other bits of the external bus may be used to access the selected two bits from the internal bus.

When the RAM configuration bits are set to the one-bit wide (×1) or serial configuration, column address bits CA0 and CA1 are used to address the individual bits in the four-bit word selected by address A0-An. Only one bit line on the external buses is used to access data. In this embodiment, the access line is the least significant external bit line. When (CA0, CA1) is (0,0),decoder201 selects mapping S0, or all I0 inputs, to couple the least significant internal bit line (B0) to the least significant external bit line (D0). When (CA0,CA1) is (0,1),decoder201 selects mapping S1, or all I1 inputs, to couple the second least significant internal bit line (B1) to the least significant external bit line (D0). When (CA0,CA1) is (1,0),decoder201 selects mapping S2, or all I2 inputs, to couple the second most significant internal bit line (B2) to the least significant external bit line (D0). Finally, when (CA0,CA1) is (1,1),decoder201 selects mapping S3, or all I3 inputs, to couple the most significant internal bit line (B3) to the least significant external bit line (D0). Thus, each bit of the four-bit internal word is addressable.

The embodiment ofFIG. 2 is easily expanded for larger internal words and more possible configurations. It will also be obvious to one skilled in the art that multiplexer/decoder embodiments can be used to implement the mappings of Table 1. For example, at the cost of modifying the decoder, another embodiment may comprise a four to one multiplexer for coupling internal bit lines to external bit line D0, a two to one multiplexer for coupling only internal bit lines B1 and B3 to external bit line D1, and direct connections for coupling internal bit line B2 to external bit line D2 and internal bit line B3 to external bit line D3.

FIG. 3 is a circuit diagram of one embodiment of a four to one multiplexer suitable for use in the circuit of FIG.2. Input signals I0, I1, I2 and I3 are provided toinverters300,301,302 and303, respectively. I0′, the output ofinverter300, is provided to the transmission gate formed byNMOS transistor304 and parallel withPMOS transistor305. I1′, the output ofinverter301, is provided to the transmission gate formed byNMOS307 in parallel withPMOS transistor308. I2′, the output ofinverter302, is provided to the transmission gate formed byNMOS transistor310 and parallel withPMOS311. I3′, the output ofinverter303, is provided to the transmission gate formed byNMOS transistor313 in parallel withPMOS314. The output line of the transmission gates are joined at node316 (O′), which in turn is coupled to the input terminal ofinverter317. Theinverter317 provides signal318 (O).

Select signal S0 is provided to the gate ofNMOS transistor304, and throughinverter306 to the gate ofPMOS transistor305. Select signal S1 is provided to thegate NMOS transistor307 and throughinverter309 to the gate ofPMOS transistor308. Select signal S2 is provided to the gate ofNMOS transistor310 and throughinverter312 to the gate ofPMOS transistor311. Select signal S3 is provided to the gate ofNMOS transistor313 and throughinverter315 to the gate ofPMOS transistor314.

The transmission gates formed by the complimentary NMOS and PMOS transistors provide a closed circuit when the associated select signal is asserted. When the associated select signal is not asserted, the transmission gate provides an open circuit. By asserting only one select signal at any moment in time, multiplexing of the four input values to a single output value is achieved. Inverters300-303 and317 provide buffering for the transmission function, but are unnecessary when the transmission gates are formed from logic having built-in sourcing and sinking capabilities.

FIG. 4 is a logic level diagram of one embodiment of a decoder for the example of FIG.2. The decoding function provided is defined by Table 2, with select signals S0-S3 corresponding to bit mappings S0-S3. InFIG. 4, configuration signals MEM1 and MEM2 are coupled toinverters400 and401 respectively to provide signals MEM1′ and MEM2′. Similarly, lower order address bits CA0 and CA1 are provided toinverters402 and403, respectively, to provide signals CA0′ and CA1′.

NAND gates404 and405 and NORgate406 provide decoding of the input signals to generate select signal S3.NAND gate404 receives as input signals MEM2 and CA1.NAND gate405 receives as input signals MEM1 and CA0.Output signal416 fromNAND gate404 and output signal417 fromNAND gate405 are provided as input signals to NORgate406. The output signal of NORgate406 is select signal S3.

NAND gate407 and NORgates408 and409 provide decoding of the input signals to generate select signal S2. NAND gate receives as input signals MEM2 and CA1. NORgate408 receives as signals MEM1′ and CA0′.Output signal418 fromNAND gate407 and output signal419 from NORgate408 are provided as input signals to NORgate409. The output signal of NORgate409 is select signal S2.

NAND gates410 and411 and NORgate412 provide decoding of the input signals to generate select signal S1.NAND gate410 receives as input signals MEM2 and CA1′.NAND gate411 receives as input signals MEM1 and CA0.Output signal420 fromNAND gate410 and output signal421 fromNAND gate411 are provided as input signals to NORgate412. The output signal of NORgate412 is select signal S1.

NORgates413,414 and415 provide decoding of the input signals to generate select signal S0. NORgate413 receives as input signals MEM2′ and CA1′. NORgate414 receives as input signals MEM1′ and CA0′.Output signal422 from NORgate413 and output signal423 from NORgate414 are provided as input signals to NORgate415. The output signal of NORgate415 is select signal S0.

TABLE 3
WRITE ENABLE CONTROLS

				BI-0/	BI-1/	BI-2/	BI-3/
MEM1	MEM2	CA0	CA1	EN	EN	EN	EN
0	0	X	X		1	1	1	1
0	1	0	X	1	1	0	0
0	1	1	X	0	0	1	1
1	0	X	X		0	0	0	0
1	1	0	0	1	0	0	0
1	1	0	1	0	1	0	0
1	1	1	0	0	0	1	0
1	1	1	1	0	0	0	1
(X = Don't care conditions)

For configurations in which a writing operation writes information to only a portion of the internal data word, the unselected portion of the internal data word is disabled to prevent the undesired writing over of underlying data. For this purpose, the RAM may be designed with individual “write enable” control of the internal bit lines or of the smallest selectable unit of the internal word. A decoding operation similar to that outlined inFIG. 4 is used to enable and disable the internal bit lines as necessary. Table 3 defines the enabling of bit lines BI-0 through BI-3 to correspond to the selection definitions of Table 1.

The contents of Table 3 can be reduced to the following Boolean equations:
BI-0/EN=(MEM1′ MEM2′)+(CA0′ MEM1′)+(MEM2 CA0′ CA1′)
BI-1/EN=(MEM1′ MEM2′)+(CA0′ MEM1′)+(MEM2 CA0′ CA1)
BI-2/EN=(MEM1′ MEM2′)+(CA0 MEM1′)+(MEM2 CA0 CA1′)
BI-3/EN=(MEM1′ MEM2′)+(CA0 MEM1′)+(MEM2 CA0 CA1)

Combinational logic for implementing the above decoding equations enables each bit line on the internal RAM input bus as appropriate based on the combination of signals MEM1, MEM2, CA0 and CA1. A similar derivation is performed to provide enabling/disabling write circuitry for other embodiments.

Thus, a multiport RAM with programmable data port configuration has been described.

Claims (18)

1. A circuit for programmably configuring a data port having a fixed word length M, comprising:

a multiplexer circuit coupled to a data port, said multiplexer circuit having a selectable electronic mapping between said data port and a second port of programmable word-length N where N is less than or equal to M, said multiplexer circuit responsive to a select signal; and

a decoder having a configuration input and an address input, said decoder generating said select signal.

2. The circuit for programmably configuring a data port ofclaim 1 wherein M divided by N is a multiple of two.

3. The circuit for programmably configuring a data port ofclaim 1 wherein said programmable word-length N is dependent on said configuration input.

4. The circuit for programmably configuring a data port ofclaim 3 wherein said configuration input is received from a register having configuration bits stored therein.

5. The circuit for programmably configuring a data port ofclaim 3 wherein said configuration input is received from a ROM having configuration bits stored therein.

6. The circuit for programmably configuring a data port ofclaim 1 wherein said decoder selects an N-bit word from said M-bit data port based on said address input.

7. The circuit for programmably configuring a data port ofclaim 1 wherein said multiplexer circuit comprises:

an input multiplexer coupled to said data port and said select signal, said input multiplexer selectably configured to map input data words of word-length N from said second port into said data port; and

an output multiplexer coupled to said data port and said select signal, said output multiplexer selectably configured to map output data words of word-length M from said data port into said second port.

8. The circuit for programmably configuring a data port ofclaim 1 wherein said data port is part of a memory circuit, and wherein said decoder further comprises:

a decoding circuit coupled to said data port, wherein said decoding circuit is configured to selectively disable a write operation for a portion of said data port based on said configuration input and said address input.

9. A multiport RAM with programmable data port configuration, comprising:

a first internal data port of fixed width M;

a second internal data port of fixed width N;

a first multiplexer circuit coupled to said first internal data port, said first multiplexer circuit having a selectable electronic mapping between said first internal data port and a first external data port of programmable width X where X is less than or equal to M, said first multiplexer circuit responsive to a first select signal;

a second multiplexer circuit coupled to said second internal data port, said second multiplexer circuit having a selectable electronic mapping between said second internal data port and a second external data port of programmable width Y where Y is less than or equal to N, said second multiplexer circuit responsive to a second select signal;

a first decoder having a first configuration input and a first address input, said first decoder generating said first select signal; and

a second decoder having a second configuration input and a second address input, said second decoder generating said second select signal.

10. The circuit multiport RAM ofclaim 9 wherein M divided by X is a multiple of two.

11. The circuit multiport RAM ofclaim 9 wherein said programmable width X is dependent on said first configuration input, and said programmable width Y is dependent on said second configuration input.

12. The circuit multiport RAM ofclaim 11 wherein said first configuration input and said second configuration input are received from at least one register having configuration bits stored therein.

13. The circuit multiport RAM ofclaim 11 wherein said first configuration input and said second configuration input are received from a ROM having configuration bits stored therein.

14. The circuit multiport RAM ofclaim 9 wherein said first decoder selects an X-bit word from said first internal data port based on said first address input, and said second decoder selects a Y-bit word from said second internal data port based on said second address input.

15. The circuit multiport RAM ofclaim 9 wherein said first multiplexer circuit comprises:

an input multiplexer coupled to said first internal data port and said first select signal, said input multiplexer selectably configured to map input data words of width X from said first external data port into said first internal data port; and

an output multiplexer coupled to said first internal data port and said first select signal, said output multiplexer selectably configured to map output data words of width M from said first internal data port into said first external data port.

16. The circuit multiport RAM ofclaim 9 wherein said second multiplexer circuit comprises:

an input multiplexer coupled to said second internal data port and said second select signal, said input multiplexer selectably configured to map input data words of width Y from said second external data port into said second internal data port; and

an output multiplexer coupled to said second internal data port and said second select signal, said output multiplexer selectably configured to map output data words of width N from said second internal data port into said second external data port.

17. The circuit multiport RAM ofclaim 9 wherein each of said first and second decoders further comprise:

a decoding circuit coupled to a respective internal data port, wherein said decoding circuit is configured to selectively disable a write operation for a portion of said respective internal data port based on a respective configuration input and a respective address input.

18. The circuit multiport RAM ofclaim 9 wherein X and Y are independently programmable.

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